Get rid of unused lock code.
--HG-- extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
This commit is contained in:
Steve Reinhardt
parent
34924ce3b8
commit
cdc3e5bc22
3 changed files with 0 additions and 242 deletions
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@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
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}
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}
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#endif
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#endif
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/** Old CPU read from memory function. No longer used. */
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template <class T>
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Fault read(Request *req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->isLocked()) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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if (req->isLocked()) {
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lockAddrList.insert(req->paddr);
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lockFlag = true;
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}
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#endif
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Fault error;
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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/** CPU read function, forwards read to LSQ. */
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/** CPU read function, forwards read to LSQ. */
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template <class T>
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template <class T>
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Fault read(Request *req, T &data, int load_idx)
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Fault read(Request *req, T &data, int load_idx)
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@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
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return backEnd->read(req, data, load_idx);
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return backEnd->read(req, data, load_idx);
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}
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}
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/** Old CPU write to memory function. No longer used. */
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template <class T>
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Fault write(Request *req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->isLocked()) {
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xc = req->xc;
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if (req->isUncacheable()) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->threadContexts.size(); i++){
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xc = this->system->threadContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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if (req->isLocked()) {
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if (req->isUncacheable()) {
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req->result = 2;
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} else {
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if (this->lockFlag) {
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if (lockAddrList.find(req->paddr) !=
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lockAddrList.end()) {
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req->result = 1;
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} else {
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req->result = 0;
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return NoFault;
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}
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} else {
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req->result = 0;
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return NoFault;
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}
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}
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}
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#endif
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return this->mem->write(req, (T)htog(data));
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}
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/** CPU write function, forwards write to LSQ. */
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/** CPU write function, forwards write to LSQ. */
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template <class T>
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template <class T>
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Fault write(Request *req, T &data, int store_idx)
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Fault write(Request *req, T &data, int store_idx)
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@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
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*/
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*/
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return fault;
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return fault;
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}
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}
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#if 0
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template <class Impl>
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template <class T>
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Fault
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InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->isLocked()) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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Fault error;
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error = thread->mem->read(req, data);
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data = LittleEndianGuest::gtoh(data);
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return error;
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}
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#endif
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template <class Impl>
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template <class Impl>
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template <class T>
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template <class T>
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@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
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*/
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*/
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return fault;
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return fault;
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}
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}
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#if 0
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template <class Impl>
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template <class T>
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Fault
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InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->isLocked()) {
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xc = req->xc;
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if (req->isUncacheable()) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < cpu->system->execContexts.size(); i++){
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xc = cpu->system->execContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
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}
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#endif
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template <class Impl>
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template <class Impl>
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template <class T>
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template <class T>
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@ -232,75 +232,6 @@ class SimpleThread : public ThreadState
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/// Set the status to Halted.
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/// Set the status to Halted.
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void halt();
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void halt();
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/*
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template <class T>
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Fault read(RequestPtr &req, T &data)
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{
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#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
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if (req->isLocked()) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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Fault error;
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error = mem->prot_read(req->paddr, data, req->size);
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data = LittleEndianGuest::gtoh(data);
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return error;
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}
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template <class T>
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Fault write(RequestPtr &req, T &data)
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{
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#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->isLocked()) {
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xc = req->xc;
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if (req->isUncacheable()) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < system->execContexts.size(); i++){
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xc = system->execContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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return mem->prot_write(req->paddr, (T)htog(data), req->size);
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}
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*/
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virtual bool misspeculating();
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virtual bool misspeculating();
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Fault instRead(RequestPtr &req)
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Fault instRead(RequestPtr &req)
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