Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst.
src/arch/x86/predecoder.cc: Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes. --HG-- extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
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@ -69,9 +69,9 @@ namespace AlphaISA
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//Use this to give data to the predecoder. This should be used
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//Use this to give data to the predecoder. This should be used
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//when there is control flow.
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//when there is control flow.
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void moreBytes(Addr pc, Addr off, MachInst inst)
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void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst)
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{
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{
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fetchPC = pc;
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fetchPC = _fetchPC;
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assert(off == 0);
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assert(off == 0);
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ext_inst = inst;
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ext_inst = inst;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -80,13 +80,6 @@ namespace AlphaISA
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#endif
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#endif
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}
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}
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//Use this to give data to the predecoder. This should be used
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//when instructions are executed in order.
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void moreBytes(MachInst machInst)
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{
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moreBytes(fetchPC + sizeof(machInst), 0, machInst);
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}
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bool needMoreBytes()
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bool needMoreBytes()
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{
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{
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return true;
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return true;
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@ -66,19 +66,12 @@ namespace MipsISA
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//Use this to give data to the predecoder. This should be used
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//Use this to give data to the predecoder. This should be used
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//when there is control flow.
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//when there is control flow.
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void moreBytes(Addr currPC, Addr off, MachInst inst)
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void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
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{
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{
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assert(off == 0);
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assert(off == 0);
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emi = inst;
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emi = inst;
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}
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}
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//Use this to give data to the predecoder. This should be used
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//when instructions are executed in order.
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void moreBytes(MachInst machInst)
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{
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moreBytes(0, 0, machInst);
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}
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bool needMoreBytes()
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bool needMoreBytes()
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{
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{
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return true;
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return true;
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@ -67,7 +67,7 @@ namespace SparcISA
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//Use this to give data to the predecoder. This should be used
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//Use this to give data to the predecoder. This should be used
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//when there is control flow.
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//when there is control flow.
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void moreBytes(Addr currPC, Addr off, MachInst inst)
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void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
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{
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{
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assert(off == 0);
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assert(off == 0);
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@ -85,13 +85,6 @@ namespace SparcISA
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<< (sizeof(MachInst) * 8));
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<< (sizeof(MachInst) * 8));
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}
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}
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//Use this to give data to the predecoder. This should be used
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//when instructions are executed in order.
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void moreBytes(MachInst machInst)
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{
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moreBytes(0, 0, machInst);
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}
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bool needMoreBytes()
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bool needMoreBytes()
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{
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{
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return true;
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return true;
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@ -209,34 +209,38 @@ namespace X86ISA
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//Figure out the effective operand size. This can be overriden to
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//Figure out the effective operand size. This can be overriden to
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//a fixed value at the decoder level.
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//a fixed value at the decoder level.
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int logOpSize;
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if(/*FIXME long mode*/1)
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if(/*FIXME long mode*/1)
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{
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{
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if(emi.rex && emi.rex.w)
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if(emi.rex.w)
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emi.opSize = 3; // 64 bit operand size
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logOpSize = 3; // 64 bit operand size
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else if(emi.legacy.op)
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else if(emi.legacy.op)
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emi.opSize = 1; // 16 bit operand size
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logOpSize = 1; // 16 bit operand size
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else
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else
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emi.opSize = 2; // 32 bit operand size
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logOpSize = 2; // 32 bit operand size
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}
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}
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else if(/*FIXME default 32*/1)
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else if(/*FIXME default 32*/1)
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{
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{
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if(emi.legacy.op)
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if(emi.legacy.op)
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emi.opSize = 1; // 16 bit operand size
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logOpSize = 1; // 16 bit operand size
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else
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else
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emi.opSize = 2; // 32 bit operand size
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logOpSize = 2; // 32 bit operand size
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}
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}
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else // 16 bit default operand size
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else // 16 bit default operand size
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{
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{
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if(emi.legacy.op)
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if(emi.legacy.op)
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emi.opSize = 2; // 32 bit operand size
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logOpSize = 2; // 32 bit operand size
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else
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else
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emi.opSize = 1; // 16 bit operand size
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logOpSize = 1; // 16 bit operand size
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}
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}
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//Figure out how big of an immediate we'll retreive based
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//Figure out how big of an immediate we'll retreive based
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//on the opcode.
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//on the opcode.
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int immType = ImmediateType[emi.opcode.num - 1][nextByte];
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int immType = ImmediateType[emi.opcode.num - 1][nextByte];
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immediateSize = SizeTypeToSize[emi.opSize - 1][immType];
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immediateSize = SizeTypeToSize[logOpSize - 1][immType];
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//Set the actual op size
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emi.opSize = 1 << logOpSize;
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//Determine what to expect next
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//Determine what to expect next
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if (UsesModRM[emi.opcode.num - 1][nextByte]) {
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if (UsesModRM[emi.opcode.num - 1][nextByte]) {
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@ -192,9 +192,9 @@ namespace X86ISA
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//Use this to give data to the predecoder. This should be used
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//Use this to give data to the predecoder. This should be used
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//when there is control flow.
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//when there is control flow.
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void moreBytes(Addr currPC, Addr off, MachInst data)
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void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data)
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{
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{
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basePC = currPC;
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basePC = fetchPC;
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offset = off;
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offset = off;
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fetchChunk = data;
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fetchChunk = data;
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assert(off < sizeof(MachInst));
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assert(off < sizeof(MachInst));
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@ -202,13 +202,6 @@ namespace X86ISA
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process();
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process();
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}
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}
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//Use this to give data to the predecoder. This should be used
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//when instructions are executed in order.
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void moreBytes(MachInst machInst)
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{
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moreBytes(basePC + sizeof(machInst), 0, machInst);
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}
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bool needMoreBytes()
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bool needMoreBytes()
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{
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{
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return outOfBytes;
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return outOfBytes;
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@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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(&cacheData[tid][offset]));
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(&cacheData[tid][offset]));
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predecoder.setTC(cpu->thread[tid]->getTC());
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predecoder.setTC(cpu->thread[tid]->getTC());
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predecoder.moreBytes(fetch_PC, 0, inst);
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predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
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ext_inst = predecoder.getExtMachInst();
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ext_inst = predecoder.getExtMachInst();
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@ -336,13 +336,12 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
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thread->readNextPC(),thread->readNextNPC());
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thread->readNextPC(),thread->readNextNPC());
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#else
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#else
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
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thread->readNextPC());
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thread->readNextPC());
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#endif
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#endif
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const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
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Addr fetchPC = (threadPC & PCMask) + fetchOffset;
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Addr fetchPC = threadPC + fetchOffset;
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req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
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req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
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Fault fault = thread->translateInstReq(req);
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Fault fault = thread->translateInstReq(req);
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@ -381,7 +380,8 @@ BaseSimpleCPU::preExecute()
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predecoder.setTC(thread->getTC());
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predecoder.setTC(thread->getTC());
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//If more fetch data is needed, pass it in.
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//If more fetch data is needed, pass it in.
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if(predecoder.needMoreBytes())
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if(predecoder.needMoreBytes())
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predecoder.moreBytes(thread->readPC() + fetchOffset, 0, inst);
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predecoder.moreBytes(thread->readPC(),
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(thread->readPC() & PCMask) + fetchOffset, 0, inst);
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else
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else
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predecoder.process();
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predecoder.process();
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@ -166,6 +166,9 @@ class BaseSimpleCPU : public BaseCPU
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return numInst - startNumInst;
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return numInst - startNumInst;
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}
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}
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// Mask to align PCs to MachInst sized boundaries
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static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
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// number of simulated memory references
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// number of simulated memory references
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Stats::Scalar<> numMemRefs;
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Stats::Scalar<> numMemRefs;
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