Fixes for SPARC_FS
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
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4 changed files with 15 additions and 51 deletions
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@ -84,8 +84,14 @@ def makeSparcSystem(mem_mode, mdesc = None):
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# generic system
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# generic system
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mdesc = SysConfig()
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge()
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self.t1000 = T1000()
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self.t1000.attachIO(self.iobus)
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.physmem.port = self.membus.port
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self.rom.port = self.membus.port
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self.rom.port = self.membus.port
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self.intrctrl = IntrControl()
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self.intrctrl = IntrControl()
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@ -94,7 +94,8 @@ void MiscRegFile::reset()
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hintp = 0;
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hintp = 0;
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htba = 0;
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htba = 0;
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hstick_cmpr = 0;
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hstick_cmpr = 0;
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strandStatusReg = 0;
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//This is set this way in Legion for some reason
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strandStatusReg = 0x50000;
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fsr = 0;
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fsr = 0;
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implicitInstAsi = ASI_PRIMARY;
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implicitInstAsi = ASI_PRIMARY;
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implicitDataAsi = ASI_PRIMARY;
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implicitDataAsi = ASI_PRIMARY;
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@ -247,8 +247,10 @@ Trace::InstRecord::dump(ostream &outs)
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if (shared_data->flags == OWN_M5) {
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if (shared_data->flags == OWN_M5) {
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if (lgnPc != m5Pc)
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if (lgnPc != m5Pc)
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diffPC = true;
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diffPC = true;
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if (shared_data->instruction != staticInst->machInst)
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if (shared_data->instruction !=
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(SparcISA::MachInst)staticInst->machInst) {
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diffInst = true;
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diffInst = true;
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}
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for (int i = 0; i < TheISA::NumRegularIntRegs; i++) {
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for (int i = 0; i < TheISA::NumRegularIntRegs; i++) {
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if (thread->readIntReg(i) != shared_data->intregs[i]) {
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if (thread->readIntReg(i) != shared_data->intregs[i]) {
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diffRegs = true;
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diffRegs = true;
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@ -1,11 +1,9 @@
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from m5.params import *
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from m5.params import *
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from m5.proxy import *
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from m5.proxy import *
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from Device import BasicPioDevice
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from Device import BasicPioDevice
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from Platform import Platform
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from AlphaConsole import AlphaConsole
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from Uart import Uart8250
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from Uart import Uart8250
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from Pci import PciConfigAll
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from Platform import Platform
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from BadDevice import BadDevice
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from SimConsole import SimConsole, ConsoleListener
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class IsaFake(BasicPioDevice):
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class IsaFake(BasicPioDevice):
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type = 'IsaFake'
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type = 'IsaFake'
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@ -22,55 +20,12 @@ class T1000(Platform):
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fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
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fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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uart = Uart8250(pio_addr=0xfff0c2c000)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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console = SimConsole(listener = ConsoleListener())
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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uart = Uart8250(pio_addr=0x801fc0003f8)
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# Attach I/O devices to specified bus object. Can't do this
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# earlier, since the bus object itself is typically defined at the
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# System level.
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# System level.
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def attachIO(self, bus):
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def attachIO(self, bus):
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self.fake_iob.pio = bus.port
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self.fake_iob.pio = bus.port
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self.fake_uart1.pio = bus.port
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self.fake_uart2.pio = bus.port
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self.fake_uart3.pio = bus.port
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self.fake_uart4.pio = bus.port
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self.fake_ppc.pio = bus.port
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self.fake_OROM.pio = bus.port
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self.fake_pnp_addr.pio = bus.port
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self.fake_pnp_write.pio = bus.port
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self.fake_pnp_read0.pio = bus.port
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self.fake_pnp_read1.pio = bus.port
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self.fake_pnp_read2.pio = bus.port
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self.fake_pnp_read3.pio = bus.port
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self.fake_pnp_read4.pio = bus.port
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self.fake_pnp_read5.pio = bus.port
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self.fake_pnp_read6.pio = bus.port
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self.fake_pnp_read7.pio = bus.port
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self.fake_ata0.pio = bus.port
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self.fake_ata1.pio = bus.port
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self.fb.pio = bus.port
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self.io.pio = bus.port
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self.uart.pio = bus.port
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self.uart.pio = bus.port
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