MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
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2 changed files with 8 additions and 18 deletions
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@ -91,12 +91,6 @@ ISA::ISA()
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init();
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init();
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}
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}
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ISA::ISA(BaseCPU *_cpu)
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{
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cpu = _cpu;
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init();
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}
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void
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void
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ISA::init()
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ISA::init()
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{
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{
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@ -173,11 +167,10 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
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//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
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//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
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void
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void
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ISA::reset(std::string core_name, ThreadID num_threads,
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ISA::reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes, BaseCPU *_cpu)
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unsigned num_vpes, BaseCPU *cpu)
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{
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{
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DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
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DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
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num_threads, num_vpes);
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num_threads, num_vpes);
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cpu = _cpu;
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MipsISA::CoreSpecific &cp = cpu->coreParams;
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MipsISA::CoreSpecific &cp = cpu->coreParams;
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@ -499,7 +492,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
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miscRegFile[misc_reg][reg_sel] = cp0_val;
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miscRegFile[misc_reg][reg_sel] = cp0_val;
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scheduleCP0Update(1);
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scheduleCP0Update(tc->getCpuPtr(), 1);
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}
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}
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/**
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/**
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@ -528,7 +521,7 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
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}
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}
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void
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void
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ISA::scheduleCP0Update(int delay)
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ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
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{
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{
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if (!cp0Updated) {
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if (!cp0Updated) {
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cp0Updated = true;
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cp0Updated = true;
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@ -540,7 +533,7 @@ ISA::scheduleCP0Update(int delay)
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}
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}
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void
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void
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ISA::updateCPU()
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ISA::updateCPU(BaseCPU *cpu)
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{
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{
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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//
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//
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@ -578,7 +571,7 @@ ISA::CP0Event::process()
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switch (cp0EventType)
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switch (cp0EventType)
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{
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{
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case UpdateCP0:
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case UpdateCP0:
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cp0->updateCPU();
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cp0->updateCPU(cpu);
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break;
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break;
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}
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}
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}
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}
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@ -64,18 +64,15 @@ namespace MipsISA
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std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
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std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
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std::vector<BankType> bankType;
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std::vector<BankType> bankType;
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BaseCPU *cpu;
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public:
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public:
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ISA();
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ISA();
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ISA(BaseCPU *_cpu);
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void init();
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void init();
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void clear(unsigned tid_or_vpn = 0);
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void clear(unsigned tid_or_vpn = 0);
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void reset(std::string core_name, ThreadID num_threads,
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void reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes, BaseCPU *_cpu);
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unsigned num_vpes, BaseCPU *cpu);
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void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
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void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
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@ -147,11 +144,11 @@ namespace MipsISA
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};
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};
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// Schedule a CP0 Update Event
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// Schedule a CP0 Update Event
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void scheduleCP0Update(int delay = 0);
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void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
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// If any changes have been made, then check the state for changes
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// If any changes have been made, then check the state for changes
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// and if necessary alert the CPU
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// and if necessary alert the CPU
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void updateCPU();
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void updateCPU(BaseCPU *cpu);
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// Keep a List of CPU Events that need to be deallocated
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// Keep a List of CPU Events that need to be deallocated
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std::queue<CP0Event*> cp0EventRemoveList;
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std::queue<CP0Event*> cp0EventRemoveList;
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