ARM: Implement SVC (was SWI) outside of the decoder.
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caa95639ec
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@ -286,13 +286,7 @@ format DataOp {
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} // CPNUM (OP4 == 1)
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} // CPNUM (OP4 == 1)
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} //OPCODE_4
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} //OPCODE_4
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1: PredOp::swi({{
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1: Svc::svc();
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#if FULL_SYSTEM
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fault = new SupervisorCall();
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#else
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fault = new SupervisorCall(machInst);
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#endif
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}}, IsSyscall);
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} // OPCODE_24
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} // OPCODE_24
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}
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}
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@ -59,6 +59,9 @@
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//Include the branch format
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//Include the branch format
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##include "branch.isa"
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##include "branch.isa"
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//Miscellaneous instructions that don't fit elsewhere
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##include "misc.isa"
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//Include the unimplemented format
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//Include the unimplemented format
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##include "unimp.isa"
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##include "unimp.isa"
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42
src/arch/arm/isa/formats/misc.isa
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42
src/arch/arm/isa/formats/misc.isa
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@ -0,0 +1,42 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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def format Svc() {{
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decode_block = "return new Svc(machInst);"
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}};
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@ -46,6 +46,9 @@
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//Loads of a single item
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//Loads of a single item
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##include "ldr.isa"
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##include "ldr.isa"
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//Miscellaneous instructions that don't fit elsewhere
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##include "misc.isa"
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//Stores of a single item
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//Stores of a single item
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##include "str.isa"
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##include "str.isa"
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57
src/arch/arm/isa/insts/misc.isa
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57
src/arch/arm/isa/insts/misc.isa
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@ -0,0 +1,57 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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|
// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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svcCode = '''
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#if FULL_SYSTEM
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fault = new SupervisorCall;
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#else
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fault = new SupervisorCall(machInst);
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#endif
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'''
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svcIop = InstObjParams("svc", "Svc", "PredOp",
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{ "code": svcCode,
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"predicate_test": predicateTest }, ["IsSyscall"])
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header_output = BasicDeclare.subst(svcIop)
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decoder_output = BasicConstructor.subst(svcIop)
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exec_output = PredOpExecute.subst(svcIop)
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}};
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