mem: Remove unused arguments (asid/contex_id) from accessBlock

Change-Id: I79c2662fc81630ab321db8a75be6cd15fa07d372
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

src/mem/cache/cache.cc

@@ -314,11 +314,9 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
         return false;
     }
 
-    ContextID id = pkt->req->hasContextId() ?
-        pkt->req->contextId() : InvalidContextID;
     // Here lat is the value passed as parameter to accessBlock() function
     // that can modify its value.
-    blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id);
+    blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
 
     DPRINTF(Cache, "%s %s\n", pkt->print(),
             blk ? "hit " + blk->print() : "miss");

src/mem/cache/tags/base.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2014,2016 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -225,8 +225,7 @@ class BaseTags : public ClockedObject
 
     virtual void invalidate(CacheBlk *blk) = 0;
 
-    virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
+    virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
-                                  int context_src) = 0;
 
     virtual Addr extractTag(Addr addr) const = 0;
 

src/mem/cache/tags/base_set_assoc.hh

@@ -155,12 +155,10 @@ public:
      * side effect.
      * @param addr The address to find.
      * @param is_secure True if the target memory space is secure.
-     * @param asid The address space ID.
      * @param lat The access latency.
      * @return Pointer to the cache block if found.
      */
-    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
+    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
-                          int context_src) override
     {
         Addr tag = extractTag(addr);
         int set = extractSet(addr);

src/mem/cache/tags/fa_lru.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013,2016 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -171,14 +171,13 @@ FALRU::invalidate(CacheBlk *blk)
 }
 
 CacheBlk*
-FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src)
+FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat)
 {
-    return accessBlock(addr, is_secure, lat, context_src, 0);
+    return accessBlock(addr, is_secure, lat, 0);
 }
 
 CacheBlk*
-FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
+FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int *inCache)
-                   int *inCache)
 {
     accesses++;
     int tmp_in_cache = 0;

src/mem/cache/tags/fa_lru.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013,2016 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -182,19 +182,17 @@ public:
      * Returns the access latency and inCache flags as a side effect.
      * @param addr The address to look for.
      * @param is_secure True if the target memory space is secure.
-     * @param asid The address space ID.
      * @param lat The latency of the access.
      * @param inCache The FALRUBlk::inCache flags.
      * @return Pointer to the cache block.
      */
     CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
-                          int context_src, int *inCache);
+                          int *inCache);
 
     /**
      * Just a wrapper of above function to conform with the base interface.
      */
-    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
+    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
-                          int context_src) override;
 
     /**
      * Find the block in the cache, do not update the replacement data.

src/mem/cache/tags/lru.cc

@@ -56,9 +56,9 @@ LRU::LRU(const Params *p)
 }
 
 CacheBlk*
-LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int master_id)
+LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat)
 {
-    CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat, master_id);
+    CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat);
 
     if (blk != nullptr) {
         // move this block to head of the MRU list

src/mem/cache/tags/lru.hh

@@ -69,8 +69,7 @@ class LRU : public BaseSetAssoc
      */
     ~LRU() {}
 
-    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
+    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
-                         int context_src);
     CacheBlk* findVictim(Addr addr);
     void insertBlock(PacketPtr pkt, BlkType *blk);
     void invalidate(CacheBlk *blk);

src/mem/cache/tags/random_repl.cc

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2014 The Regents of The University of Michigan
+ * Copyright (c) 2016 ARM Limited
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -46,9 +47,9 @@ RandomRepl::RandomRepl(const Params *p)
 }
 
 CacheBlk*
-RandomRepl::accessBlock(Addr addr, bool is_secure, Cycles &lat, int master_id)
+RandomRepl::accessBlock(Addr addr, bool is_secure, Cycles &lat)
 {
-    return BaseSetAssoc::accessBlock(addr, is_secure, lat, master_id);
+    return BaseSetAssoc::accessBlock(addr, is_secure, lat);
 }
 
 CacheBlk*

src/mem/cache/tags/random_repl.hh

@@ -58,8 +58,7 @@ class RandomRepl : public BaseSetAssoc
      */
     ~RandomRepl() {}
 
-    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
+    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
-                         int context_src);
     CacheBlk* findVictim(Addr addr);
     void insertBlock(PacketPtr pkt, BlkType *blk);
     void invalidate(CacheBlk *blk);