Merge zizzer.eecs.umich.edu:/bk/m5

into ziff.eecs.umich.edu:/z/binkertn/research/m5/memory

--HG--
extra : convert_revision : 626baf73d2e26201088b05b4e5fac19292abcb32

arch/alpha/alpha_memory.cc

@@ -282,10 +282,18 @@ AlphaItb::translate(MemReqPtr &req) const
 
     if (req->flags & PHYSICAL) {
         req->paddr = req->vaddr;
-    } else if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+    } else {
-               VA_SPACE(req->vaddr) == 2) {
+        // verify that this is a good virtual address
+        if (!validVirtualAddress(req->vaddr)) {
+            fault(req->vaddr, req->xc);
+            acv++;
+            return Itb_Acv_Fault;
+        }
+
         // Check for "superpage" mapping: when SP<1> is set, and
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
+        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+               VA_SPACE(req->vaddr) == 2) {
 
             // only valid in kernel mode
             if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
@@ -296,13 +304,6 @@ AlphaItb::translate(MemReqPtr &req) const
 
             req->paddr = req->vaddr & PA_IMPL_MASK;
         } else {
-        // verify that this is a good virtual address
-        if (!validVirtualAddress(req->vaddr)) {
-            fault(req->vaddr, req->xc);
-            acv++;
-            return Itb_Acv_Fault;
-        }
-
             // not a physical address: need to look up pte
             AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
                                  DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
@@ -322,6 +323,9 @@ AlphaItb::translate(MemReqPtr &req) const
                 acv++;
                 return Itb_Acv_Fault;
             }
+
+            hits++;
+        }
     }
 
     // check that the physical address is ok (catch bad physical addresses)
@@ -330,7 +334,6 @@ AlphaItb::translate(MemReqPtr &req) const
 
     checkCacheability(req);
 
-    hits++;
     return No_Fault;
 }
 
@@ -453,13 +456,26 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
 
     if (req->flags & PHYSICAL) {
         req->paddr = req->vaddr;
-    } else if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+    } else {
-        VA_SPACE(req->vaddr) == 2) {
+        // verify that this is a good virtual address
+        if (!validVirtualAddress(req->vaddr)) {
+            fault(req->vaddr,
+                  ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK |
+                   MM_STAT_ACV_MASK),
+                  req->xc);
+
+            if (write) { write_acv++; } else { read_acv++; }
+            return Dtb_Fault_Fault;
+        }
+
         // Check for "superpage" mapping: when SP<1> is set, and
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
+        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+            VA_SPACE(req->vaddr) == 2) {
 
             // only valid in kernel mode
-        if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != AlphaISA::mode_kernel) {
+            if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
+                AlphaISA::mode_kernel) {
                 fault(req->vaddr,
                       ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK),
                       req->xc);
@@ -474,17 +490,6 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
             else
                 read_accesses++;
 
-        // verify that this is a good virtual address
-        if (!validVirtualAddress(req->vaddr)) {
-            fault(req->vaddr,
-                  ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK |
-                   MM_STAT_ACV_MASK),
-                  req->xc);
-
-            if (write) { write_acv++; } else { read_acv++; }
-            return Dtb_Fault_Fault;
-        }
-
             // not a physical address: need to look up pte
             AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
                                  DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
@@ -518,7 +523,8 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
             } else {
                 if (!(pte->xre & MODE2MASK(mode))) {
                     fault(req->vaddr,
-                      MM_STAT_ACV_MASK | (pte->fonr ? MM_STAT_FONR_MASK : 0),
+                          MM_STAT_ACV_MASK |
+                          (pte->fonr ? MM_STAT_FONR_MASK : 0),
                           req->xc);
                     read_acv++;
                     return Dtb_Acv_Fault;
@@ -529,6 +535,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
                     return Dtb_Fault_Fault;
                 }
             }
+        }
 
         if (write)
             write_hits++;
@@ -546,9 +553,11 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
 }
 
 AlphaISA::PTE &
-AlphaTlb::index()
+AlphaTlb::index(bool advance)
 {
     AlphaISA::PTE *pte = &table[nlu];
+
+    if (advance)
         nextnlu();
 
     return *pte;

arch/alpha/alpha_memory.hh

@@ -56,7 +56,7 @@ class AlphaTlb : public SimObject
 
     int getsize() const { return size; }
 
-    AlphaISA::PTE &index();
+    AlphaISA::PTE &index(bool advance = true);
     void insert(Addr vaddr, AlphaISA::PTE &pte);
 
     void flushAll();

arch/alpha/ev5.cc

@@ -240,6 +240,8 @@ ExecContext::readIpr(int idx, Fault &fault)
       case AlphaISA::IPR_VA:
         // SFX: unlocks interrupt status registers
         retval = ipr[idx];
+
+        if (!misspeculating())
             regs.intrlock = false;
         break;
 
@@ -253,7 +255,7 @@ ExecContext::readIpr(int idx, Fault &fault)
 
       case AlphaISA::IPR_DTB_PTE:
         {
-            AlphaISA::PTE &pte = dtb->index();
+            AlphaISA::PTE &pte = dtb->index(!misspeculating());
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;