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regress: updated hammer memtest and rubytest outputs

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--HG--
extra : rebase_source : b02ad38b477d87bf28f7677c985ec7fe9a7d4694
This commit is contained in:
Brad Beckmann 2011-12-01 11:54:30 -08:00
parent aab7397324
commit cb6ea0492f
9 changed files with 870 additions and 881 deletions
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1
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
mem_mode=timing mem_mode=timing
memories=system.physmem system.funcmem
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0 work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1 work_begin_cpu_id_exit=-1

1045
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
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File diff suppressed because it is too large Load diff

146
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
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@ -1,74 +1,74 @@
system.cpu2: completed 10000 read, 5303 write accesses @1876789 system.cpu4: completed 10000 read, 5368 write accesses @1896819
system.cpu6: completed 10000 read, 5467 write accesses @1901719 system.cpu0: completed 10000 read, 5327 write accesses @1910725
system.cpu1: completed 10000 read, 5435 write accesses @1922051 system.cpu5: completed 10000 read, 5493 write accesses @1929799
system.cpu7: completed 10000 read, 5297 write accesses @1933459 system.cpu2: completed 10000 read, 5341 write accesses @1933339
system.cpu4: completed 10000 read, 5524 write accesses @1940138 system.cpu1: completed 10000 read, 5585 write accesses @1940439
system.cpu5: completed 10000 read, 5406 write accesses @1942088 system.cpu7: completed 10000 read, 5510 write accesses @1944309
system.cpu0: completed 10000 read, 5366 write accesses @1952899 system.cpu6: completed 10000 read, 5231 write accesses @1946469
system.cpu3: completed 10000 read, 5440 write accesses @1977948 system.cpu3: completed 10000 read, 5461 write accesses @1963728
system.cpu4: completed 20000 read, 10787 write accesses @3784460 system.cpu0: completed 20000 read, 10595 write accesses @3805359
system.cpu6: completed 20000 read, 10802 write accesses @3793699 system.cpu2: completed 20000 read, 10586 write accesses @3820599
system.cpu2: completed 20000 read, 10675 write accesses @3812149 system.cpu3: completed 20000 read, 10867 write accesses @3829429
system.cpu5: completed 20000 read, 10824 write accesses @3843809 system.cpu4: completed 20000 read, 10761 write accesses @3846318
system.cpu7: completed 20000 read, 10635 write accesses @3848309 system.cpu6: completed 20000 read, 10413 write accesses @3857570
system.cpu1: completed 20000 read, 10760 write accesses @3864739 system.cpu5: completed 20000 read, 10874 write accesses @3859158
system.cpu0: completed 20000 read, 10677 write accesses @3867909 system.cpu7: completed 20000 read, 10747 write accesses @3866018
system.cpu3: completed 20000 read, 10802 write accesses @3932189 system.cpu1: completed 20000 read, 11096 write accesses @3900361
system.cpu4: completed 30000 read, 16195 write accesses @5712798 system.cpu3: completed 30000 read, 16232 write accesses @5720598
system.cpu2: completed 30000 read, 16031 write accesses @5729519 system.cpu2: completed 30000 read, 15880 write accesses @5740479
system.cpu5: completed 30000 read, 16208 write accesses @5744739 system.cpu7: completed 30000 read, 16148 write accesses @5769618
system.cpu1: completed 30000 read, 16141 write accesses @5773879 system.cpu0: completed 30000 read, 16080 write accesses @5774128
system.cpu7: completed 30000 read, 16141 write accesses @5780239 system.cpu6: completed 30000 read, 15848 write accesses @5779758
system.cpu6: completed 30000 read, 16232 write accesses @5784103 system.cpu4: completed 30000 read, 16090 write accesses @5782899
system.cpu0: completed 30000 read, 16012 write accesses @5799238 system.cpu1: completed 30000 read, 16550 write accesses @5821028
system.cpu3: completed 30000 read, 16245 write accesses @5831409 system.cpu5: completed 30000 read, 16439 write accesses @5824429
system.cpu5: completed 40000 read, 21576 write accesses @7645389 system.cpu3: completed 40000 read, 21587 write accesses @7653178
system.cpu2: completed 40000 read, 21332 write accesses @7669349 system.cpu0: completed 40000 read, 21623 write accesses @7670365
system.cpu4: completed 40000 read, 21616 write accesses @7685173 system.cpu2: completed 40000 read, 21273 write accesses @7684699
system.cpu1: completed 40000 read, 21665 write accesses @7712158 system.cpu7: completed 40000 read, 21445 write accesses @7713338
system.cpu0: completed 40000 read, 21358 write accesses @7717389 system.cpu6: completed 40000 read, 21321 write accesses @7719841
system.cpu6: completed 40000 read, 21602 write accesses @7718461 system.cpu4: completed 40000 read, 21451 write accesses @7726211
system.cpu3: completed 40000 read, 21484 write accesses @7735829 system.cpu1: completed 40000 read, 21832 write accesses @7734179
system.cpu7: completed 40000 read, 21641 write accesses @7781308 system.cpu5: completed 40000 read, 21913 write accesses @7792051
system.cpu2: completed 50000 read, 26834 write accesses @9615299 system.cpu0: completed 50000 read, 27135 write accesses @9608539
system.cpu0: completed 50000 read, 26760 write accesses @9622459 system.cpu4: completed 50000 read, 26878 write accesses @9641109
system.cpu3: completed 50000 read, 26814 write accesses @9627019 system.cpu3: completed 50000 read, 27076 write accesses @9643149
system.cpu5: completed 50000 read, 27114 write accesses @9630983 system.cpu6: completed 50000 read, 26709 write accesses @9646978
system.cpu4: completed 50000 read, 27066 write accesses @9656028 system.cpu2: completed 50000 read, 26734 write accesses @9654151
system.cpu6: completed 50000 read, 27209 write accesses @9657908 system.cpu7: completed 50000 read, 26876 write accesses @9682409
system.cpu1: completed 50000 read, 27012 write accesses @9661059 system.cpu5: completed 50000 read, 27248 write accesses @9689700
system.cpu7: completed 50000 read, 26974 write accesses @9754120 system.cpu1: completed 50000 read, 27302 write accesses @9695809
system.cpu2: completed 60000 read, 32159 write accesses @11510528 system.cpu0: completed 60000 read, 32449 write accesses @11491779
system.cpu5: completed 60000 read, 32406 write accesses @11518191 system.cpu3: completed 60000 read, 32401 write accesses @11561629
system.cpu6: completed 60000 read, 32617 write accesses @11553009 system.cpu6: completed 60000 read, 32081 write accesses @11565049
system.cpu3: completed 60000 read, 32203 write accesses @11554678 system.cpu7: completed 60000 read, 32080 write accesses @11566379
system.cpu0: completed 60000 read, 32053 write accesses @11566058 system.cpu4: completed 60000 read, 32352 write accesses @11573283
system.cpu1: completed 60000 read, 32501 write accesses @11568721 system.cpu5: completed 60000 read, 32718 write accesses @11575018
system.cpu4: completed 60000 read, 32470 write accesses @11604588 system.cpu2: completed 60000 read, 32150 write accesses @11585149
system.cpu7: completed 60000 read, 32381 write accesses @11680099 system.cpu1: completed 60000 read, 32680 write accesses @11632119
system.cpu2: completed 70000 read, 37529 write accesses @13430348 system.cpu0: completed 70000 read, 37771 write accesses @13429459
system.cpu5: completed 70000 read, 37835 write accesses @13440518 system.cpu7: completed 70000 read, 37234 write accesses @13447809
system.cpu6: completed 70000 read, 37972 write accesses @13479051 system.cpu4: completed 70000 read, 37607 write accesses @13456099
system.cpu3: completed 70000 read, 37489 write accesses @13479829 system.cpu6: completed 70000 read, 37614 write accesses @13484149
system.cpu0: completed 70000 read, 37464 write accesses @13498959 system.cpu5: completed 70000 read, 38039 write accesses @13487310
system.cpu4: completed 70000 read, 37713 write accesses @13503400 system.cpu3: completed 70000 read, 37787 write accesses @13523429
system.cpu1: completed 70000 read, 37879 write accesses @13506829 system.cpu1: completed 70000 read, 38168 write accesses @13544389
system.cpu7: completed 70000 read, 37696 write accesses @13588959 system.cpu2: completed 70000 read, 37479 write accesses @13559549
system.cpu2: completed 80000 read, 42898 write accesses @15336919 system.cpu0: completed 80000 read, 43086 write accesses @15325259
system.cpu3: completed 80000 read, 42777 write accesses @15361220 system.cpu4: completed 80000 read, 42854 write accesses @15364368
system.cpu5: completed 80000 read, 43096 write accesses @15388319 system.cpu7: completed 80000 read, 42627 write accesses @15378763
system.cpu4: completed 80000 read, 42937 write accesses @15407799 system.cpu6: completed 80000 read, 42741 write accesses @15379020
system.cpu0: completed 80000 read, 42740 write accesses @15414688 system.cpu3: completed 80000 read, 43087 write accesses @15412649
system.cpu6: completed 80000 read, 43294 write accesses @15425669 system.cpu5: completed 80000 read, 43504 write accesses @15439469
system.cpu1: completed 80000 read, 43269 write accesses @15452049 system.cpu1: completed 80000 read, 43522 write accesses @15480429
system.cpu7: completed 80000 read, 42960 write accesses @15504918 system.cpu2: completed 80000 read, 42764 write accesses @15493419
system.cpu2: completed 90000 read, 48377 write accesses @17274228 system.cpu0: completed 90000 read, 48539 write accesses @17246629
system.cpu3: completed 90000 read, 48234 write accesses @17290569 system.cpu5: completed 90000 read, 48747 write accesses @17277729
system.cpu5: completed 90000 read, 48524 write accesses @17330090 system.cpu6: completed 90000 read, 48097 write accesses @17293679
system.cpu6: completed 90000 read, 48654 write accesses @17333398 system.cpu4: completed 90000 read, 48405 write accesses @17331308
system.cpu0: completed 90000 read, 48119 write accesses @17336459 system.cpu7: completed 90000 read, 48155 write accesses @17349560
system.cpu4: completed 90000 read, 48219 write accesses @17373599 system.cpu3: completed 90000 read, 48566 write accesses @17362109
system.cpu1: completed 90000 read, 48746 write accesses @17384429 system.cpu2: completed 90000 read, 48156 write accesses @17435789
system.cpu7: completed 90000 read, 48558 write accesses @17482399 system.cpu1: completed 90000 read, 49002 write accesses @17469038
system.cpu2: completed 100000 read, 53807 write accesses @19206609 system.cpu0: completed 100000 read, 53926 write accesses @19175808
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

8
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 30 2011 15:20:24 gem5 compiled Dec 1 2011 11:03:29
gem5 started Jun 30 2011 15:20:49 gem5 started Dec 1 2011 11:03:44
gem5 executing on SC2B0622 gem5 executing on SC2B0612
command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 19206609 because maximum number of loads reached Exiting @ tick 19175808 because maximum number of loads reached

42
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
View file

@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.019207 # Number of seconds simulated sim_seconds 0.019176 # Number of seconds simulated
sim_ticks 19206609 # Number of ticks simulated sim_ticks 19175808 # Number of ticks simulated
sim_freq 1000000000 # Frequency of simulated ticks sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 127969 # Simulator tick rate (ticks/s) host_tick_rate 134618 # Simulator tick rate (ticks/s)
host_mem_usage 358544 # Number of bytes of host memory used host_mem_usage 381740 # Number of bytes of host memory used
host_seconds 150.09 # Real time elapsed on the host host_seconds 142.45 # Real time elapsed on the host
system.cpu0.num_reads 99703 # number of read accesses completed system.cpu0.num_reads 100000 # number of read accesses completed
system.cpu0.num_writes 53386 # number of write accesses completed system.cpu0.num_writes 53926 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu1.num_reads 99601 # number of read accesses completed system.cpu1.num_reads 98882 # number of read accesses completed
system.cpu1.num_writes 53869 # number of write accesses completed system.cpu1.num_writes 53707 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed system.cpu1.num_copies 0 # number of copy accesses completed
system.cpu2.num_reads 100000 # number of read accesses completed system.cpu2.num_reads 98977 # number of read accesses completed
system.cpu2.num_writes 53807 # number of write accesses completed system.cpu2.num_writes 53060 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed system.cpu2.num_copies 0 # number of copy accesses completed
system.cpu3.num_reads 99908 # number of read accesses completed system.cpu3.num_reads 99594 # number of read accesses completed
system.cpu3.num_writes 53597 # number of write accesses completed system.cpu3.num_writes 53686 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed system.cpu3.num_copies 0 # number of copy accesses completed
system.cpu4.num_reads 99417 # number of read accesses completed system.cpu4.num_reads 99524 # number of read accesses completed
system.cpu4.num_writes 53278 # number of write accesses completed system.cpu4.num_writes 53497 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed system.cpu4.num_copies 0 # number of copy accesses completed
system.cpu5.num_reads 99735 # number of read accesses completed system.cpu5.num_reads 99742 # number of read accesses completed
system.cpu5.num_writes 53654 # number of write accesses completed system.cpu5.num_writes 53984 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed system.cpu5.num_copies 0 # number of copy accesses completed
system.cpu6.num_reads 99876 # number of read accesses completed system.cpu6.num_reads 99887 # number of read accesses completed
system.cpu6.num_writes 53791 # number of write accesses completed system.cpu6.num_writes 53292 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed system.cpu6.num_copies 0 # number of copy accesses completed
system.cpu7.num_reads 98943 # number of read accesses completed system.cpu7.num_reads 99347 # number of read accesses completed
system.cpu7.num_writes 53425 # number of write accesses completed system.cpu7.num_writes 53300 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed system.cpu7.num_copies 0 # number of copy accesses completed
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

85
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=dir_cntrl0 l1_cntrl0 physmem ruby tester children=dir_cntrl0 l1_cntrl0 physmem ruby tester
mem_mode=timing mem_mode=timing
memories=system.physmem
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0 work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1 work_begin_cpu_id_exit=-1
@ -31,6 +32,7 @@ number_of_TBEs=256
probeFilter=system.dir_cntrl0.probeFilter probeFilter=system.dir_cntrl0.probeFilter
probe_filter_enabled=false probe_filter_enabled=false
recycle_latency=10 recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32 transitions_per_cycle=32
version=0 version=0
@ -73,9 +75,9 @@ start_index_bit=6
[system.l1_cntrl0] [system.l1_cntrl0]
type=L1Cache_Controller type=L1Cache_Controller
children=L2cacheMemory children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
L2cacheMemory=system.l1_cntrl0.L2cacheMemory L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0 buffer_size=0
cache_response_latency=10 cache_response_latency=10
@ -85,10 +87,27 @@ l2_cache_hit_latency=10
no_mig_atomic=true no_mig_atomic=true
number_of_TBEs=256 number_of_TBEs=256
recycle_latency=10 recycle_latency=10
sequencer=system.ruby.cpu_ruby_ports ruby_system=system.ruby
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32 transitions_per_cycle=32
version=0 version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L2cacheMemory] [system.l1_cntrl0.L2cacheMemory]
type=RubyCache type=RubyCache
assoc=2 assoc=2
@ -97,6 +116,21 @@ replacement_policy=PSEUDO_LRU
size=512 size=512
start_index_bit=6 start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=false
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
physmem=system.physmem
ruby_system=system.ruby
using_network_tester=false
using_ruby_tester=true
version=0
physMemPort=system.physmem.port[0]
port=system.tester.cpuPort[0]
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory
file= file=
@ -105,52 +139,18 @@ latency_var=0
null=false null=false
range=0:134217727 range=0:134217727
zero=false zero=false
port=system.ruby.cpu_ruby_ports.physMemPort port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby] [system.ruby]
type=RubySystem type=RubySystem
children=cpu_ruby_ports network profiler tracer children=network profiler tracer
block_size_bytes=64 block_size_bytes=64
clock=1 clock=1
mem_size=134217728 mem_size=134217728
network=system.ruby.network
no_mem_vec=false no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234 random_seed=1234
randomization=true randomization=true
stats_filename=ruby.stats stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache icache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.icache
max_outstanding_requests=16
physmem=system.physmem
using_network_tester=false
using_ruby_tester=true
version=0
physMemPort=system.physmem.port[0]
port=system.tester.cpuPort[0]
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.cpu_ruby_ports.icache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network] [system.ruby.network]
type=SimpleNetwork type=SimpleNetwork
@ -160,6 +160,7 @@ buffer_size=0
control_msg_size=8 control_msg_size=8
endpoint_bandwidth=1000 endpoint_bandwidth=1000
number_of_virtual_networks=10 number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology topology=system.ruby.network.topology
[system.ruby.network.topology] [system.ruby.network.topology]
@ -224,9 +225,11 @@ type=RubyProfiler
all_instructions=false all_instructions=false
hot_lines=false hot_lines=false
num_of_sequencers=1 num_of_sequencers=1
ruby_system=system.ruby
[system.ruby.tracer] [system.ruby.tracer]
type=RubyTracer type=RubyTracer
ruby_system=system.ruby
warmup_length=100000 warmup_length=100000
[system.tester] [system.tester]
@ -235,5 +238,5 @@ check_flush=false
checks_to_complete=100 checks_to_complete=100
deadlock_threshold=50000 deadlock_threshold=50000
wakeup_frequency=10 wakeup_frequency=10
cpuPort=system.ruby.cpu_ruby_ports.port[0] cpuPort=system.l1_cntrl0.sequencer.port[0]

396
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
View file

@ -34,29 +34,29 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================ ================ End RubySystem Configuration Print ================
Real time: Apr/28/2011 15:12:18 Real time: Dec/01/2011 11:03:43
Profiler Stats Profiler Stats
-------------- --------------
Elapsed_time_in_seconds: 0 Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0 Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 0 Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.47 Virtual_time_in_seconds: 0.46
Virtual_time_in_minutes: 0.00783333 Virtual_time_in_minutes: 0.00766667
Virtual_time_in_hours: 0.000130556 Virtual_time_in_hours: 0.000127778
Virtual_time_in_days: 5.43981e-06 Virtual_time_in_days: 5.32407e-06
Ruby_current_time: 218861 Ruby_current_time: 208411
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 218861 Ruby_cycles: 208411
mbytes_resident: 35.7695 mbytes_resident: 37.7227
mbytes_total: 219.633 mbytes_total: 242.977
resident_ratio: 0.162914 resident_ratio: 0.155268
ruby_cycles_executed: [ 218862 ] ruby_cycles_executed: [ 208412 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -65,17 +65,17 @@ Directory-0:0
Busy Bank Count:0 Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1005 average: 15.808 | standard deviation: 1.13264 | 0 1 1 1 1 1 1 1 1 1 1 1 1 2 4 65 922 ] sequencer_requests_outstanding: [binsize: 1 max: 16 count: 956 average: 15.7887 | standard deviation: 1.16133 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5 75 863 ]
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 128 max: 15144 count: 990 average: 3497.61 | standard deviation: 1761.96 | 94 4 26 34 22 11 5 2 0 0 2 0 0 2 0 0 1 0 1 0 0 1 3 1 3 8 16 24 44 55 84 62 81 68 73 52 45 41 35 22 24 22 9 3 1 2 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency: [binsize: 64 max: 6811 count: 941 average: 3500.81 | standard deviation: 1691.94 | 69 9 9 1 10 4 14 20 8 15 4 7 3 4 5 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 7 1 9 8 8 18 13 21 17 21 28 37 31 37 40 46 28 35 31 30 27 28 32 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 32 max: 5449 count: 40 average: 3885.72 | standard deviation: 1329.57 | 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 2 1 0 4 1 0 0 1 1 0 1 0 0 0 0 2 0 1 0 0 1 0 1 1 0 0 0 3 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 ] miss_latency_LD: [binsize: 64 max: 6620 count: 49 average: 3597.61 | standard deviation: 1746.75 | 5 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 128 max: 15144 count: 890 average: 3688.06 | standard deviation: 1639.42 | 83 2 16 13 12 4 3 1 0 0 2 0 0 2 0 0 1 0 1 0 0 1 3 1 2 8 14 24 42 51 78 60 80 66 71 50 42 38 34 21 22 21 8 3 1 2 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 64 max: 6811 count: 841 average: 3677.95 | standard deviation: 1562.59 | 61 8 4 0 5 4 3 14 3 9 2 3 1 3 5 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 5 1 9 7 8 18 12 20 17 18 28 37 27 35 37 43 27 32 30 29 26 26 31 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 8 max: 999 count: 60 average: 413.883 | standard deviation: 232.639 | 6 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 5 1 1 0 0 1 0 1 0 0 0 0 0 1 3 4 3 0 2 1 0 0 1 0 0 0 2 1 1 2 0 1 1 0 1 0 0 0 0 1 2 1 3 0 0 0 0 1 0 0 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH: [binsize: 8 max: 1159 count: 51 average: 486.745 | standard deviation: 255.245 | 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 13.2051 | standard deviation: 32.1294 | 0 21 15 17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 0 1 1 0 0 0 0 1 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 116 count: 70 average: 16.2571 | standard deviation: 35.3332 | 0 9 16 14 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 1 ]
miss_latency_L2Cache: [binsize: 128 max: 15144 count: 38 average: 3161.37 | standard deviation: 3572.78 | 16 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 2 1 1 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L2Cache: [binsize: 32 max: 4640 count: 34 average: 2534.59 | standard deviation: 1878.68 | 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ]
miss_latency_Directory: [binsize: 32 max: 5926 count: 874 average: 3823.2 | standard deviation: 1334.21 | 0 0 0 0 0 2 2 0 9 7 2 8 16 4 3 11 4 1 10 6 1 5 4 1 0 2 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 1 0 1 0 1 1 2 1 1 4 3 2 6 4 2 7 7 8 8 9 15 10 13 13 8 20 17 18 24 23 18 9 19 15 21 21 16 22 24 8 21 13 24 18 15 15 16 12 12 10 9 11 11 12 12 5 11 13 7 10 10 8 2 9 8 3 5 10 6 3 9 4 5 4 6 1 2 0 2 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_Directory: [binsize: 64 max: 6811 count: 837 average: 3831.48 | standard deviation: 1383.91 | 0 0 9 1 9 4 14 19 7 15 4 7 2 4 4 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 6 1 8 8 8 16 12 19 17 21 27 36 30 35 39 45 28 35 30 27 27 27 31 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -85,15 +85,14 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 874 imcomplete_dir_Times: 837
miss_latency_LD_L1Cache: [binsize: 1 max: 115 count: 2 average: 59 | standard deviation: 79.196 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_LD_L1Cache: [binsize: 1 max: 104 count: 6 average: 19.8333 | standard deviation: 41.248 | 0 1 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD_Directory: [binsize: 32 max: 5449 count: 38 average: 4087.13 | standard deviation: 1014.85 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 2 1 0 4 1 0 0 1 1 0 1 0 0 0 0 2 0 1 0 0 1 0 1 1 0 0 0 3 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 ] miss_latency_LD_Directory: [binsize: 64 max: 6620 count: 43 average: 4096.84 | standard deviation: 1184.49 | 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 113 count: 75 average: 12.1333 | standard deviation: 30.4935 | 0 21 14 16 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 0 1 1 0 0 0 0 1 ] miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 64 average: 15.9219 | standard deviation: 35.0852 | 0 8 16 12 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 1 ]
miss_latency_ST_L2Cache: [binsize: 128 max: 15144 count: 30 average: 3999.4 | standard deviation: 3582.58 | 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 2 1 1 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_ST_L2Cache: [binsize: 32 max: 4640 count: 31 average: 2779.26 | standard deviation: 1783.63 | 5 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ]
miss_latency_ST_Directory: [binsize: 32 max: 5926 count: 785 average: 4027.37 | standard deviation: 1077.58 | 0 0 0 0 0 1 1 0 3 5 1 7 6 1 2 4 2 0 6 3 0 2 2 0 0 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 1 0 0 0 1 1 2 1 1 4 2 2 5 4 2 7 7 8 7 9 14 10 11 13 8 18 16 18 20 22 18 9 18 14 21 20 16 22 24 8 19 13 23 18 15 14 16 11 11 10 9 11 8 12 11 4 10 13 7 9 10 8 2 9 8 2 5 9 5 3 9 3 5 4 6 1 1 0 2 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_Directory: [binsize: 64 max: 6811 count: 746 average: 4029.46 | standard deviation: 1146.93 | 0 0 4 0 4 4 3 13 2 9 2 3 0 3 4 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 4 1 8 7 8 16 11 18 17 18 27 36 26 33 36 42 27 32 29 26 26 25 30 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 1 average: 2 | standard deviation: 0 | 0 0 1 ] miss_latency_IFETCH_L2Cache: [binsize: 1 max: 9 count: 3 average: 6.33333 | standard deviation: 3.08221 | 0 0 0 1 0 0 0 1 0 1 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 108 count: 8 average: 18.75 | standard deviation: 36.0912 | 0 0 0 0 1 2 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_IFETCH_Directory: [binsize: 8 max: 1159 count: 48 average: 516.771 | standard deviation: 231.637 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
miss_latency_IFETCH_Directory: [binsize: 8 max: 999 count: 51 average: 483.941 | standard deviation: 174.07 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 5 1 1 0 0 1 0 1 0 0 0 0 0 1 3 4 3 0 2 1 0 0 1 0 0 0 2 1 1 2 0 1 1 0 1 0 0 0 0 1 2 1 3 0 0 0 0 1 0 0 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
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@ -125,7 +124,7 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 10373 page_reclaims: 10661
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
@ -134,98 +133,98 @@ block_outputs: 0
Network Stats Network Stats
------------- -------------
total_msg_count_Request_Control: 2625 21000 total_msg_count_Request_Control: 2511 20088
total_msg_count_Response_Data: 2622 188784 total_msg_count_Response_Data: 2511 180792
total_msg_count_Writeback_Data: 2342 168624 total_msg_count_Writeback_Data: 2248 161856
total_msg_count_Writeback_Control: 5451 43608 total_msg_count_Writeback_Control: 5220 41760
total_msg_count_Unblock_Control: 2615 20920 total_msg_count_Unblock_Control: 2506 20048
total_msgs: 15655 total_bytes: 442936 total_msgs: 14996 total_bytes: 424544
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.10979 links_utilized_percent_switch_0: 2.12273
links_utilized_percent_switch_0_link_0: 1.99487 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 2.00637 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.2247 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 2.23909 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 782 56304 [ 0 0 0 0 0 782 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Data: 750 54000 [ 0 0 0 0 0 750 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Unblock_Control: 873 6984 [ 0 0 0 0 0 873 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Unblock_Control: 836 6688 [ 0 0 0 0 0 836 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.10727 links_utilized_percent_switch_1: 2.12153
links_utilized_percent_switch_1_link_0: 2.21967 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 2.23669 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 1.99487 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 2.00637 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 874 6992 [ 0 0 874 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 780 56160 [ 0 0 0 0 0 780 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Unblock_Control: 871 6968 [ 0 0 0 0 0 871 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.10739 links_utilized_percent_switch_2: 2.12153
links_utilized_percent_switch_2_link_0: 1.99487 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 2.00637 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.2199 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 2.23669 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Request_Control: 875 7000 [ 0 0 875 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Data: 780 56160 [ 0 0 0 0 0 780 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 871 6968 [ 0 0 0 0 0 871 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.cpu_ruby_ports.icache Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.ruby.cpu_ruby_ports.icache_total_misses: 59 system.l1_cntrl0.L1IcacheMemory_total_misses: 51
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 59 system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 51
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 59 100% system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 51 100%
Cache Stats: system.ruby.cpu_ruby_ports.dcache Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.ruby.cpu_ruby_ports.dcache_total_misses: 872 system.l1_cntrl0.L1DcacheMemory_total_misses: 820
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 872 system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 820
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 4.58716% system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.2439%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 95.4128% system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.7561%
system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 872 100% system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 820 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory Cache Stats: system.l1_cntrl0.L2cacheMemory
system.l1_cntrl0.L2cacheMemory_total_misses: 931 system.l1_cntrl0.L2cacheMemory_total_misses: 871
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 931 system.l1_cntrl0.L2cacheMemory_total_demand_misses: 871
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.29646% system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.93685%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.3663% system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2078%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.33727% system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.85534%
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 931 100% system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 871 100%
--- L1Cache --- --- L1Cache ---
- Event Counts - - Event Counts -
Load [42 ] 42 Load [49 ] 49
Ifetch [61 ] 61 Ifetch [55 ] 55
Store [922 ] 922 Store [863 ] 863
L2_Replacement [869 ] 869 L2_Replacement [830 ] 830
L1_to_L2 [16473 ] 16473 L1_to_L2 [15990 ] 15990
Trigger_L2_to_L1D [47 ] 47 Trigger_L2_to_L1D [31 ] 31
Trigger_L2_to_L1I [8 ] 8 Trigger_L2_to_L1I [3 ] 3
Complete_L2_to_L1 [55 ] 55 Complete_L2_to_L1 [34 ] 34
Other_GETX [0 ] 0 Other_GETX [0 ] 0
Other_GETS [0 ] 0 Other_GETS [0 ] 0
Merged_GETS [0 ] 0 Merged_GETS [0 ] 0
@ -236,18 +235,18 @@ Ack [0 ] 0
Shared_Ack [0 ] 0 Shared_Ack [0 ] 0
Data [0 ] 0 Data [0 ] 0
Shared_Data [0 ] 0 Shared_Data [0 ] 0
Exclusive_Data [874 ] 874 Exclusive_Data [837 ] 837
Writeback_Ack [866 ] 866 Writeback_Ack [830 ] 830
Writeback_Nack [0 ] 0 Writeback_Nack [0 ] 0
All_acks [0 ] 0 All_acks [0 ] 0
All_acks_no_sharers [873 ] 873 All_acks_no_sharers [836 ] 836
Flush_line [0 ] 0 Flush_line [0 ] 0
Block_Ack [0 ] 0 Block_Ack [0 ] 0
- Transitions - - Transitions -
I Load [39 ] 39 I Load [43 ] 43
I Ifetch [51 ] 51 I Ifetch [48 ] 48
I Store [786 ] 786 I Store [746 ] 746
I L2_Replacement [0 ] 0 I L2_Replacement [0 ] 0
I L1_to_L2 [0 ] 0 I L1_to_L2 [0 ] 0
I Trigger_L2_to_L1D [0 ] 0 I Trigger_L2_to_L1D [0 ] 0
@ -290,10 +289,10 @@ O Flush_line [0 ] 0
M Load [0 ] 0 M Load [0 ] 0
M Ifetch [0 ] 0 M Ifetch [0 ] 0
M Store [2 ] 2 M Store [0 ] 0
M L2_Replacement [85 ] 85 M L2_Replacement [80 ] 80
M L1_to_L2 [93 ] 93 M L1_to_L2 [87 ] 87
M Trigger_L2_to_L1D [8 ] 8 M Trigger_L2_to_L1D [7 ] 7
M Trigger_L2_to_L1I [0 ] 0 M Trigger_L2_to_L1I [0 ] 0
M Other_GETX [0 ] 0 M Other_GETX [0 ] 0
M Other_GETS [0 ] 0 M Other_GETS [0 ] 0
@ -303,13 +302,13 @@ M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0 M Invalidate [0 ] 0
M Flush_line [0 ] 0 M Flush_line [0 ] 0
MM Load [2 ] 2 MM Load [6 ] 6
MM Ifetch [9 ] 9 MM Ifetch [0 ] 0
MM Store [102 ] 102 MM Store [63 ] 63
MM L2_Replacement [784 ] 784 MM L2_Replacement [750 ] 750
MM L1_to_L2 [833 ] 833 MM L1_to_L2 [779 ] 779
MM Trigger_L2_to_L1D [39 ] 39 MM Trigger_L2_to_L1D [24 ] 24
MM Trigger_L2_to_L1I [8 ] 8 MM Trigger_L2_to_L1I [3 ] 3
MM Other_GETX [0 ] 0 MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0 MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0 MM Merged_GETS [0 ] 0
@ -318,11 +317,40 @@ MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0 MM Invalidate [0 ] 0
MM Flush_line [0 ] 0 MM Flush_line [0 ] 0
IR Load [0 ] 0
IR Ifetch [0 ] 0
IR Store [0 ] 0
IR L1_to_L2 [0 ] 0
IR Flush_line [0 ] 0
SR Load [0 ] 0
SR Ifetch [0 ] 0
SR Store [0 ] 0
SR L1_to_L2 [0 ] 0
SR Flush_line [0 ] 0
OR Load [0 ] 0
OR Ifetch [0 ] 0
OR Store [0 ] 0
OR L1_to_L2 [0 ] 0
OR Flush_line [0 ] 0
MR Load [0 ] 0
MR Ifetch [0 ] 0
MR Store [7 ] 7
MR L1_to_L2 [52 ] 52
MMR Load [0 ] 0
MMR Ifetch [3 ] 3
MMR Store [24 ] 24
MMR L1_to_L2 [92 ] 92
MMR Flush_line [0 ] 0
IM Load [0 ] 0 IM Load [0 ] 0
IM Ifetch [0 ] 0 IM Ifetch [0 ] 0
IM Store [0 ] 0 IM Store [0 ] 0
IM L2_Replacement [0 ] 0 IM L2_Replacement [0 ] 0
IM L1_to_L2 [10256 ] 10256 IM L1_to_L2 [9590 ] 9590
IM Other_GETX [0 ] 0 IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0 IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0 IM Other_GETS_No_Mig [0 ] 0
@ -330,7 +358,7 @@ IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0 IM Invalidate [0 ] 0
IM Ack [0 ] 0 IM Ack [0 ] 0
IM Data [0 ] 0 IM Data [0 ] 0
IM Exclusive_Data [785 ] 785 IM Exclusive_Data [746 ] 746
IM Flush_line [0 ] 0 IM Flush_line [0 ] 0
SM Load [0 ] 0 SM Load [0 ] 0
@ -377,25 +405,25 @@ M_W Load [0 ] 0
M_W Ifetch [0 ] 0 M_W Ifetch [0 ] 0
M_W Store [0 ] 0 M_W Store [0 ] 0
M_W L2_Replacement [0 ] 0 M_W L2_Replacement [0 ] 0
M_W L1_to_L2 [292 ] 292 M_W L1_to_L2 [263 ] 263
M_W Ack [0 ] 0 M_W Ack [0 ] 0
M_W All_acks_no_sharers [88 ] 88 M_W All_acks_no_sharers [90 ] 90
M_W Flush_line [0 ] 0 M_W Flush_line [0 ] 0
MM_W Load [0 ] 0 MM_W Load [0 ] 0
MM_W Ifetch [0 ] 0 MM_W Ifetch [0 ] 0
MM_W Store [1 ] 1 MM_W Store [1 ] 1
MM_W L2_Replacement [0 ] 0 MM_W L2_Replacement [0 ] 0
MM_W L1_to_L2 [4281 ] 4281 MM_W L1_to_L2 [4391 ] 4391
MM_W Ack [0 ] 0 MM_W Ack [0 ] 0
MM_W All_acks_no_sharers [785 ] 785 MM_W All_acks_no_sharers [746 ] 746
MM_W Flush_line [0 ] 0 MM_W Flush_line [0 ] 0
IS Load [0 ] 0 IS Load [0 ] 0
IS Ifetch [0 ] 0 IS Ifetch [0 ] 0
IS Store [0 ] 0 IS Store [0 ] 0
IS L2_Replacement [0 ] 0 IS L2_Replacement [0 ] 0
IS L1_to_L2 [576 ] 576 IS L1_to_L2 [619 ] 619
IS Other_GETX [0 ] 0 IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0 IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0 IS Other_GETS_No_Mig [0 ] 0
@ -405,7 +433,7 @@ IS Ack [0 ] 0
IS Shared_Ack [0 ] 0 IS Shared_Ack [0 ] 0
IS Data [0 ] 0 IS Data [0 ] 0
IS Shared_Data [0 ] 0 IS Shared_Data [0 ] 0
IS Exclusive_Data [89 ] 89 IS Exclusive_Data [91 ] 91
IS Flush_line [0 ] 0 IS Flush_line [0 ] 0
SS Load [0 ] 0 SS Load [0 ] 0
@ -434,8 +462,8 @@ OI Writeback_Ack [0 ] 0
OI Flush_line [0 ] 0 OI Flush_line [0 ] 0
MI Load [0 ] 0 MI Load [0 ] 0
MI Ifetch [0 ] 0 MI Ifetch [3 ] 3
MI Store [2 ] 2 MI Store [1 ] 1
MI L2_Replacement [0 ] 0 MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0 MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0 MI Other_GETX [0 ] 0
@ -444,7 +472,7 @@ MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0 MI Other_GETS_No_Mig [0 ] 0
MI NC_DMA_GETS [0 ] 0 MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0 MI Invalidate [0 ] 0
MI Writeback_Ack [866 ] 866 MI Writeback_Ack [830 ] 830
MI Flush_line [0 ] 0 MI Flush_line [0 ] 0
II Load [0 ] 0 II Load [0 ] 0
@ -467,13 +495,6 @@ IT Store [0 ] 0
IT L2_Replacement [0 ] 0 IT L2_Replacement [0 ] 0
IT L1_to_L2 [0 ] 0 IT L1_to_L2 [0 ] 0
IT Complete_L2_to_L1 [0 ] 0 IT Complete_L2_to_L1 [0 ] 0
IT Other_GETX [0 ] 0
IT Other_GETS [0 ] 0
IT Merged_GETS [0 ] 0
IT Other_GETS_No_Mig [0 ] 0
IT NC_DMA_GETS [0 ] 0
IT Invalidate [0 ] 0
IT Flush_line [0 ] 0
ST Load [0 ] 0 ST Load [0 ] 0
ST Ifetch [0 ] 0 ST Ifetch [0 ] 0
@ -481,13 +502,6 @@ ST Store [0 ] 0
ST L2_Replacement [0 ] 0 ST L2_Replacement [0 ] 0
ST L1_to_L2 [0 ] 0 ST L1_to_L2 [0 ] 0
ST Complete_L2_to_L1 [0 ] 0 ST Complete_L2_to_L1 [0 ] 0
ST Other_GETX [0 ] 0
ST Other_GETS [0 ] 0
ST Merged_GETS [0 ] 0
ST Other_GETS_No_Mig [0 ] 0
ST NC_DMA_GETS [0 ] 0
ST Invalidate [0 ] 0
ST Flush_line [0 ] 0
OT Load [0 ] 0 OT Load [0 ] 0
OT Ifetch [0 ] 0 OT Ifetch [0 ] 0
@ -495,41 +509,20 @@ OT Store [0 ] 0
OT L2_Replacement [0 ] 0 OT L2_Replacement [0 ] 0
OT L1_to_L2 [0 ] 0 OT L1_to_L2 [0 ] 0
OT Complete_L2_to_L1 [0 ] 0 OT Complete_L2_to_L1 [0 ] 0
OT Other_GETX [0 ] 0
OT Other_GETS [0 ] 0
OT Merged_GETS [0 ] 0
OT Other_GETS_No_Mig [0 ] 0
OT NC_DMA_GETS [0 ] 0
OT Invalidate [0 ] 0
OT Flush_line [0 ] 0
MT Load [1 ] 1 MT Load [0 ] 0
MT Ifetch [0 ] 0 MT Ifetch [0 ] 0
MT Store [1 ] 1 MT Store [2 ] 2
MT L2_Replacement [0 ] 0 MT L2_Replacement [0 ] 0
MT L1_to_L2 [25 ] 25 MT L1_to_L2 [52 ] 52
MT Complete_L2_to_L1 [8 ] 8 MT Complete_L2_to_L1 [7 ] 7
MT Other_GETX [0 ] 0
MT Other_GETS [0 ] 0
MT Merged_GETS [0 ] 0
MT Other_GETS_No_Mig [0 ] 0
MT NC_DMA_GETS [0 ] 0
MT Invalidate [0 ] 0
MT Flush_line [0 ] 0
MMT Load [0 ] 0 MMT Load [0 ] 0
MMT Ifetch [1 ] 1 MMT Ifetch [1 ] 1
MMT Store [28 ] 28 MMT Store [19 ] 19
MMT L2_Replacement [0 ] 0 MMT L2_Replacement [0 ] 0
MMT L1_to_L2 [117 ] 117 MMT L1_to_L2 [65 ] 65
MMT Complete_L2_to_L1 [47 ] 47 MMT Complete_L2_to_L1 [27 ] 27
MMT Other_GETX [0 ] 0
MMT Other_GETS [0 ] 0
MMT Merged_GETS [0 ] 0
MMT Other_GETS_No_Mig [0 ] 0
MMT NC_DMA_GETS [0 ] 0
MMT Invalidate [0 ] 0
MMT Flush_line [0 ] 0
MI_F Load [0 ] 0 MI_F Load [0 ] 0
MI_F Ifetch [0 ] 0 MI_F Ifetch [0 ] 0
@ -627,42 +620,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
Memory controller: system.dir_cntrl0.memBuffer: Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1654 memory_total_requests: 1586
memory_reads: 874 memory_reads: 837
memory_writes: 780 memory_writes: 749
memory_refreshes: 456 memory_refreshes: 435
memory_total_request_delays: 1201 memory_total_request_delays: 1175
memory_delays_per_request: 0.726119 memory_delays_per_request: 0.740858
memory_delays_in_input_queue: 157 memory_delays_in_input_queue: 168
memory_delays_behind_head_of_bank_queue: 3 memory_delays_behind_head_of_bank_queue: 3
memory_delays_stalled_at_head_of_bank_queue: 1041 memory_delays_stalled_at_head_of_bank_queue: 1004
memory_stalls_for_bank_busy: 197 memory_stalls_for_bank_busy: 269
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 94 memory_stalls_for_arbitration: 76
memory_stalls_for_bus: 428 memory_stalls_for_bus: 376
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 194 memory_stalls_for_read_write_turnaround: 160
memory_stalls_for_read_read_turnaround: 128 memory_stalls_for_read_read_turnaround: 123
accesses_per_bank: 53 40 52 100 61 73 71 45 32 60 50 44 54 57 43 49 54 47 51 56 44 55 51 40 46 56 45 41 40 49 48 47 accesses_per_bank: 59 53 47 85 75 57 58 40 39 53 46 64 35 48 41 50 42 53 58 54 53 40 32 36 33 45 49 57 36 47 49 52
--- Directory --- --- Directory ---
- Event Counts - - Event Counts -
GETX [785 ] 785 GETX [747 ] 747
GETS [89 ] 89 GETS [92 ] 92
PUT [923 ] 923 PUT [900 ] 900
Unblock [0 ] 0 Unblock [0 ] 0
UnblockS [0 ] 0 UnblockS [0 ] 0
UnblockM [871 ] 871 UnblockM [835 ] 835
Writeback_Clean [0 ] 0 Writeback_Clean [0 ] 0
Writeback_Dirty [0 ] 0 Writeback_Dirty [0 ] 0
Writeback_Exclusive_Clean [84 ] 84 Writeback_Exclusive_Clean [79 ] 79
Writeback_Exclusive_Dirty [780 ] 780 Writeback_Exclusive_Dirty [749 ] 749
Pf_Replacement [0 ] 0 Pf_Replacement [0 ] 0
DMA_READ [0 ] 0 DMA_READ [0 ] 0
DMA_WRITE [0 ] 0 DMA_WRITE [0 ] 0
Memory_Data [874 ] 874 Memory_Data [837 ] 837
Memory_Ack [780 ] 780 Memory_Ack [749 ] 749
Ack [0 ] 0 Ack [0 ] 0
Shared_Ack [0 ] 0 Shared_Ack [0 ] 0
Shared_Data [0 ] 0 Shared_Data [0 ] 0
@ -686,7 +679,7 @@ NX GETF [0 ] 0
NO GETX [0 ] 0 NO GETX [0 ] 0
NO GETS [0 ] 0 NO GETS [0 ] 0
NO PUT [867 ] 867 NO PUT [830 ] 830
NO Pf_Replacement [0 ] 0 NO Pf_Replacement [0 ] 0
NO DMA_READ [0 ] 0 NO DMA_READ [0 ] 0
NO DMA_WRITE [0 ] 0 NO DMA_WRITE [0 ] 0
@ -708,8 +701,8 @@ O DMA_READ [0 ] 0
O DMA_WRITE [0 ] 0 O DMA_WRITE [0 ] 0
O GETF [0 ] 0 O GETF [0 ] 0
E GETX [785 ] 785 E GETX [746 ] 746
E GETS [89 ] 89 E GETS [91 ] 91
E PUT [0 ] 0 E PUT [0 ] 0
E DMA_READ [0 ] 0 E DMA_READ [0 ] 0
E DMA_WRITE [0 ] 0 E DMA_WRITE [0 ] 0
@ -750,9 +743,9 @@ NO_R GETF [0 ] 0
NO_B GETX [0 ] 0 NO_B GETX [0 ] 0
NO_B GETS [0 ] 0 NO_B GETS [0 ] 0
NO_B PUT [56 ] 56 NO_B PUT [70 ] 70
NO_B UnblockS [0 ] 0 NO_B UnblockS [0 ] 0
NO_B UnblockM [871 ] 871 NO_B UnblockM [835 ] 835
NO_B Pf_Replacement [0 ] 0 NO_B Pf_Replacement [0 ] 0
NO_B DMA_READ [0 ] 0 NO_B DMA_READ [0 ] 0
NO_B DMA_WRITE [0 ] 0 NO_B DMA_WRITE [0 ] 0
@ -806,7 +799,7 @@ NO_B_W UnblockM [0 ] 0
NO_B_W Pf_Replacement [0 ] 0 NO_B_W Pf_Replacement [0 ] 0
NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_READ [0 ] 0
NO_B_W DMA_WRITE [0 ] 0 NO_B_W DMA_WRITE [0 ] 0
NO_B_W Memory_Data [874 ] 874 NO_B_W Memory_Data [837 ] 837
NO_B_W GETF [0 ] 0 NO_B_W GETF [0 ] 0
O_B_W GETX [0 ] 0 O_B_W GETX [0 ] 0
@ -927,14 +920,14 @@ O_DR_B All_acks_and_owner_data [0 ] 0
O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0
O_DR_B GETF [0 ] 0 O_DR_B GETF [0 ] 0
WB GETX [0 ] 0 WB GETX [1 ] 1
WB GETS [0 ] 0 WB GETS [1 ] 1
WB PUT [0 ] 0 WB PUT [0 ] 0
WB Unblock [0 ] 0 WB Unblock [0 ] 0
WB Writeback_Clean [0 ] 0 WB Writeback_Clean [0 ] 0
WB Writeback_Dirty [0 ] 0 WB Writeback_Dirty [0 ] 0
WB Writeback_Exclusive_Clean [84 ] 84 WB Writeback_Exclusive_Clean [79 ] 79
WB Writeback_Exclusive_Dirty [780 ] 780 WB Writeback_Exclusive_Dirty [749 ] 749
WB Pf_Replacement [0 ] 0 WB Pf_Replacement [0 ] 0
WB DMA_READ [0 ] 0 WB DMA_READ [0 ] 0
WB DMA_WRITE [0 ] 0 WB DMA_WRITE [0 ] 0
@ -955,7 +948,7 @@ WB_E_W PUT [0 ] 0
WB_E_W Pf_Replacement [0 ] 0 WB_E_W Pf_Replacement [0 ] 0
WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_READ [0 ] 0
WB_E_W DMA_WRITE [0 ] 0 WB_E_W DMA_WRITE [0 ] 0
WB_E_W Memory_Ack [780 ] 780 WB_E_W Memory_Ack [749 ] 749
WB_E_W GETF [0 ] 0 WB_E_W GETF [0 ] 0
NO_F GETX [0 ] 0 NO_F GETX [0 ] 0
@ -973,4 +966,5 @@ NO_F_W Pf_Replacement [0 ] 0
NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_READ [0 ] 0
NO_F_W DMA_WRITE [0 ] 0 NO_F_W DMA_WRITE [0 ] 0
NO_F_W Memory_Data [0 ] 0 NO_F_W Memory_Data [0 ] 0
NO_F_W GETF NO_F_W GETF [0 ] 0

18
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
View file

@ -1,14 +1,10 @@
M5 Simulator System gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008 gem5 compiled Dec 1 2011 11:03:29
The Regents of The University of Michigan gem5 started Dec 1 2011 11:03:42
All Rights Reserved gem5 executing on SC2B0612
command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
M5 compiled Apr 28 2011 15:11:39
M5 started Apr 28 2011 15:12:18
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 218861 because Ruby Tester completed Exiting @ tick 208411 because Ruby Tester completed

10
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
View file

@ -1,10 +1,10 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_mem_usage 224908 # Number of bytes of host memory used sim_seconds 0.000208 # Number of seconds simulated
host_seconds 0.15 # Real time elapsed on the host sim_ticks 208411 # Number of ticks simulated
host_tick_rate 1412316 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks sim_freq 1000000000 # Frequency of simulated ticks
sim_seconds 0.000219 # Number of seconds simulated host_tick_rate 1657766 # Simulator tick rate (ticks/s)
sim_ticks 218861 # Number of ticks simulated host_mem_usage 248812 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------