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during a cache miss in the simple cpu we were finalizing the trace

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data too early (before the cache miss completed) and therefore
writing freeded memory after the cache miss completed.

Also removed some spurious setAddr() and setData() calls.

--HG--
extra : convert_revision : 3da82540c69c4c417aba3ed155e167d09431a1b2
This commit is contained in:
Ali Saidi 2005-03-15 17:31:18 -05:00
parent aa8ebb9efa
commit caf16a99cc
1 changed files with 10 additions and 19 deletions
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29
cpu/simple_cpu/simple_cpu.cc
View file

@ -393,13 +393,11 @@ template <class T>
Fault Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags) SimpleCPU::read(Addr addr, T &data, unsigned flags)
{ {
if (status() == DcacheMissStall) { if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
Fault fault = xc->read(memReq,data); Fault fault = xc->read(memReq,data);
if (traceData) { if (traceData) {
traceData->setAddr(addr); traceData->setAddr(addr);
if (fault == No_Fault)
traceData->setData(data);
} }
return fault; return fault;
} }
@ -428,21 +426,11 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
// do functional access // do functional access
fault = xc->read(memReq, data); fault = xc->read(memReq, data);
if (traceData) {
traceData->setAddr(addr);
if (fault == No_Fault)
traceData->setData(data);
}
} }
} else if(fault == No_Fault) { } else if(fault == No_Fault) {
// do functional access // do functional access
fault = xc->read(memReq, data); fault = xc->read(memReq, data);
if (traceData) {
traceData->setAddr(addr);
if (fault == No_Fault)
traceData->setData(data);
}
} }
if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
@ -498,11 +486,6 @@ template <class T>
Fault Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{ {
if (traceData) {
traceData->setAddr(addr);
traceData->setData(data);
}
memReq->reset(addr, sizeof(T), flags); memReq->reset(addr, sizeof(T), flags);
// translate to physical address // translate to physical address
@ -605,6 +588,8 @@ SimpleCPU::processCacheCompletion()
case DcacheMissStall: case DcacheMissStall:
if (memReq->cmd.isRead()) { if (memReq->cmd.isRead()) {
curStaticInst->execute(this,traceData); curStaticInst->execute(this,traceData);
if (traceData)
traceData->finalize();
} }
dcacheStallCycles += curTick - lastDcacheStall; dcacheStallCycles += curTick - lastDcacheStall;
_status = Running; _status = Running;
@ -613,6 +598,8 @@ SimpleCPU::processCacheCompletion()
case DcacheMissSwitch: case DcacheMissSwitch:
if (memReq->cmd.isRead()) { if (memReq->cmd.isRead()) {
curStaticInst->execute(this,traceData); curStaticInst->execute(this,traceData);
if (traceData)
traceData->finalize();
} }
_status = SwitchedOut; _status = SwitchedOut;
sampler->signalSwitched(); sampler->signalSwitched();
@ -785,8 +772,12 @@ SimpleCPU::tick()
comLoadEventQueue[0]->serviceEvents(numLoad); comLoadEventQueue[0]->serviceEvents(numLoad);
} }
if (traceData) // If we have a dcache miss, then we can't finialize the instruction
// trace yet because we want to populate it with the data later
if (traceData &&
!(status() == DcacheMissStall && memReq->cmd.isRead())) {
traceData->finalize(); traceData->finalize();
}
traceFunctions(xc->regs.pc); traceFunctions(xc->regs.pc);