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config: Add voltage domain to Ruby example scripts

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This patch adds the minimum required voltage domain configuration to
the Ruby example scripts.
This commit is contained in:
Andreas Hansson 2013-09-12 17:49:12 -04:00
parent cc155ffa0d
commit c9e45f01e4
4 changed files with 39 additions and 13 deletions
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13
configs/example/ruby_direct_test.py
View file

@ -92,8 +92,14 @@ else:
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
system = System(physmem = SimpleMemory(),
clk_domain = SrcClockDomain(clock = options.sys_clock))
system = System(physmem = SimpleMemory())
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
#
# Create the ruby random tester
@ -105,7 +111,8 @@ system.tester = RubyDirectedTester(requests_to_complete = \
Ruby.create_system(options, system)
# Since Ruby runs at an independent frequency, create a seperate clock
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))

14
configs/example/ruby_fs.py
View file

@ -90,7 +90,11 @@ elif buildEnv['TARGET_ISA'] == "x86":
else:
fatal("incapable of building non-alpha or non-x86 full system!")
system.clk_domain = SrcClockDomain(clock = options.sys_clock)
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
if options.kernel is not None:
system.kernel = binary(options.kernel)
@ -101,12 +105,14 @@ if options.script is not None:
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
# Create a source clock for the CPUs and set the clock period
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain = system.voltage_domain)
Ruby.create_system(options, system, system.piobus, system._dma_ports)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for (i, cpu) in enumerate(system.cpu):
#
@ -129,7 +135,7 @@ for (i, cpu) in enumerate(system.cpu):
# Create the appropriate memory controllers and connect them to the
# PIO bus
system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
for i in xrange(len(system.physmem)):
for i in xrange(len(system.mem_ctrls)):
system.mem_ctrls[i].port = system.piobus.master
root = Root(full_system = True, system = system)

13
configs/example/ruby_network_test.py
View file

@ -104,13 +104,20 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
# create the desired simulated system
system = System(cpu = cpus,
physmem = SimpleMemory(),
clk_domain = SrcClockDomain(clock = options.sys_clock))
physmem = SimpleMemory())
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
Ruby.create_system(options, system)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
i = 0
for ruby_port in system.ruby._cpu_ruby_ports:

12
configs/example/ruby_random_test.py
View file

@ -97,13 +97,19 @@ tester = RubyTester(check_flush = check_flush,
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
system = System(tester = tester, physmem = SimpleMemory(),
clk_domain = SrcClockDomain(clock = options.sys_clock))
system = System(tester = tester, physmem = SimpleMemory())
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
Ruby.create_system(options, system)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))