ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.
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2 changed files with 33 additions and 4 deletions
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@ -110,7 +110,11 @@ namespace ArmISA
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* Technically this should be 0, but we don't support those
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* settings.
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*/
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miscRegs[MISCREG_CPACR] = 0x0fffffff;
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CPACR cpacr = 0;
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// Enable CP 10, 11
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cpacr.cp10 = 0x3;
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cpacr.cp11 = 0x3;
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miscRegs[MISCREG_CPACR] = cpacr;
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/* One region, unified map. */
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miscRegs[MISCREG_MPUIR] = 0x100;
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@ -249,10 +253,16 @@ namespace ArmISA
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}
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switch (misc_reg) {
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case MISCREG_CPACR:
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newVal = bits(val, 27, 0);
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if (newVal != 0x0fffffff) {
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{
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CPACR newCpacr = 0;
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CPACR valCpacr = val;
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newCpacr.cp10 = valCpacr.cp10;
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newCpacr.cp11 = valCpacr.cp11;
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if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
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panic("Disabling coprocessors isn't implemented.\n");
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}
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newVal = newCpacr;
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}
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break;
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case MISCREG_CSSELR:
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warn("The csselr register isn't implemented.\n");
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@ -230,6 +230,25 @@ namespace ArmISA
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Bitfield<1> a; // Alignment fault checking
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Bitfield<0> m; // MMU enable bit
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EndBitUnion(SCTLR)
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BitUnion32(CPACR)
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Bitfield<1, 0> cp0;
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Bitfield<3, 2> cp1;
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Bitfield<5, 4> cp2;
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Bitfield<7, 6> cp3;
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Bitfield<9, 8> cp4;
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Bitfield<11, 10> cp5;
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Bitfield<13, 12> cp6;
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Bitfield<15, 14> cp7;
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Bitfield<17, 16> cp8;
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Bitfield<19, 18> cp9;
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Bitfield<21, 20> cp10;
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Bitfield<23, 22> cp11;
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Bitfield<25, 24> cp12;
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Bitfield<27, 26> cp13;
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Bitfield<30> d32dis;
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Bitfield<31> asedis;
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EndBitUnion(CPACR)
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};
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#endif // __ARCH_ARM_MISCREGS_HH__
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