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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.

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This commit is contained in:
Gabe Black 2009-07-08 23:02:22 -07:00
parent 3d39b62132
commit c9a27d85b9
22 changed files with 19 additions and 148 deletions
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12
src/arch/alpha/ev5.cc
View file

@ -127,18 +127,6 @@ zeroRegisters(CPU *cpu)
cpu->thread->setFloatReg(ZeroReg, 0.0);
}
int
ISA::getInstAsid()
{
return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
ISA::getDataAsid()
{
return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
////////////////////////////////////////////////////////////////////////

5
src/arch/alpha/isa.hh
View file

@ -65,11 +65,6 @@ namespace AlphaISA
public:
// These functions should be removed once the simplescalar cpu
// model has been replaced.
int getInstAsid();
int getDataAsid();
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);

10
src/arch/mips/isa.hh
View file

@ -57,16 +57,6 @@ namespace MipsISA
miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
}
int instAsid()
{
return miscRegFile.getInstAsid();
}
int dataAsid()
{
return miscRegFile.getDataAsid();
}
void clear();
MiscReg readMiscRegNoEffect(int miscReg);

15
src/arch/mips/mips_core_specific.cc
View file

@ -109,19 +109,4 @@ MipsISA::processInterrupts(CPU *cpu)
*/
}
/*int
MipsISA::MiscRegFile::getInstAsid()
{
return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
MipsISA::MiscRegFile::getDataAsid()
{
return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}*/
#endif // FULL_SYSTEM || BARE_IRON

11
src/arch/mips/misc_regfile.cc
View file

@ -167,17 +167,6 @@ MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
}
}
int MiscRegFile::getInstAsid()
{
MiscReg Entry_Hi = readRegNoEffect(EntryHi);
return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO);
}
int MiscRegFile:: getDataAsid()
{
MiscReg EHi = readRegNoEffect(EntryHi);
return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO);
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
MiscRegFile::reset(std::string core_name, ThreadID num_threads,

3
src/arch/mips/misc_regfile.hh
View file

@ -103,9 +103,6 @@ namespace MipsISA
void setReg(int misc_reg, const MiscReg &val,
ThreadContext *tc, ThreadID tid = 0);
int getInstAsid();
int getDataAsid();
//////////////////////////////////////////////////////////
//
// DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)

11
src/arch/sparc/isa.hh
View file

@ -45,17 +45,6 @@ namespace SparcISA
MiscRegFile miscRegFile;
public:
int instAsid()
{
return miscRegFile.getInstAsid();
}
int dataAsid()
{
return miscRegFile.getDataAsid();
}
void clear();
MiscReg readMiscRegNoEffect(int miscReg);

10
src/arch/sparc/miscregfile.hh
View file

@ -158,16 +158,6 @@ namespace SparcISA
void setReg(int miscReg,
const MiscReg &val, ThreadContext * tc);
int getInstAsid()
{
return priContext | (uint32_t)partId << 13;
}
int getDataAsid()
{
return priContext | (uint32_t)partId << 13;
}
void serialize(EventManager *em, std::ostream & os);
void unserialize(EventManager *em, Checkpoint *cp,

12
src/arch/x86/isa.hh
View file

@ -45,18 +45,6 @@ namespace X86ISA
MiscRegFile miscRegFile;
public:
int instAsid()
{
//XXX This doesn't make sense in x86
return 0;
}
int dataAsid()
{
//XXX This doesn't make sense in x86
return 0;
}
void clear();
MiscReg readMiscRegNoEffect(int miscReg);

3
src/cpu/checker/cpu.cc
View file

@ -72,8 +72,7 @@ CheckerCPU::CheckerCPU(Params *p)
systemPtr = NULL;
#else
process = p->process;
thread = new SimpleThread(this, /* thread_num */ 0, process,
/* asid */ 0);
thread = new SimpleThread(this, /* thread_num */ 0, process);
tc = thread->getTC();
threadContexts.push_back(tc);

4
src/cpu/inorder/cpu.cc
View file

@ -207,12 +207,12 @@ InOrderCPU::InOrderCPU(Params *params)
DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
tid, this->thread[tid]);
this->thread[tid] =
new Thread(this, tid, params->workload[tid], tid);
new Thread(this, tid, params->workload[tid]);
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = params->workload[0];
this->thread[tid] = new Thread(this, tid, dummy_proc, tid);
this->thread[tid] = new Thread(this, tid, dummy_proc);
}
// Setup the TC that will serve as the interface to the threads/CPU.

8
src/cpu/inorder/cpu.hh
View file

@ -395,14 +395,6 @@ class InOrderCPU : public BaseCPU
return cpuEventNum++;
}
/** Get instruction asid. */
int getInstAsid(ThreadID tid)
{ return thread[tid]->getInstAsid(); }
/** Get data asid. */
int getDataAsid(ThreadID tid)
{ return thread[tid]->getDataAsid(); }
/** Register file accessors */
uint64_t readIntReg(int reg_idx, ThreadID tid);

4
src/cpu/inorder/thread_state.hh
View file

@ -68,9 +68,9 @@ class InOrderThreadState : public ThreadState {
InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num,
Process *_process, int _asid)
Process *_process)
: ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/,
_process, 0/*_asid*/),
_process),
cpu(_cpu), inSyscall(0), trapPending(0)
{ }

4
src/cpu/o3/cpu.cc
View file

@ -361,7 +361,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
tid, params->workload[tid], tid);
tid, params->workload[tid]);
//usedTids[tid] = true;
//threadMap[tid] = tid;
@ -372,7 +372,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
tid, dummy_proc, tid);
tid, dummy_proc);
//usedTids[tid] = false;
}
#endif // !FULL_SYSTEM

17
src/cpu/o3/cpu.hh
View file

@ -392,23 +392,6 @@ class FullO3CPU : public BaseO3CPU
/** Check if this address is a valid data address. */
bool validDataAddr(Addr addr) { return true; }
/** Get instruction asid. */
int getInstAsid(ThreadID tid)
{ return isa[tid].instAsid(); }
/** Get data asid. */
int getDataAsid(ThreadID tid)
{ return isa[tid].dataAsid(); }
#else
/** Get instruction asid. */
int getInstAsid(ThreadID tid)
{ return thread[tid]->getInstAsid(); }
/** Get data asid. */
int getDataAsid(ThreadID tid)
{ return thread[tid]->getDataAsid(); }
#endif
/** Register accessors. Index refers to the physical register index. */

4
src/cpu/o3/thread_state.hh
View file

@ -95,8 +95,8 @@ struct O3ThreadState : public ThreadState {
profilePC = 3;
}
#else
O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
: ThreadState(_cpu, _thread_num, _process, _asid),
O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0)
{ }
#endif

5
src/cpu/ozone/thread_state.hh
View file

@ -86,9 +86,8 @@ struct OzoneThreadState : public ThreadState {
miscRegFile.clear();
}
#else
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
int _asid)
: ThreadState(_cpu, -1, _thread_num, _process, _asid),
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, -1, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0)
{
miscRegFile.clear();

2
src/cpu/simple/base.cc
View file

@ -78,7 +78,7 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
#else
thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
p->itb, p->dtb, /* asid */ 0);
p->itb, p->dtb);
#endif // !FULL_SYSTEM
thread->setStatus(ThreadContext::Halted);

6
src/cpu/simple_thread.cc
View file

@ -92,8 +92,8 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid)
: ThreadState(_cpu, _thread_num, _process, _asid),
TheISA::TLB *_itb, TheISA::TLB *_dtb)
: ThreadState(_cpu, _thread_num, _process),
cpu(_cpu), itb(_itb), dtb(_dtb)
{
clearArchRegs();
@ -106,7 +106,7 @@ SimpleThread::SimpleThread()
#if FULL_SYSTEM
: ThreadState(NULL, -1)
#else
: ThreadState(NULL, -1, NULL, -1)
: ThreadState(NULL, -1, NULL)
#endif
{
tc = new ProxyThreadContext<SimpleThread>(this);

5
src/cpu/simple_thread.hh
View file

@ -145,7 +145,7 @@ class SimpleThread : public ThreadState
bool use_kernel_stats = true);
#else
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
TheISA::TLB *_itb, TheISA::TLB *_dtb);
#endif
SimpleThread();
@ -191,9 +191,6 @@ class SimpleThread : public ThreadState
}
#if FULL_SYSTEM
int getInstAsid() { return isa.instAsid(); }
int getDataAsid() { return isa.dataAsid(); }
void dumpFuncProfile();
Fault hwrei();

5
src/cpu/thread_state.cc
View file

@ -45,8 +45,7 @@
#if FULL_SYSTEM
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid)
#else
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid,
Process *_process, short _asid)
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
#endif
: numInst(0), numLoad(0), _status(ThreadContext::Halted),
baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
@ -54,7 +53,7 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid,
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
kernelStats(NULL), physPort(NULL), virtPort(NULL),
#else
port(NULL), process(_process), asid(_asid),
port(NULL), process(_process),
#endif
funcExeInst(0), storeCondFailures(0)
{

11
src/cpu/thread_state.hh
View file

@ -68,7 +68,7 @@ struct ThreadState {
#if FULL_SYSTEM
ThreadState(BaseCPU *cpu, ThreadID _tid);
#else
ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process, short _asid);
ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
#endif
~ThreadState();
@ -119,9 +119,6 @@ struct ThreadState {
TranslatingPort *getMemPort();
void setMemPort(TranslatingPort *_port) { port = _port; }
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
#endif
/** Sets the current instruction being committed. */
@ -205,12 +202,6 @@ struct ThreadState {
TranslatingPort *port;
Process *process;
// Address space ID. Note that this is used for TIMING cache
// simulation only; all functional memory accesses should use
// one of the FunctionalMemory pointers above.
short asid;
#endif
/** Current instruction the thread is committing. Only set and