X86: Add x86 reference output for the timing CPU.
This commit is contained in:
parent
846cb450f9
commit
c981b7ed50
32 changed files with 4200 additions and 0 deletions
193
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
Normal file
193
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
Normal file
|
@ -0,0 +1,193 @@
|
||||||
|
[root]
|
||||||
|
type=Root
|
||||||
|
children=system
|
||||||
|
dummy=0
|
||||||
|
|
||||||
|
[system]
|
||||||
|
type=System
|
||||||
|
children=cpu membus physmem
|
||||||
|
mem_mode=atomic
|
||||||
|
physmem=system.physmem
|
||||||
|
|
||||||
|
[system.cpu]
|
||||||
|
type=TimingSimpleCPU
|
||||||
|
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||||
|
clock=500
|
||||||
|
cpu_id=0
|
||||||
|
defer_registration=false
|
||||||
|
dtb=system.cpu.dtb
|
||||||
|
function_trace=false
|
||||||
|
function_trace_start=0
|
||||||
|
itb=system.cpu.itb
|
||||||
|
max_insts_all_threads=0
|
||||||
|
max_insts_any_thread=0
|
||||||
|
max_loads_all_threads=0
|
||||||
|
max_loads_any_thread=0
|
||||||
|
numThreads=1
|
||||||
|
phase=0
|
||||||
|
progress_interval=0
|
||||||
|
system=system
|
||||||
|
tracer=system.cpu.tracer
|
||||||
|
workload=system.cpu.workload
|
||||||
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.dcache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=262144
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.dcache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.dtb]
|
||||||
|
type=X86DTB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.icache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=131072
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.icache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.itb]
|
||||||
|
type=X86ITB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.l2cache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=10000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=100000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=2097152
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.toL2Bus.port[2]
|
||||||
|
mem_side=system.membus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.toL2Bus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.tracer]
|
||||||
|
type=ExeTracer
|
||||||
|
|
||||||
|
[system.cpu.workload]
|
||||||
|
type=LiveProcess
|
||||||
|
cmd=gzip input.log 1
|
||||||
|
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
|
||||||
|
egid=100
|
||||||
|
env=
|
||||||
|
errout=cerr
|
||||||
|
euid=100
|
||||||
|
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||||
|
gid=100
|
||||||
|
input=cin
|
||||||
|
max_stack_size=67108864
|
||||||
|
output=cout
|
||||||
|
pid=100
|
||||||
|
ppid=99
|
||||||
|
simpoint=0
|
||||||
|
system=system
|
||||||
|
uid=100
|
||||||
|
|
||||||
|
[system.membus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||||
|
|
||||||
|
[system.physmem]
|
||||||
|
type=PhysicalMemory
|
||||||
|
file=
|
||||||
|
latency=30000
|
||||||
|
latency_var=0
|
||||||
|
null=false
|
||||||
|
range=0:134217727
|
||||||
|
zero=false
|
||||||
|
port=system.membus.port[0]
|
||||||
|
|
234
tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt
Normal file
234
tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,234 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 1159099 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 201888 # Number of bytes of host memory used
|
||||||
|
host_seconds 1397.12 # Real time elapsed on the host
|
||||||
|
host_tick_rate 1828142910 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 1619398860 # Number of instructions simulated
|
||||||
|
sim_seconds 2.554133 # Number of seconds simulated
|
||||||
|
sim_ticks 2554132875000 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 606644555 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 506099 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 439707 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 308507 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 721 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 1925902841 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 721 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 4 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses
|
||||||
|
system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 161820 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 282704 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 82097 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 61702 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 5108265750 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 1619398860 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 607161871 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
9
tests/long/00.gzip/ref/x86/linux/simple-timing/stderr
Executable file
9
tests/long/00.gzip/ref/x86/linux/simple-timing/stderr
Executable file
|
@ -0,0 +1,9 @@
|
||||||
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
|
warn: instruction 'fnstcw_Mw' unimplemented
|
||||||
|
warn: instruction 'fldcw_Mw' unimplemented
|
||||||
|
warn: instruction 'prefetch_t0' unimplemented
|
||||||
|
warn: instruction 'prefetch_t0' unimplemented
|
||||||
|
warn: instruction 'prefetch_t0' unimplemented
|
||||||
|
warn: instruction 'prefetch_t0' unimplemented
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: be nice to actually delete the event here
|
47
tests/long/00.gzip/ref/x86/linux/simple-timing/stdout
Executable file
47
tests/long/00.gzip/ref/x86/linux/simple-timing/stdout
Executable file
|
@ -0,0 +1,47 @@
|
||||||
|
M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2008
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Nov 7 2008 03:21:37
|
||||||
|
M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
|
||||||
|
M5 commit date Thu Nov 06 23:13:50 2008 -0800
|
||||||
|
M5 started Nov 8 2008 00:23:58
|
||||||
|
M5 executing on tater
|
||||||
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing
|
||||||
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
spec_init
|
||||||
|
Loading Input Data
|
||||||
|
Duplicating 262144 bytes
|
||||||
|
Duplicating 524288 bytes
|
||||||
|
Input data 1048576 bytes in length
|
||||||
|
Compressing Input Data, level 1
|
||||||
|
Compressed data 108074 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Compressing Input Data, level 3
|
||||||
|
Compressed data 97831 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Compressing Input Data, level 5
|
||||||
|
Compressed data 83382 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Compressing Input Data, level 7
|
||||||
|
Compressed data 76606 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Compressing Input Data, level 9
|
||||||
|
Compressed data 73189 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Tested 1MB buffer: OK!
|
||||||
|
Exiting @ tick 2554132875000 because target called exit()
|
193
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
Normal file
193
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
Normal file
|
@ -0,0 +1,193 @@
|
||||||
|
[root]
|
||||||
|
type=Root
|
||||||
|
children=system
|
||||||
|
dummy=0
|
||||||
|
|
||||||
|
[system]
|
||||||
|
type=System
|
||||||
|
children=cpu membus physmem
|
||||||
|
mem_mode=atomic
|
||||||
|
physmem=system.physmem
|
||||||
|
|
||||||
|
[system.cpu]
|
||||||
|
type=TimingSimpleCPU
|
||||||
|
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||||
|
clock=500
|
||||||
|
cpu_id=0
|
||||||
|
defer_registration=false
|
||||||
|
dtb=system.cpu.dtb
|
||||||
|
function_trace=false
|
||||||
|
function_trace_start=0
|
||||||
|
itb=system.cpu.itb
|
||||||
|
max_insts_all_threads=0
|
||||||
|
max_insts_any_thread=0
|
||||||
|
max_loads_all_threads=0
|
||||||
|
max_loads_any_thread=0
|
||||||
|
numThreads=1
|
||||||
|
phase=0
|
||||||
|
progress_interval=0
|
||||||
|
system=system
|
||||||
|
tracer=system.cpu.tracer
|
||||||
|
workload=system.cpu.workload
|
||||||
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.dcache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=262144
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.dcache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.dtb]
|
||||||
|
type=X86DTB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.icache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=131072
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.icache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.itb]
|
||||||
|
type=X86ITB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.l2cache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=10000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=100000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=2097152
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.toL2Bus.port[2]
|
||||||
|
mem_side=system.membus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.toL2Bus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.tracer]
|
||||||
|
type=ExeTracer
|
||||||
|
|
||||||
|
[system.cpu.workload]
|
||||||
|
type=LiveProcess
|
||||||
|
cmd=mcf mcf.in
|
||||||
|
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
||||||
|
egid=100
|
||||||
|
env=
|
||||||
|
errout=cerr
|
||||||
|
euid=100
|
||||||
|
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||||
|
gid=100
|
||||||
|
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||||
|
max_stack_size=67108864
|
||||||
|
output=cout
|
||||||
|
pid=100
|
||||||
|
ppid=99
|
||||||
|
simpoint=55300000000
|
||||||
|
system=system
|
||||||
|
uid=100
|
||||||
|
|
||||||
|
[system.membus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||||
|
|
||||||
|
[system.physmem]
|
||||||
|
type=PhysicalMemory
|
||||||
|
file=
|
||||||
|
latency=30000
|
||||||
|
latency_var=0
|
||||||
|
null=false
|
||||||
|
range=0:268435455
|
||||||
|
zero=false
|
||||||
|
port=system.membus.port[0]
|
||||||
|
|
234
tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt
Normal file
234
tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,234 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 1094085 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 336424 # Number of bytes of host memory used
|
||||||
|
host_seconds 246.51 # Real time elapsed on the host
|
||||||
|
host_tick_rate 2009645019 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 269697303 # Number of instructions simulated
|
||||||
|
sim_seconds 0.495388 # Number of seconds simulated
|
||||||
|
sim_ticks 495387670000 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 55999.899641 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.899641 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 12833889000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 12146358000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 20116.007644 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 43840123000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 37302028000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 20116.007644 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 120039828 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 43840123000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 2179365 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 37302028000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 2049944 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 229129 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 807 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 331462528 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 807 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 24 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 5400304000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses
|
||||||
|
system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 10027680000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 1862007 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 10027680000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 192840 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 108885 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 70892 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 990775340 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 269697303 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 124054655 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
999
tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
Normal file
999
tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
Normal file
|
@ -0,0 +1,999 @@
|
||||||
|
()
|
||||||
|
500
|
||||||
|
()
|
||||||
|
499
|
||||||
|
()
|
||||||
|
498
|
||||||
|
()
|
||||||
|
496
|
||||||
|
()
|
||||||
|
495
|
||||||
|
()
|
||||||
|
494
|
||||||
|
()
|
||||||
|
493
|
||||||
|
()
|
||||||
|
492
|
||||||
|
()
|
||||||
|
491
|
||||||
|
()
|
||||||
|
490
|
||||||
|
()
|
||||||
|
489
|
||||||
|
()
|
||||||
|
488
|
||||||
|
()
|
||||||
|
487
|
||||||
|
()
|
||||||
|
486
|
||||||
|
()
|
||||||
|
484
|
||||||
|
()
|
||||||
|
482
|
||||||
|
()
|
||||||
|
481
|
||||||
|
()
|
||||||
|
480
|
||||||
|
()
|
||||||
|
479
|
||||||
|
()
|
||||||
|
478
|
||||||
|
()
|
||||||
|
477
|
||||||
|
()
|
||||||
|
476
|
||||||
|
()
|
||||||
|
475
|
||||||
|
()
|
||||||
|
474
|
||||||
|
()
|
||||||
|
473
|
||||||
|
()
|
||||||
|
472
|
||||||
|
()
|
||||||
|
471
|
||||||
|
()
|
||||||
|
469
|
||||||
|
()
|
||||||
|
468
|
||||||
|
()
|
||||||
|
467
|
||||||
|
()
|
||||||
|
466
|
||||||
|
()
|
||||||
|
465
|
||||||
|
()
|
||||||
|
464
|
||||||
|
()
|
||||||
|
463
|
||||||
|
()
|
||||||
|
462
|
||||||
|
()
|
||||||
|
461
|
||||||
|
()
|
||||||
|
460
|
||||||
|
()
|
||||||
|
459
|
||||||
|
()
|
||||||
|
458
|
||||||
|
()
|
||||||
|
457
|
||||||
|
()
|
||||||
|
455
|
||||||
|
()
|
||||||
|
454
|
||||||
|
()
|
||||||
|
452
|
||||||
|
()
|
||||||
|
451
|
||||||
|
()
|
||||||
|
450
|
||||||
|
()
|
||||||
|
449
|
||||||
|
()
|
||||||
|
448
|
||||||
|
()
|
||||||
|
446
|
||||||
|
()
|
||||||
|
445
|
||||||
|
()
|
||||||
|
444
|
||||||
|
()
|
||||||
|
443
|
||||||
|
()
|
||||||
|
442
|
||||||
|
()
|
||||||
|
440
|
||||||
|
()
|
||||||
|
439
|
||||||
|
()
|
||||||
|
438
|
||||||
|
()
|
||||||
|
436
|
||||||
|
()
|
||||||
|
435
|
||||||
|
()
|
||||||
|
433
|
||||||
|
()
|
||||||
|
432
|
||||||
|
()
|
||||||
|
431
|
||||||
|
()
|
||||||
|
428
|
||||||
|
()
|
||||||
|
427
|
||||||
|
()
|
||||||
|
425
|
||||||
|
()
|
||||||
|
424
|
||||||
|
()
|
||||||
|
423
|
||||||
|
()
|
||||||
|
420
|
||||||
|
()
|
||||||
|
419
|
||||||
|
()
|
||||||
|
416
|
||||||
|
()
|
||||||
|
414
|
||||||
|
()
|
||||||
|
413
|
||||||
|
()
|
||||||
|
412
|
||||||
|
()
|
||||||
|
407
|
||||||
|
()
|
||||||
|
406
|
||||||
|
()
|
||||||
|
405
|
||||||
|
()
|
||||||
|
404
|
||||||
|
()
|
||||||
|
403
|
||||||
|
()
|
||||||
|
402
|
||||||
|
()
|
||||||
|
401
|
||||||
|
()
|
||||||
|
400
|
||||||
|
()
|
||||||
|
399
|
||||||
|
()
|
||||||
|
398
|
||||||
|
()
|
||||||
|
396
|
||||||
|
()
|
||||||
|
395
|
||||||
|
()
|
||||||
|
393
|
||||||
|
()
|
||||||
|
392
|
||||||
|
()
|
||||||
|
390
|
||||||
|
()
|
||||||
|
389
|
||||||
|
()
|
||||||
|
388
|
||||||
|
()
|
||||||
|
387
|
||||||
|
()
|
||||||
|
386
|
||||||
|
()
|
||||||
|
385
|
||||||
|
()
|
||||||
|
384
|
||||||
|
()
|
||||||
|
383
|
||||||
|
()
|
||||||
|
382
|
||||||
|
()
|
||||||
|
381
|
||||||
|
()
|
||||||
|
380
|
||||||
|
()
|
||||||
|
379
|
||||||
|
()
|
||||||
|
377
|
||||||
|
()
|
||||||
|
375
|
||||||
|
()
|
||||||
|
374
|
||||||
|
()
|
||||||
|
373
|
||||||
|
()
|
||||||
|
372
|
||||||
|
()
|
||||||
|
371
|
||||||
|
()
|
||||||
|
370
|
||||||
|
()
|
||||||
|
369
|
||||||
|
()
|
||||||
|
368
|
||||||
|
()
|
||||||
|
366
|
||||||
|
()
|
||||||
|
365
|
||||||
|
()
|
||||||
|
364
|
||||||
|
()
|
||||||
|
362
|
||||||
|
()
|
||||||
|
361
|
||||||
|
()
|
||||||
|
360
|
||||||
|
()
|
||||||
|
359
|
||||||
|
()
|
||||||
|
358
|
||||||
|
()
|
||||||
|
357
|
||||||
|
()
|
||||||
|
356
|
||||||
|
()
|
||||||
|
355
|
||||||
|
()
|
||||||
|
354
|
||||||
|
()
|
||||||
|
352
|
||||||
|
()
|
||||||
|
350
|
||||||
|
()
|
||||||
|
347
|
||||||
|
()
|
||||||
|
344
|
||||||
|
()
|
||||||
|
342
|
||||||
|
()
|
||||||
|
341
|
||||||
|
()
|
||||||
|
340
|
||||||
|
()
|
||||||
|
339
|
||||||
|
()
|
||||||
|
338
|
||||||
|
()
|
||||||
|
332
|
||||||
|
()
|
||||||
|
325
|
||||||
|
()
|
||||||
|
320
|
||||||
|
***
|
||||||
|
345
|
||||||
|
()
|
||||||
|
319
|
||||||
|
***
|
||||||
|
497
|
||||||
|
()
|
||||||
|
318
|
||||||
|
***
|
||||||
|
349
|
||||||
|
()
|
||||||
|
317
|
||||||
|
***
|
||||||
|
408
|
||||||
|
()
|
||||||
|
316
|
||||||
|
***
|
||||||
|
324
|
||||||
|
()
|
||||||
|
315
|
||||||
|
***
|
||||||
|
328
|
||||||
|
()
|
||||||
|
314
|
||||||
|
***
|
||||||
|
335
|
||||||
|
()
|
||||||
|
313
|
||||||
|
***
|
||||||
|
378
|
||||||
|
()
|
||||||
|
312
|
||||||
|
***
|
||||||
|
426
|
||||||
|
()
|
||||||
|
311
|
||||||
|
***
|
||||||
|
411
|
||||||
|
()
|
||||||
|
304
|
||||||
|
***
|
||||||
|
343
|
||||||
|
()
|
||||||
|
303
|
||||||
|
***
|
||||||
|
417
|
||||||
|
()
|
||||||
|
302
|
||||||
|
***
|
||||||
|
485
|
||||||
|
()
|
||||||
|
301
|
||||||
|
***
|
||||||
|
363
|
||||||
|
()
|
||||||
|
300
|
||||||
|
***
|
||||||
|
376
|
||||||
|
()
|
||||||
|
299
|
||||||
|
***
|
||||||
|
333
|
||||||
|
()
|
||||||
|
292
|
||||||
|
***
|
||||||
|
337
|
||||||
|
()
|
||||||
|
291
|
||||||
|
***
|
||||||
|
409
|
||||||
|
()
|
||||||
|
290
|
||||||
|
***
|
||||||
|
421
|
||||||
|
()
|
||||||
|
289
|
||||||
|
***
|
||||||
|
437
|
||||||
|
()
|
||||||
|
288
|
||||||
|
***
|
||||||
|
430
|
||||||
|
()
|
||||||
|
287
|
||||||
|
***
|
||||||
|
348
|
||||||
|
()
|
||||||
|
286
|
||||||
|
***
|
||||||
|
326
|
||||||
|
()
|
||||||
|
284
|
||||||
|
()
|
||||||
|
282
|
||||||
|
***
|
||||||
|
308
|
||||||
|
()
|
||||||
|
279
|
||||||
|
***
|
||||||
|
297
|
||||||
|
***
|
||||||
|
305
|
||||||
|
()
|
||||||
|
278
|
||||||
|
()
|
||||||
|
277
|
||||||
|
***
|
||||||
|
307
|
||||||
|
()
|
||||||
|
276
|
||||||
|
***
|
||||||
|
296
|
||||||
|
()
|
||||||
|
273
|
||||||
|
()
|
||||||
|
271
|
||||||
|
()
|
||||||
|
265
|
||||||
|
()
|
||||||
|
246
|
||||||
|
***
|
||||||
|
267
|
||||||
|
()
|
||||||
|
245
|
||||||
|
***
|
||||||
|
280
|
||||||
|
()
|
||||||
|
244
|
||||||
|
***
|
||||||
|
391
|
||||||
|
()
|
||||||
|
243
|
||||||
|
***
|
||||||
|
330
|
||||||
|
()
|
||||||
|
242
|
||||||
|
***
|
||||||
|
456
|
||||||
|
()
|
||||||
|
241
|
||||||
|
***
|
||||||
|
346
|
||||||
|
()
|
||||||
|
240
|
||||||
|
***
|
||||||
|
483
|
||||||
|
()
|
||||||
|
239
|
||||||
|
***
|
||||||
|
260
|
||||||
|
()
|
||||||
|
238
|
||||||
|
***
|
||||||
|
261
|
||||||
|
()
|
||||||
|
237
|
||||||
|
***
|
||||||
|
262
|
||||||
|
***
|
||||||
|
294
|
||||||
|
()
|
||||||
|
236
|
||||||
|
***
|
||||||
|
253
|
||||||
|
()
|
||||||
|
229
|
||||||
|
***
|
||||||
|
397
|
||||||
|
()
|
||||||
|
228
|
||||||
|
***
|
||||||
|
298
|
||||||
|
()
|
||||||
|
227
|
||||||
|
***
|
||||||
|
415
|
||||||
|
()
|
||||||
|
226
|
||||||
|
***
|
||||||
|
264
|
||||||
|
()
|
||||||
|
224
|
||||||
|
***
|
||||||
|
232
|
||||||
|
()
|
||||||
|
222
|
||||||
|
***
|
||||||
|
233
|
||||||
|
()
|
||||||
|
217
|
||||||
|
***
|
||||||
|
250
|
||||||
|
()
|
||||||
|
211
|
||||||
|
***
|
||||||
|
331
|
||||||
|
()
|
||||||
|
210
|
||||||
|
***
|
||||||
|
394
|
||||||
|
()
|
||||||
|
209
|
||||||
|
***
|
||||||
|
410
|
||||||
|
()
|
||||||
|
208
|
||||||
|
***
|
||||||
|
321
|
||||||
|
()
|
||||||
|
207
|
||||||
|
***
|
||||||
|
327
|
||||||
|
()
|
||||||
|
206
|
||||||
|
***
|
||||||
|
309
|
||||||
|
()
|
||||||
|
199
|
||||||
|
***
|
||||||
|
259
|
||||||
|
()
|
||||||
|
198
|
||||||
|
***
|
||||||
|
219
|
||||||
|
()
|
||||||
|
197
|
||||||
|
***
|
||||||
|
220
|
||||||
|
()
|
||||||
|
195
|
||||||
|
***
|
||||||
|
429
|
||||||
|
()
|
||||||
|
194
|
||||||
|
***
|
||||||
|
470
|
||||||
|
()
|
||||||
|
193
|
||||||
|
***
|
||||||
|
274
|
||||||
|
()
|
||||||
|
191
|
||||||
|
***
|
||||||
|
203
|
||||||
|
()
|
||||||
|
190
|
||||||
|
***
|
||||||
|
263
|
||||||
|
()
|
||||||
|
189
|
||||||
|
215
|
||||||
|
***
|
||||||
|
230
|
||||||
|
()
|
||||||
|
188
|
||||||
|
***
|
||||||
|
266
|
||||||
|
***
|
||||||
|
295
|
||||||
|
()
|
||||||
|
182
|
||||||
|
***
|
||||||
|
329
|
||||||
|
()
|
||||||
|
181
|
||||||
|
***
|
||||||
|
351
|
||||||
|
()
|
||||||
|
180
|
||||||
|
***
|
||||||
|
441
|
||||||
|
()
|
||||||
|
179
|
||||||
|
***
|
||||||
|
453
|
||||||
|
()
|
||||||
|
178
|
||||||
|
***
|
||||||
|
418
|
||||||
|
()
|
||||||
|
177
|
||||||
|
***
|
||||||
|
353
|
||||||
|
()
|
||||||
|
176
|
||||||
|
***
|
||||||
|
422
|
||||||
|
()
|
||||||
|
175
|
||||||
|
***
|
||||||
|
225
|
||||||
|
***
|
||||||
|
255
|
||||||
|
()
|
||||||
|
174
|
||||||
|
***
|
||||||
|
269
|
||||||
|
()
|
||||||
|
173
|
||||||
|
***
|
||||||
|
214
|
||||||
|
()
|
||||||
|
172
|
||||||
|
***
|
||||||
|
186
|
||||||
|
()
|
||||||
|
171
|
||||||
|
***
|
||||||
|
447
|
||||||
|
()
|
||||||
|
170
|
||||||
|
***
|
||||||
|
270
|
||||||
|
***
|
||||||
|
306
|
||||||
|
()
|
||||||
|
169
|
||||||
|
***
|
||||||
|
336
|
||||||
|
()
|
||||||
|
168
|
||||||
|
***
|
||||||
|
285
|
||||||
|
()
|
||||||
|
165
|
||||||
|
***
|
||||||
|
249
|
||||||
|
()
|
||||||
|
146
|
||||||
|
***
|
||||||
|
154
|
||||||
|
()
|
||||||
|
143
|
||||||
|
***
|
||||||
|
334
|
||||||
|
()
|
||||||
|
142
|
||||||
|
***
|
||||||
|
216
|
||||||
|
***
|
||||||
|
257
|
||||||
|
()
|
||||||
|
141
|
||||||
|
***
|
||||||
|
167
|
||||||
|
***
|
||||||
|
251
|
||||||
|
()
|
||||||
|
140
|
||||||
|
***
|
||||||
|
162
|
||||||
|
***
|
||||||
|
293
|
||||||
|
()
|
||||||
|
139
|
||||||
|
***
|
||||||
|
158
|
||||||
|
()
|
||||||
|
137
|
||||||
|
***
|
||||||
|
166
|
||||||
|
***
|
||||||
|
201
|
||||||
|
()
|
||||||
|
136
|
||||||
|
***
|
||||||
|
160
|
||||||
|
()
|
||||||
|
134
|
||||||
|
***
|
||||||
|
221
|
||||||
|
()
|
||||||
|
132
|
||||||
|
***
|
||||||
|
213
|
||||||
|
()
|
||||||
|
131
|
||||||
|
***
|
||||||
|
187
|
||||||
|
()
|
||||||
|
129
|
||||||
|
***
|
||||||
|
235
|
||||||
|
()
|
||||||
|
128
|
||||||
|
***
|
||||||
|
153
|
||||||
|
()
|
||||||
|
127
|
||||||
|
***
|
||||||
|
156
|
||||||
|
()
|
||||||
|
126
|
||||||
|
***
|
||||||
|
159
|
||||||
|
***
|
||||||
|
218
|
||||||
|
()
|
||||||
|
125
|
||||||
|
***
|
||||||
|
155
|
||||||
|
()
|
||||||
|
124
|
||||||
|
***
|
||||||
|
157
|
||||||
|
()
|
||||||
|
123
|
||||||
|
***
|
||||||
|
152
|
||||||
|
()
|
||||||
|
116
|
||||||
|
***
|
||||||
|
135
|
||||||
|
***
|
||||||
|
163
|
||||||
|
()
|
||||||
|
115
|
||||||
|
***
|
||||||
|
133
|
||||||
|
***
|
||||||
|
204
|
||||||
|
***
|
||||||
|
248
|
||||||
|
()
|
||||||
|
114
|
||||||
|
***
|
||||||
|
192
|
||||||
|
***
|
||||||
|
212
|
||||||
|
()
|
||||||
|
113
|
||||||
|
***
|
||||||
|
268
|
||||||
|
()
|
||||||
|
112
|
||||||
|
***
|
||||||
|
367
|
||||||
|
()
|
||||||
|
111
|
||||||
|
***
|
||||||
|
272
|
||||||
|
()
|
||||||
|
110
|
||||||
|
***
|
||||||
|
434
|
||||||
|
()
|
||||||
|
109
|
||||||
|
***
|
||||||
|
323
|
||||||
|
()
|
||||||
|
108
|
||||||
|
***
|
||||||
|
281
|
||||||
|
()
|
||||||
|
107
|
||||||
|
***
|
||||||
|
144
|
||||||
|
***
|
||||||
|
148
|
||||||
|
()
|
||||||
|
106
|
||||||
|
***
|
||||||
|
275
|
||||||
|
()
|
||||||
|
105
|
||||||
|
***
|
||||||
|
196
|
||||||
|
***
|
||||||
|
254
|
||||||
|
()
|
||||||
|
104
|
||||||
|
***
|
||||||
|
138
|
||||||
|
***
|
||||||
|
161
|
||||||
|
()
|
||||||
|
103
|
||||||
|
***
|
||||||
|
310
|
||||||
|
()
|
||||||
|
102
|
||||||
|
***
|
||||||
|
223
|
||||||
|
***
|
||||||
|
252
|
||||||
|
()
|
||||||
|
80
|
||||||
|
()
|
||||||
|
70
|
||||||
|
()
|
||||||
|
69
|
||||||
|
()
|
||||||
|
68
|
||||||
|
()
|
||||||
|
66
|
||||||
|
()
|
||||||
|
64
|
||||||
|
()
|
||||||
|
62
|
||||||
|
***
|
||||||
|
256
|
||||||
|
()
|
||||||
|
61
|
||||||
|
***
|
||||||
|
93
|
||||||
|
()
|
||||||
|
59
|
||||||
|
***
|
||||||
|
120
|
||||||
|
()
|
||||||
|
58
|
||||||
|
()
|
||||||
|
57
|
||||||
|
***
|
||||||
|
183
|
||||||
|
()
|
||||||
|
55
|
||||||
|
()
|
||||||
|
54
|
||||||
|
()
|
||||||
|
52
|
||||||
|
***
|
||||||
|
147
|
||||||
|
()
|
||||||
|
51
|
||||||
|
***
|
||||||
|
118
|
||||||
|
()
|
||||||
|
50
|
||||||
|
***
|
||||||
|
83
|
||||||
|
()
|
||||||
|
49
|
||||||
|
***
|
||||||
|
98
|
||||||
|
()
|
||||||
|
48
|
||||||
|
***
|
||||||
|
99
|
||||||
|
()
|
||||||
|
47
|
||||||
|
()
|
||||||
|
46
|
||||||
|
***
|
||||||
|
184
|
||||||
|
()
|
||||||
|
45
|
||||||
|
***
|
||||||
|
121
|
||||||
|
()
|
||||||
|
44
|
||||||
|
()
|
||||||
|
43
|
||||||
|
***
|
||||||
|
88
|
||||||
|
()
|
||||||
|
42
|
||||||
|
***
|
||||||
|
122
|
||||||
|
()
|
||||||
|
41
|
||||||
|
***
|
||||||
|
91
|
||||||
|
()
|
||||||
|
40
|
||||||
|
***
|
||||||
|
96
|
||||||
|
()
|
||||||
|
38
|
||||||
|
***
|
||||||
|
100
|
||||||
|
()
|
||||||
|
37
|
||||||
|
***
|
||||||
|
149
|
||||||
|
()
|
||||||
|
36
|
||||||
|
***
|
||||||
|
74
|
||||||
|
()
|
||||||
|
35
|
||||||
|
***
|
||||||
|
258
|
||||||
|
()
|
||||||
|
34
|
||||||
|
***
|
||||||
|
151
|
||||||
|
()
|
||||||
|
33
|
||||||
|
***
|
||||||
|
85
|
||||||
|
()
|
||||||
|
32
|
||||||
|
()
|
||||||
|
31
|
||||||
|
***
|
||||||
|
94
|
||||||
|
()
|
||||||
|
30
|
||||||
|
***
|
||||||
|
97
|
||||||
|
()
|
||||||
|
29
|
||||||
|
***
|
||||||
|
90
|
||||||
|
()
|
||||||
|
28
|
||||||
|
***
|
||||||
|
89
|
||||||
|
()
|
||||||
|
27
|
||||||
|
***
|
||||||
|
92
|
||||||
|
()
|
||||||
|
26
|
||||||
|
***
|
||||||
|
72
|
||||||
|
***
|
||||||
|
247
|
||||||
|
()
|
||||||
|
25
|
||||||
|
***
|
||||||
|
86
|
||||||
|
()
|
||||||
|
24
|
||||||
|
***
|
||||||
|
82
|
||||||
|
()
|
||||||
|
23
|
||||||
|
***
|
||||||
|
87
|
||||||
|
***
|
||||||
|
117
|
||||||
|
()
|
||||||
|
22
|
||||||
|
***
|
||||||
|
76
|
||||||
|
***
|
||||||
|
119
|
||||||
|
()
|
||||||
|
21
|
||||||
|
***
|
||||||
|
84
|
||||||
|
()
|
||||||
|
20
|
||||||
|
***
|
||||||
|
78
|
||||||
|
()
|
||||||
|
19
|
||||||
|
***
|
||||||
|
73
|
||||||
|
()
|
||||||
|
18
|
||||||
|
***
|
||||||
|
81
|
||||||
|
()
|
||||||
|
17
|
||||||
|
***
|
||||||
|
65
|
||||||
|
()
|
||||||
|
16
|
||||||
|
***
|
||||||
|
63
|
||||||
|
***
|
||||||
|
101
|
||||||
|
()
|
||||||
|
15
|
||||||
|
***
|
||||||
|
71
|
||||||
|
()
|
||||||
|
14
|
||||||
|
***
|
||||||
|
75
|
||||||
|
()
|
||||||
|
13
|
||||||
|
***
|
||||||
|
322
|
||||||
|
()
|
||||||
|
12
|
||||||
|
***
|
||||||
|
77
|
||||||
|
()
|
||||||
|
11
|
||||||
|
***
|
||||||
|
283
|
||||||
|
()
|
||||||
|
10
|
||||||
|
***
|
||||||
|
79
|
||||||
|
()
|
||||||
|
9
|
||||||
|
***
|
||||||
|
145
|
||||||
|
***
|
||||||
|
150
|
||||||
|
()
|
||||||
|
8
|
||||||
|
***
|
||||||
|
67
|
||||||
|
()
|
||||||
|
7
|
||||||
|
***
|
||||||
|
60
|
||||||
|
***
|
||||||
|
231
|
||||||
|
()
|
||||||
|
6
|
||||||
|
***
|
||||||
|
56
|
||||||
|
***
|
||||||
|
234
|
||||||
|
()
|
||||||
|
5
|
||||||
|
***
|
||||||
|
164
|
||||||
|
***
|
||||||
|
202
|
||||||
|
()
|
||||||
|
4
|
||||||
|
***
|
||||||
|
53
|
||||||
|
()
|
||||||
|
3
|
||||||
|
***
|
||||||
|
130
|
||||||
|
***
|
||||||
|
185
|
||||||
|
***
|
||||||
|
200
|
||||||
|
()
|
||||||
|
2
|
||||||
|
***
|
||||||
|
205
|
||||||
|
()
|
||||||
|
1
|
||||||
|
***
|
||||||
|
39
|
||||||
|
***
|
||||||
|
95
|
4
tests/long/10.mcf/ref/x86/linux/simple-timing/stderr
Executable file
4
tests/long/10.mcf/ref/x86/linux/simple-timing/stderr
Executable file
|
@ -0,0 +1,4 @@
|
||||||
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
|
warn: instruction 'fnstcw_Mw' unimplemented
|
||||||
|
warn: instruction 'fldcw_Mw' unimplemented
|
||||||
|
warn: be nice to actually delete the event here
|
32
tests/long/10.mcf/ref/x86/linux/simple-timing/stdout
Executable file
32
tests/long/10.mcf/ref/x86/linux/simple-timing/stdout
Executable file
|
@ -0,0 +1,32 @@
|
||||||
|
M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2008
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Nov 7 2008 03:21:37
|
||||||
|
M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
|
||||||
|
M5 commit date Thu Nov 06 23:13:50 2008 -0800
|
||||||
|
M5 started Nov 8 2008 01:13:22
|
||||||
|
M5 executing on tater
|
||||||
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing
|
||||||
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
MCF SPEC version 1.6.I
|
||||||
|
by Andreas Loebel
|
||||||
|
Copyright (c) 1998,1999 ZIB Berlin
|
||||||
|
All Rights Reserved.
|
||||||
|
|
||||||
|
nodes : 500
|
||||||
|
active arcs : 1905
|
||||||
|
simplex iterations : 1502
|
||||||
|
flow value : 4990014995
|
||||||
|
new implicit arcs : 23867
|
||||||
|
active arcs : 25772
|
||||||
|
simplex iterations : 2663
|
||||||
|
flow value : 3080014995
|
||||||
|
checksum : 68389
|
||||||
|
optimal
|
||||||
|
Exiting @ tick 495387670000 because target called exit()
|
193
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
Normal file
193
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
Normal file
|
@ -0,0 +1,193 @@
|
||||||
|
[root]
|
||||||
|
type=Root
|
||||||
|
children=system
|
||||||
|
dummy=0
|
||||||
|
|
||||||
|
[system]
|
||||||
|
type=System
|
||||||
|
children=cpu membus physmem
|
||||||
|
mem_mode=atomic
|
||||||
|
physmem=system.physmem
|
||||||
|
|
||||||
|
[system.cpu]
|
||||||
|
type=TimingSimpleCPU
|
||||||
|
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||||
|
clock=500
|
||||||
|
cpu_id=0
|
||||||
|
defer_registration=false
|
||||||
|
dtb=system.cpu.dtb
|
||||||
|
function_trace=false
|
||||||
|
function_trace_start=0
|
||||||
|
itb=system.cpu.itb
|
||||||
|
max_insts_all_threads=0
|
||||||
|
max_insts_any_thread=0
|
||||||
|
max_loads_all_threads=0
|
||||||
|
max_loads_any_thread=0
|
||||||
|
numThreads=1
|
||||||
|
phase=0
|
||||||
|
progress_interval=0
|
||||||
|
system=system
|
||||||
|
tracer=system.cpu.tracer
|
||||||
|
workload=system.cpu.workload
|
||||||
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.dcache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=262144
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.dcache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.dtb]
|
||||||
|
type=X86DTB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.icache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=131072
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.icache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.itb]
|
||||||
|
type=X86ITB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.l2cache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=10000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=100000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=2097152
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.toL2Bus.port[2]
|
||||||
|
mem_side=system.membus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.toL2Bus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.tracer]
|
||||||
|
type=ExeTracer
|
||||||
|
|
||||||
|
[system.cpu.workload]
|
||||||
|
type=LiveProcess
|
||||||
|
cmd=parser 2.1.dict -batch
|
||||||
|
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||||
|
egid=100
|
||||||
|
env=
|
||||||
|
errout=cerr
|
||||||
|
euid=100
|
||||||
|
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||||
|
gid=100
|
||||||
|
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||||
|
max_stack_size=67108864
|
||||||
|
output=cout
|
||||||
|
pid=100
|
||||||
|
ppid=99
|
||||||
|
simpoint=114600000000
|
||||||
|
system=system
|
||||||
|
uid=100
|
||||||
|
|
||||||
|
[system.membus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||||
|
|
||||||
|
[system.physmem]
|
||||||
|
type=PhysicalMemory
|
||||||
|
file=
|
||||||
|
latency=30000
|
||||||
|
latency_var=0
|
||||||
|
null=false
|
||||||
|
range=0:134217727
|
||||||
|
zero=false
|
||||||
|
port=system.membus.port[0]
|
||||||
|
|
234
tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt
Normal file
234
tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,234 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 588841 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 206816 # Number of bytes of host memory used
|
||||||
|
host_seconds 2539.72 # Real time elapsed on the host
|
||||||
|
host_tick_rate 941590971 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 1495492697 # Number of instructions simulated
|
||||||
|
sim_seconds 2.391380 # Number of seconds simulated
|
||||||
|
sim_ticks 2391380378000 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 530069450 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 3192961 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 2513875 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 1463913 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 1737372102 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 2813 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 1253 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses
|
||||||
|
system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 1310104 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 1210680 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 663512 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 481430 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 4782760756 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 1495492697 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 533549000 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
7
tests/long/20.parser/ref/x86/linux/simple-timing/stderr
Executable file
7
tests/long/20.parser/ref/x86/linux/simple-timing/stderr
Executable file
|
@ -0,0 +1,7 @@
|
||||||
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
|
warn: instruction 'fnstcw_Mw' unimplemented
|
||||||
|
warn: instruction 'fldcw_Mw' unimplemented
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: be nice to actually delete the event here
|
75
tests/long/20.parser/ref/x86/linux/simple-timing/stdout
Executable file
75
tests/long/20.parser/ref/x86/linux/simple-timing/stdout
Executable file
|
@ -0,0 +1,75 @@
|
||||||
|
M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2008
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Nov 9 2008 18:23:31
|
||||||
|
M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e
|
||||||
|
M5 commit date Sat Nov 08 21:06:07 2008 -0800
|
||||||
|
M5 started Nov 9 2008 18:34:37
|
||||||
|
M5 executing on tater
|
||||||
|
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing
|
||||||
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
Reading the dictionary files: *************************************************
|
||||||
|
58924 words stored in 3784810 bytes
|
||||||
|
|
||||||
|
|
||||||
|
Welcome to the Link Parser -- Version 2.1
|
||||||
|
|
||||||
|
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||||
|
|
||||||
|
Processing sentences in batch mode
|
||||||
|
|
||||||
|
Echoing of input sentence turned on.
|
||||||
|
* as had expected the party to be a success , it was a success
|
||||||
|
* do you know where John 's
|
||||||
|
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||||
|
* how fast the program is it
|
||||||
|
* I am wondering whether to invite to the party
|
||||||
|
* I gave him for his birthday it
|
||||||
|
* I thought terrible after our discussion
|
||||||
|
* I wonder how much money have you earned
|
||||||
|
* Janet who is an expert on dogs helped me choose one
|
||||||
|
* she interviewed more programmers than was hired
|
||||||
|
* such flowers are found chiefly particularly in Europe
|
||||||
|
* the dogs some of which were very large ran after the man
|
||||||
|
* the man whom I play tennis is here
|
||||||
|
* there is going to be an important meeting January
|
||||||
|
* to pretend that our program is usable in its current form would be happy
|
||||||
|
* we're thinking about going to a movie this theater
|
||||||
|
* which dog you said you chased
|
||||||
|
- also invited to the meeting were several prominent scientists
|
||||||
|
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||||
|
- so many people attended that they spilled over into several neighboring fields
|
||||||
|
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||||
|
: Grace may not be possible to fix the problem
|
||||||
|
any program as good as ours should be useful
|
||||||
|
biochemically , I think the experiment has a lot of problems
|
||||||
|
Fred has had five years of experience as a programmer
|
||||||
|
he is looking for another job
|
||||||
|
how did John do it
|
||||||
|
how many more people do you think will come
|
||||||
|
how much more spilled
|
||||||
|
I have more money than John has time
|
||||||
|
I made it clear that I was angry
|
||||||
|
I wonder how John did it
|
||||||
|
I wonder how much more quickly he ran
|
||||||
|
invite John and whoever else you want to invite
|
||||||
|
it is easier to ignore the problem than it is to solve it
|
||||||
|
many who initially supported Thomas later changed their minds
|
||||||
|
neither Mary nor Louise are coming to the party
|
||||||
|
she interviewed more programmers than were hired
|
||||||
|
telling Joe that Sue was coming to the party would create a real problem
|
||||||
|
the man with whom I play tennis is here
|
||||||
|
there is a dog in the park
|
||||||
|
this is not the man we know and love
|
||||||
|
we like to eat at restaurants , usually on weekends
|
||||||
|
what did John say he thought you should do
|
||||||
|
about 2 million people attended
|
||||||
|
the five best costumes got prizes
|
||||||
|
No errors!
|
||||||
|
Exiting @ tick 2391380378000 because target called exit()
|
193
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
Normal file
193
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
Normal file
|
@ -0,0 +1,193 @@
|
||||||
|
[root]
|
||||||
|
type=Root
|
||||||
|
children=system
|
||||||
|
dummy=0
|
||||||
|
|
||||||
|
[system]
|
||||||
|
type=System
|
||||||
|
children=cpu membus physmem
|
||||||
|
mem_mode=atomic
|
||||||
|
physmem=system.physmem
|
||||||
|
|
||||||
|
[system.cpu]
|
||||||
|
type=TimingSimpleCPU
|
||||||
|
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||||
|
clock=500
|
||||||
|
cpu_id=0
|
||||||
|
defer_registration=false
|
||||||
|
dtb=system.cpu.dtb
|
||||||
|
function_trace=false
|
||||||
|
function_trace_start=0
|
||||||
|
itb=system.cpu.itb
|
||||||
|
max_insts_all_threads=0
|
||||||
|
max_insts_any_thread=0
|
||||||
|
max_loads_all_threads=0
|
||||||
|
max_loads_any_thread=0
|
||||||
|
numThreads=1
|
||||||
|
phase=0
|
||||||
|
progress_interval=0
|
||||||
|
system=system
|
||||||
|
tracer=system.cpu.tracer
|
||||||
|
workload=system.cpu.workload
|
||||||
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.dcache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=262144
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.dcache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.dtb]
|
||||||
|
type=X86DTB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.icache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=131072
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.icache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.itb]
|
||||||
|
type=X86ITB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.l2cache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=10000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=100000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=2097152
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.toL2Bus.port[2]
|
||||||
|
mem_side=system.membus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.toL2Bus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.tracer]
|
||||||
|
type=ExeTracer
|
||||||
|
|
||||||
|
[system.cpu.workload]
|
||||||
|
type=LiveProcess
|
||||||
|
cmd=bzip2 input.source 1
|
||||||
|
cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
||||||
|
egid=100
|
||||||
|
env=
|
||||||
|
errout=cerr
|
||||||
|
euid=100
|
||||||
|
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||||
|
gid=100
|
||||||
|
input=cin
|
||||||
|
max_stack_size=67108864
|
||||||
|
output=cout
|
||||||
|
pid=100
|
||||||
|
ppid=99
|
||||||
|
simpoint=0
|
||||||
|
system=system
|
||||||
|
uid=100
|
||||||
|
|
||||||
|
[system.membus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||||
|
|
||||||
|
[system.physmem]
|
||||||
|
type=PhysicalMemory
|
||||||
|
file=
|
||||||
|
latency=30000
|
||||||
|
latency_var=0
|
||||||
|
null=false
|
||||||
|
range=0:134217727
|
||||||
|
zero=false
|
||||||
|
port=system.membus.port[0]
|
||||||
|
|
234
tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt
Normal file
234
tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,234 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 1139442 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 201800 # Number of bytes of host memory used
|
||||||
|
host_seconds 4083.77 # Real time elapsed on the host
|
||||||
|
host_tick_rate 1872105757 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 4653219791 # Number of instructions simulated
|
||||||
|
sim_seconds 7.645253 # Number of seconds simulated
|
||||||
|
sim_ticks 7645253019000 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 1668242528 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 9470550 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 9108982 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 2244013 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 5670421196 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 675 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 10 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses
|
||||||
|
system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 5328546 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 3785207 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 2772128 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 1199171 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 15290506038 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 4653219791 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 1686313781 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
7
tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr
Executable file
7
tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr
Executable file
|
@ -0,0 +1,7 @@
|
||||||
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
|
warn: instruction 'fnstcw_Mw' unimplemented
|
||||||
|
warn: instruction 'fldcw_Mw' unimplemented
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: be nice to actually delete the event here
|
30
tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout
Executable file
30
tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout
Executable file
|
@ -0,0 +1,30 @@
|
||||||
|
M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2008
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Nov 7 2008 03:21:37
|
||||||
|
M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
|
||||||
|
M5 commit date Thu Nov 06 23:13:50 2008 -0800
|
||||||
|
M5 started Nov 8 2008 10:43:38
|
||||||
|
M5 executing on tater
|
||||||
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing
|
||||||
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
spec_init
|
||||||
|
Loading Input Data
|
||||||
|
Input data 1048576 bytes in length
|
||||||
|
Compressing Input Data, level 7
|
||||||
|
Compressed data 198546 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Compressing Input Data, level 9
|
||||||
|
Compressed data 198677 bytes in length
|
||||||
|
Uncompressing Data
|
||||||
|
Uncompressed data 1048576 bytes in length
|
||||||
|
Uncompressed data compared correctly
|
||||||
|
Tested 1MB buffer: OK!
|
||||||
|
Exiting @ tick 7645253019000 because target called exit()
|
193
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
Normal file
193
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
Normal file
|
@ -0,0 +1,193 @@
|
||||||
|
[root]
|
||||||
|
type=Root
|
||||||
|
children=system
|
||||||
|
dummy=0
|
||||||
|
|
||||||
|
[system]
|
||||||
|
type=System
|
||||||
|
children=cpu membus physmem
|
||||||
|
mem_mode=atomic
|
||||||
|
physmem=system.physmem
|
||||||
|
|
||||||
|
[system.cpu]
|
||||||
|
type=TimingSimpleCPU
|
||||||
|
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||||
|
clock=500
|
||||||
|
cpu_id=0
|
||||||
|
defer_registration=false
|
||||||
|
dtb=system.cpu.dtb
|
||||||
|
function_trace=false
|
||||||
|
function_trace_start=0
|
||||||
|
itb=system.cpu.itb
|
||||||
|
max_insts_all_threads=0
|
||||||
|
max_insts_any_thread=0
|
||||||
|
max_loads_all_threads=0
|
||||||
|
max_loads_any_thread=0
|
||||||
|
numThreads=1
|
||||||
|
phase=0
|
||||||
|
progress_interval=0
|
||||||
|
system=system
|
||||||
|
tracer=system.cpu.tracer
|
||||||
|
workload=system.cpu.workload
|
||||||
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.dcache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=262144
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.dcache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.dtb]
|
||||||
|
type=X86DTB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.icache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=131072
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.icache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.itb]
|
||||||
|
type=X86ITB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.l2cache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=10000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=100000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=2097152
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.toL2Bus.port[2]
|
||||||
|
mem_side=system.membus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.toL2Bus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.tracer]
|
||||||
|
type=ExeTracer
|
||||||
|
|
||||||
|
[system.cpu.workload]
|
||||||
|
type=LiveProcess
|
||||||
|
cmd=twolf smred
|
||||||
|
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
|
||||||
|
egid=100
|
||||||
|
env=
|
||||||
|
errout=cerr
|
||||||
|
euid=100
|
||||||
|
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||||
|
gid=100
|
||||||
|
input=cin
|
||||||
|
max_stack_size=67108864
|
||||||
|
output=cout
|
||||||
|
pid=100
|
||||||
|
ppid=99
|
||||||
|
simpoint=0
|
||||||
|
system=system
|
||||||
|
uid=100
|
||||||
|
|
||||||
|
[system.membus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||||
|
|
||||||
|
[system.physmem]
|
||||||
|
type=PhysicalMemory
|
||||||
|
file=
|
||||||
|
latency=30000
|
||||||
|
latency_var=0
|
||||||
|
null=false
|
||||||
|
range=0:134217727
|
||||||
|
zero=false
|
||||||
|
port=system.membus.port[0]
|
||||||
|
|
234
tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt
Normal file
234
tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,234 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 937563 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 210412 # Number of bytes of host memory used
|
||||||
|
host_seconds 233.15 # Real time elapsed on the host
|
||||||
|
host_tick_rate 1447418160 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 218595322 # Number of instructions simulated
|
||||||
|
sim_seconds 0.337470 # Number of seconds simulated
|
||||||
|
sim_ticks 337469714000 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 77163409 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 1920 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 27 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 2 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 260013903 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 4693 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 2835 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses
|
||||||
|
system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 1855 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 4732 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 674939428 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 218595322 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 77165364 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
276
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out
Normal file
276
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out
Normal file
|
@ -0,0 +1,276 @@
|
||||||
|
|
||||||
|
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||||
|
Standard Cell Placement and Global Routing Program
|
||||||
|
Authors: Carl Sechen, Bill Swartz
|
||||||
|
Yale University
|
||||||
|
|
||||||
|
|
||||||
|
NOTE: Restart file .rs2 not used
|
||||||
|
|
||||||
|
TimberWolf will perform a global route step
|
||||||
|
rowSep: 1.000000
|
||||||
|
feedThruWidth: 4
|
||||||
|
|
||||||
|
******************
|
||||||
|
BLOCK DATA
|
||||||
|
block:1 desire:85
|
||||||
|
block:2 desire:85
|
||||||
|
Total Desired Length: 170
|
||||||
|
total cell length: 168
|
||||||
|
total block length: 168
|
||||||
|
block x-span:84 block y-span:78
|
||||||
|
implicit feed thru range: -84
|
||||||
|
Using default value of bin.penalty.control:1.000000
|
||||||
|
numBins automatically set to:5
|
||||||
|
binWidth = average_cell_width + 0 sigma= 17
|
||||||
|
average_cell_width is:16
|
||||||
|
standard deviation of cell length is:23.6305
|
||||||
|
TimberWolfSC starting from the beginning
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
|
||||||
|
The number of nets with 1 pin is 4
|
||||||
|
The number of nets with 2 pin is 9
|
||||||
|
The number of nets with 3 pin is 0
|
||||||
|
The number of nets with 4 pin is 2
|
||||||
|
The number of nets with 5 pin is 0
|
||||||
|
The number of nets with 6 pin is 0
|
||||||
|
The number of nets with 7 pin is 0
|
||||||
|
The number of nets with 8 pin is 0
|
||||||
|
The number of nets with 9 pin is 0
|
||||||
|
The number of nets with 10 pin or more is 0
|
||||||
|
|
||||||
|
New Cost Function: Initial Horizontal Cost:242
|
||||||
|
New Cost Function: FEEDS:0 MISSING_ROWS:-46
|
||||||
|
|
||||||
|
bdxlen:86 bdylen:78
|
||||||
|
l:0 t:78 r:86 b:0
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
|
||||||
|
|
||||||
|
The rand generator seed was at utemp() : 1
|
||||||
|
|
||||||
|
|
||||||
|
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
|
||||||
|
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
|
||||||
|
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
|
||||||
|
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
|
||||||
|
|
||||||
|
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
|
||||||
|
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
|
||||||
|
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
|
||||||
|
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
|
||||||
|
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
|
||||||
|
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
|
||||||
|
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
|
||||||
|
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
|
||||||
|
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
|
||||||
|
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
|
||||||
|
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
|
||||||
|
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
|
||||||
|
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
|
||||||
|
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
|
||||||
|
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
|
||||||
|
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
|
||||||
|
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
|
||||||
|
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
|
||||||
|
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
|
||||||
|
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
|
||||||
|
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
|
||||||
|
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
|
||||||
|
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
|
||||||
|
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
|
||||||
|
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
|
||||||
|
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
|
||||||
|
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
|
||||||
|
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
|
||||||
|
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
|
||||||
|
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
|
||||||
|
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
|
||||||
|
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
|
||||||
|
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
|
||||||
|
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
|
||||||
|
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
|
||||||
|
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
|
||||||
|
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
|
||||||
|
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
|
||||||
|
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
|
||||||
|
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
|
||||||
|
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
|
||||||
|
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
|
||||||
|
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
|
||||||
|
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
|
||||||
|
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
|
||||||
|
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
|
||||||
|
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
|
||||||
|
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
|
||||||
|
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
|
||||||
|
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
|
||||||
|
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
|
||||||
|
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
|
||||||
|
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
|
||||||
|
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
|
||||||
|
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
|
||||||
|
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
|
||||||
|
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
|
||||||
|
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
|
||||||
|
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
|
||||||
|
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
|
||||||
|
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
|
||||||
|
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
|
||||||
|
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
|
||||||
|
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
|
||||||
|
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
|
||||||
|
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
|
||||||
|
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
|
||||||
|
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
|
||||||
|
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
|
||||||
|
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
|
||||||
|
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
|
||||||
|
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
|
||||||
|
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
|
||||||
|
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
|
||||||
|
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
|
||||||
|
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
|
||||||
|
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
|
||||||
|
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
|
||||||
|
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
|
||||||
|
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
|
||||||
|
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
|
||||||
|
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
|
||||||
|
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
|
||||||
|
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
|
||||||
|
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
|
||||||
|
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
|
||||||
|
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
|
||||||
|
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
|
||||||
|
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
|
||||||
|
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
|
||||||
|
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
|
||||||
|
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
|
||||||
|
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
|
||||||
|
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
|
||||||
|
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
|
||||||
|
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
|
||||||
|
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
|
||||||
|
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
|
||||||
|
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
|
||||||
|
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
|
||||||
|
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
|
||||||
|
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
|
||||||
|
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
|
||||||
|
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
|
||||||
|
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
|
||||||
|
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
|
||||||
|
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
|
||||||
|
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
|
||||||
|
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
|
||||||
|
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
|
||||||
|
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
|
||||||
|
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
|
||||||
|
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
|
||||||
|
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
|
||||||
|
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
|
||||||
|
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
|
||||||
|
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
|
||||||
|
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
|
||||||
|
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
|
||||||
|
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
|
||||||
|
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
|
||||||
|
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
|
||||||
|
|
||||||
|
Initial Wiring Cost: 645 Final Wiring Cost: 732
|
||||||
|
############## Percent Wire Cost Reduction: -13
|
||||||
|
|
||||||
|
|
||||||
|
Initial Wire Length: 645 Final Wire Length: 732
|
||||||
|
************** Percent Wire Length Reduction: -13
|
||||||
|
|
||||||
|
|
||||||
|
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
|
||||||
|
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
|
||||||
|
|
||||||
|
|
||||||
|
Initial Vert. Wire: 429 Final Vert. Wire: 585
|
||||||
|
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
|
||||||
|
|
||||||
|
Before Feeds are Added:
|
||||||
|
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||||
|
1 82 -20
|
||||||
|
2 86 -16
|
||||||
|
|
||||||
|
LONGEST Block is:2 Its length is:86
|
||||||
|
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||||
|
1 86 -16
|
||||||
|
2 86 -16
|
||||||
|
|
||||||
|
LONGEST Block is:1 Its length is:86
|
||||||
|
Added: 1 feed-through cells
|
||||||
|
|
||||||
|
Removed the cell overlaps --- Will do neighbor interchanges only now
|
||||||
|
|
||||||
|
TOTAL INTERCONNECT LENGTH: 994
|
||||||
|
OVERLAP PENALTY: 0
|
||||||
|
|
||||||
|
initialRowControl: 1.650
|
||||||
|
finalRowControl: 0.300
|
||||||
|
iter T Wire accept
|
||||||
|
122 0.001 976 16%
|
||||||
|
123 0.001 971 0%
|
||||||
|
124 0.001 971 0%
|
||||||
|
Total Feed-Alignment Movement (Pass 1): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 2): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 3): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 4): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 5): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 6): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 7): 0
|
||||||
|
Total Feed-Alignment Movement (Pass 8): 0
|
||||||
|
|
||||||
|
The rand generator seed was at globroute() : 987654321
|
||||||
|
|
||||||
|
|
||||||
|
Total Number of Net Segments: 9
|
||||||
|
Number of Switchable Net Segments: 0
|
||||||
|
|
||||||
|
Number of channels: 3
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
|
||||||
|
|
||||||
|
|
||||||
|
no. of accepted flips: 0
|
||||||
|
no. of attempted flips: 0
|
||||||
|
THIS IS THE NUMBER OF TRACKS: 5
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
FINAL NUMBER OF ROUTING TRACKS: 5
|
||||||
|
|
||||||
|
MAX OF CHANNEL: 1 is: 0
|
||||||
|
MAX OF CHANNEL: 2 is: 4
|
||||||
|
MAX OF CHANNEL: 3 is: 1
|
||||||
|
FINAL TOTAL INTERCONNECT LENGTH: 978
|
||||||
|
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
|
||||||
|
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
|
||||||
|
|
||||||
|
|
||||||
|
cost_scale_factor:3.90616
|
||||||
|
|
||||||
|
Number of Feed Thrus: 0
|
||||||
|
Number of Implicit Feed Thrus: 0
|
||||||
|
|
||||||
|
Statistics:
|
||||||
|
Number of Standard Cells: 10
|
||||||
|
Number of Pads: 0
|
||||||
|
Number of Nets: 15
|
||||||
|
Number of Pins: 46
|
||||||
|
Usage statistics not available
|
17
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin
Normal file
17
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin
Normal file
|
@ -0,0 +1,17 @@
|
||||||
|
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
|
||||||
|
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
|
||||||
|
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
|
||||||
|
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
|
||||||
|
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
|
||||||
|
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
|
||||||
|
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
|
||||||
|
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
|
||||||
|
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
|
||||||
|
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
|
||||||
|
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
|
||||||
|
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
|
||||||
|
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
|
||||||
|
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
|
||||||
|
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
|
||||||
|
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
|
||||||
|
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
|
11
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1
Normal file
11
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1
Normal file
|
@ -0,0 +1,11 @@
|
||||||
|
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
|
||||||
|
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
|
||||||
|
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
|
||||||
|
ACOUNT_1 14 0 18 26 2 1
|
||||||
|
twfeed1 18 0 22 26 0 1
|
||||||
|
$COUNT_1/$FJK3_1 22 0 86 26 0 1
|
||||||
|
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
|
||||||
|
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
|
||||||
|
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
|
||||||
|
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
|
||||||
|
$COUNT_1/$FJK3_2 22 52 86 78 0 2
|
|
@ -0,0 +1,2 @@
|
||||||
|
1 0 0 86 26 0 0
|
||||||
|
2 0 52 86 78 0 0
|
18
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav
Normal file
18
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav
Normal file
|
@ -0,0 +1,18 @@
|
||||||
|
0.009592
|
||||||
|
121
|
||||||
|
0
|
||||||
|
1
|
||||||
|
0.000000
|
||||||
|
0.500000
|
||||||
|
3.906156
|
||||||
|
1
|
||||||
|
1 1 2 37 13
|
||||||
|
2 2 0 34 65
|
||||||
|
3 2 2 63 65
|
||||||
|
4 1 0 59 13
|
||||||
|
5 1 2 32 13
|
||||||
|
6 2 0 23 65
|
||||||
|
7 1 2 12 13
|
||||||
|
8 2 0 6 65
|
||||||
|
9 1 0 70 13
|
||||||
|
10 2 0 70 65
|
19
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2
Normal file
19
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2
Normal file
|
@ -0,0 +1,19 @@
|
||||||
|
0.001000
|
||||||
|
123
|
||||||
|
0
|
||||||
|
2
|
||||||
|
0.000000
|
||||||
|
0.500000
|
||||||
|
3.906156
|
||||||
|
1
|
||||||
|
1 1 2 16 13
|
||||||
|
2 2 2 19 65
|
||||||
|
3 2 2 14 65
|
||||||
|
4 1 0 11 13
|
||||||
|
5 1 2 6 13
|
||||||
|
6 2 0 3 65
|
||||||
|
7 1 0 2 13
|
||||||
|
8 2 2 9 65
|
||||||
|
9 1 0 50 13
|
||||||
|
10 2 0 54 65
|
||||||
|
11 1 0 84 13
|
29
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf
Normal file
29
tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf
Normal file
|
@ -0,0 +1,29 @@
|
||||||
|
net 1
|
||||||
|
segment channel 2
|
||||||
|
pin1 1 pin2 7 0 0
|
||||||
|
net 2
|
||||||
|
segment channel 3
|
||||||
|
pin1 41 pin2 42 0 0
|
||||||
|
segment channel 2
|
||||||
|
pin1 12 pin2 3 0 0
|
||||||
|
net 3
|
||||||
|
segment channel 2
|
||||||
|
pin1 35 pin2 36 0 0
|
||||||
|
segment channel 2
|
||||||
|
pin1 19 pin2 35 0 0
|
||||||
|
net 4
|
||||||
|
segment channel 2
|
||||||
|
pin1 5 pin2 38 0 0
|
||||||
|
net 5
|
||||||
|
net 7
|
||||||
|
segment channel 2
|
||||||
|
pin1 14 pin2 43 0 0
|
||||||
|
net 8
|
||||||
|
segment channel 2
|
||||||
|
pin1 23 pin2 17 0 0
|
||||||
|
net 9
|
||||||
|
net 11
|
||||||
|
segment channel 2
|
||||||
|
pin1 25 pin2 31 0 0
|
||||||
|
net 14
|
||||||
|
net 15
|
6
tests/long/70.twolf/ref/x86/linux/simple-timing/stderr
Executable file
6
tests/long/70.twolf/ref/x86/linux/simple-timing/stderr
Executable file
|
@ -0,0 +1,6 @@
|
||||||
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
|
warn: instruction 'fnstcw_Mw' unimplemented
|
||||||
|
warn: instruction 'fldcw_Mw' unimplemented
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: Increasing stack size by one page.
|
||||||
|
warn: be nice to actually delete the event here
|
31
tests/long/70.twolf/ref/x86/linux/simple-timing/stdout
Executable file
31
tests/long/70.twolf/ref/x86/linux/simple-timing/stdout
Executable file
|
@ -0,0 +1,31 @@
|
||||||
|
M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2008
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Nov 9 2008 18:23:31
|
||||||
|
M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e
|
||||||
|
M5 commit date Sat Nov 08 21:06:07 2008 -0800
|
||||||
|
M5 started Nov 9 2008 18:29:22
|
||||||
|
M5 executing on tater
|
||||||
|
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing
|
||||||
|
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
|
||||||
|
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
|
||||||
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||||
|
Standard Cell Placement and Global Routing Program
|
||||||
|
Authors: Carl Sechen, Bill Swartz
|
||||||
|
Yale University
|
||||||
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
||||||
|
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
|
||||||
|
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
|
||||||
|
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
|
||||||
|
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
|
||||||
|
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||||
|
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||||
|
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||||
|
122 123 124 Exiting @ tick 337469714000 because target called exit()
|
193
tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
Normal file
193
tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
Normal file
|
@ -0,0 +1,193 @@
|
||||||
|
[root]
|
||||||
|
type=Root
|
||||||
|
children=system
|
||||||
|
dummy=0
|
||||||
|
|
||||||
|
[system]
|
||||||
|
type=System
|
||||||
|
children=cpu membus physmem
|
||||||
|
mem_mode=atomic
|
||||||
|
physmem=system.physmem
|
||||||
|
|
||||||
|
[system.cpu]
|
||||||
|
type=TimingSimpleCPU
|
||||||
|
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||||
|
clock=500
|
||||||
|
cpu_id=0
|
||||||
|
defer_registration=false
|
||||||
|
dtb=system.cpu.dtb
|
||||||
|
function_trace=false
|
||||||
|
function_trace_start=0
|
||||||
|
itb=system.cpu.itb
|
||||||
|
max_insts_all_threads=0
|
||||||
|
max_insts_any_thread=0
|
||||||
|
max_loads_all_threads=0
|
||||||
|
max_loads_any_thread=0
|
||||||
|
numThreads=1
|
||||||
|
phase=0
|
||||||
|
progress_interval=0
|
||||||
|
system=system
|
||||||
|
tracer=system.cpu.tracer
|
||||||
|
workload=system.cpu.workload
|
||||||
|
dcache_port=system.cpu.dcache.cpu_side
|
||||||
|
icache_port=system.cpu.icache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.dcache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=262144
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.dcache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.dtb]
|
||||||
|
type=X86DTB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.icache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=1000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=10000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=131072
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.icache_port
|
||||||
|
mem_side=system.cpu.toL2Bus.port[0]
|
||||||
|
|
||||||
|
[system.cpu.itb]
|
||||||
|
type=X86ITB
|
||||||
|
size=64
|
||||||
|
|
||||||
|
[system.cpu.l2cache]
|
||||||
|
type=BaseCache
|
||||||
|
addr_range=0:18446744073709551615
|
||||||
|
assoc=2
|
||||||
|
block_size=64
|
||||||
|
cpu_side_filter_ranges=
|
||||||
|
hash_delay=1
|
||||||
|
latency=10000
|
||||||
|
max_miss_count=0
|
||||||
|
mem_side_filter_ranges=
|
||||||
|
mshrs=10
|
||||||
|
prefetch_access=false
|
||||||
|
prefetch_cache_check_push=true
|
||||||
|
prefetch_data_accesses_only=false
|
||||||
|
prefetch_degree=1
|
||||||
|
prefetch_latency=100000
|
||||||
|
prefetch_miss=false
|
||||||
|
prefetch_past_page=false
|
||||||
|
prefetch_policy=none
|
||||||
|
prefetch_serial_squash=false
|
||||||
|
prefetch_use_cpu_id=true
|
||||||
|
prefetcher_size=100
|
||||||
|
prioritizeRequests=false
|
||||||
|
repl=Null
|
||||||
|
size=2097152
|
||||||
|
subblock_size=0
|
||||||
|
tgts_per_mshr=5
|
||||||
|
trace_addr=0
|
||||||
|
two_queue=false
|
||||||
|
write_buffers=8
|
||||||
|
cpu_side=system.cpu.toL2Bus.port[2]
|
||||||
|
mem_side=system.membus.port[1]
|
||||||
|
|
||||||
|
[system.cpu.toL2Bus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||||
|
|
||||||
|
[system.cpu.tracer]
|
||||||
|
type=ExeTracer
|
||||||
|
|
||||||
|
[system.cpu.workload]
|
||||||
|
type=LiveProcess
|
||||||
|
cmd=hello
|
||||||
|
cwd=
|
||||||
|
egid=100
|
||||||
|
env=
|
||||||
|
errout=cerr
|
||||||
|
euid=100
|
||||||
|
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||||
|
gid=100
|
||||||
|
input=cin
|
||||||
|
max_stack_size=67108864
|
||||||
|
output=cout
|
||||||
|
pid=100
|
||||||
|
ppid=99
|
||||||
|
simpoint=0
|
||||||
|
system=system
|
||||||
|
uid=100
|
||||||
|
|
||||||
|
[system.membus]
|
||||||
|
type=Bus
|
||||||
|
block_size=64
|
||||||
|
bus_id=0
|
||||||
|
clock=1000
|
||||||
|
header_cycles=1
|
||||||
|
responder_set=false
|
||||||
|
width=64
|
||||||
|
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||||
|
|
||||||
|
[system.physmem]
|
||||||
|
type=PhysicalMemory
|
||||||
|
file=
|
||||||
|
latency=30000
|
||||||
|
latency_var=0
|
||||||
|
null=false
|
||||||
|
range=0:134217727
|
||||||
|
zero=false
|
||||||
|
port=system.membus.port[0]
|
||||||
|
|
232
tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt
Normal file
232
tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,232 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 106773 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 197592 # Number of bytes of host memory used
|
||||||
|
host_seconds 0.09 # Real time elapsed on the host
|
||||||
|
host_tick_rate 379942758 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 9493 # Number of instructions simulated
|
||||||
|
sim_seconds 0.000034 # Number of seconds simulated
|
||||||
|
sim_ticks 33851000 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 1835 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 152 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 10779 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 228 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 0 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 10779 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
|
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 360 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 67702 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 9493 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 2003 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
4
tests/quick/00.hello/ref/x86/linux/simple-timing/stderr
Executable file
4
tests/quick/00.hello/ref/x86/linux/simple-timing/stderr
Executable file
|
@ -0,0 +1,4 @@
|
||||||
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
|
warn: instruction 'fnstcw_Mw' unimplemented
|
||||||
|
warn: instruction 'fldcw_Mw' unimplemented
|
||||||
|
warn: be nice to actually delete the event here
|
17
tests/quick/00.hello/ref/x86/linux/simple-timing/stdout
Executable file
17
tests/quick/00.hello/ref/x86/linux/simple-timing/stdout
Executable file
|
@ -0,0 +1,17 @@
|
||||||
|
M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2008
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Nov 7 2008 03:21:37
|
||||||
|
M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
|
||||||
|
M5 commit date Thu Nov 06 23:13:50 2008 -0800
|
||||||
|
M5 started Nov 8 2008 00:19:20
|
||||||
|
M5 executing on tater
|
||||||
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing
|
||||||
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
Hello world!
|
||||||
|
Exiting @ tick 33851000 because target called exit()
|
Loading…
Reference in a new issue