stats: Bump the vortex stats to match latest behaviour
This patch bumps the stats for the failing vortex o3 regression.
This commit is contained in:
Andreas Hansson
parent
53b713fb4b
commit
c704b7be16
1 changed files with 223 additions and 223 deletions
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@ -4,42 +4,42 @@ sim_seconds 0.025535 # Nu
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sim_ticks 25534556000 # Number of ticks simulated
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final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 42425 # Simulator instruction rate (inst/s)
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host_op_rate 60207 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 15277801 # Simulator tick rate (ticks/s)
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host_mem_usage 296924 # Number of bytes of host memory used
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host_seconds 1671.35 # Real time elapsed on the host
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host_inst_rate 124211 # Simulator instruction rate (inst/s)
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host_op_rate 176271 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 44729688 # Simulator tick rate (ticks/s)
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host_mem_usage 254184 # Number of bytes of host memory used
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host_seconds 570.86 # Real time elapsed on the host
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sim_insts 70907629 # Number of instructions simulated
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sim_ops 100626876 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory
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system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7943488 # Number of bytes read from this memory
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system.physmem.bytes_read::total 8241024 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory
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system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 124117 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 128766 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 311085260 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 322737548 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 311087767 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 322740055 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 311085260 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 533137917 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 128766 # Total number of read requests seen
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system.physmem.bw_total::cpu.data 311087767 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 533140424 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 128767 # Total number of read requests seen
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system.physmem.writeReqs 83945 # Total number of write requests seen
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system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 8240960 # Total number of bytes read from memory
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system.physmem.cpureqs 213037 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 8241024 # Total number of bytes read from memory
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system.physmem.bytesWritten 5372480 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 8240960 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedRd 8241024 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed
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@ -58,7 +58,7 @@ system.physmem.perBankRdReqs::11 8125 # Tr
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system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 7948 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 7949 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis
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@ -84,7 +84,7 @@ system.physmem.readPktSize::2 0 # Ca
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 128766 # Categorize read packet sizes
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system.physmem.readPktSize::6 128767 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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@ -92,7 +92,7 @@ system.physmem.writePktSize::3 0 # Ca
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 83945 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 70151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::0 70152 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
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@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 3209266500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 5253345250 # Sum of mem lat for all requests
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system.physmem.totBusLat 643820000 # Total cycles spent in databus access
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system.physmem.totBankLat 1400258750 # Total cycles spent in bank access
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system.physmem.avgQLat 24923.63 # Average queueing delay per request
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system.physmem.avgBankLat 10874.61 # Average bank access latency per request
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system.physmem.totQLat 3209361000 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 5253486000 # Sum of mem lat for all requests
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system.physmem.totBusLat 643825000 # Total cycles spent in databus access
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system.physmem.totBankLat 1400300000 # Total cycles spent in bank access
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system.physmem.avgQLat 24924.17 # Average queueing delay per request
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system.physmem.avgBankLat 10874.85 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 40798.25 # Average memory access latency
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system.physmem.avgMemAccLat 40799.02 # Average memory access latency
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system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s
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@ -176,7 +176,7 @@ system.physmem.readRowHits 116738 # Nu
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system.physmem.writeRowHits 52892 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes
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system.physmem.avgGap 120043.34 # Average gap between requests
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system.physmem.avgGap 120042.78 # Average gap between requests
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system.cpu.branchPred.lookups 16612549 # Number of BP lookups
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system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect
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@ -232,13 +232,13 @@ system.cpu.workload.num_syscalls 1946 # Nu
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system.cpu.numCycles 51069113 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 12514698 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.icacheStallCycles 12514697 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 10532726 # Number of cycles fetch has spent blocked
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system.cpu.fetch.BlockedCycles 10532727 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
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@ -263,8 +263,8 @@ system.cpu.fetch.rateDist::max_value 8 # Nu
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system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 14598305 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 8880724 # Number of cycles decode is blocked
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system.cpu.decode.IdleCycles 14598304 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 8880725 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing
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@ -273,9 +273,9 @@ system.cpu.decode.BranchMispred 105063 # Nu
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system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 16304725 # Number of cycles rename is idle
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system.cpu.rename.IdleCycles 16304724 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 873067 # count of cycles rename stalled for serializing inst
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system.cpu.rename.serializeStallCycles 873068 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename
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@ -298,24 +298,24 @@ system.cpu.memDep0.conflictingLoads 3871274 # Nu
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system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 107205683 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 272681 # Number of squashed instructions issued
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system.cpu.iq.iqInstsIssued 107205680 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 272682 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 25689486 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedOperandsExamined 25689497 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 10727081 23.35% 23.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 8071190 17.57% 40.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 7423915 16.16% 57.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 10727082 23.35% 23.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 8071187 17.57% 40.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 7423916 16.16% 57.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 5405073 11.76% 84.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 3914653 8.52% 92.85% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1842463 4.01% 96.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 872331 1.90% 98.76% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 570973 1.24% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 5405071 11.76% 84.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 3914661 8.52% 92.85% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1842461 4.01% 96.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 872329 1.90% 98.76% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 570972 1.24% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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@ -350,12 +350,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # at
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1365116 55.14% 59.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 998484 40.33% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1365113 55.14% 59.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 998480 40.33% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 56613299 52.81% 52.81% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 56613296 52.81% 52.81% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued
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@ -388,17 +388,17 @@ system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Ty
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system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 107205683 # Type of FU issued
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system.cpu.iq.FU_type_0::total 107205680 # Type of FU issued
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system.cpu.iq.rate 2.099227 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2475632 # FU busy when requested
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system.cpu.iq.fu_busy_cnt 2475625 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 263108179 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_reads 263108167 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 105531184 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.int_inst_queue_wakeup_accesses 105531182 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 109681022 # Number of integer alu accesses
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system.cpu.iq.int_alu_accesses 109681012 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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@ -425,19 +425,19 @@ system.cpu.iew.memOrderViolationEvents 30581 # Nu
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system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecutedInsts 106181677 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 28584422 # Number of load instructions executed
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system.cpu.iew.iewExecutedInsts 106181674 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 28584421 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.exec_nop 9768 # number of nop insts executed
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system.cpu.iew.exec_refs 49919694 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 49919693 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 14596236 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 21335272 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.079176 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 105750985 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 105531355 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_sent 105750982 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 105531353 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 53247115 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 103478593 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 103478594 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back
|
||||
|
|
@ -450,14 +450,14 @@ system.cpu.commit.committed_per_cycle::mean 2.270288 #
|
|||
system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 11622337 26.22% 60.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3461272 7.81% 68.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2876318 6.49% 74.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1875937 4.23% 79.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1955484 4.41% 83.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 11622339 26.22% 60.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3461273 7.81% 68.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2876315 6.49% 74.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1875935 4.23% 79.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1955485 4.41% 83.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6014208 13.57% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6014209 13.57% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
|
|
@ -472,9 +472,9 @@ system.cpu.commit.branches 13741485 # Nu
|
|||
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 6014208 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 6014209 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 149798719 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 149798718 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 224657070 # The number of ROB writes
|
||||
system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
|
|
@ -485,8 +485,8 @@ system.cpu.cpi 0.720220 # CP
|
|||
system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 511419514 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 103305187 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 511419502 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 103305182 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 846 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 738 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads
|
||||
|
|
@ -512,12 +512,12 @@ system.cpu.icache.demand_misses::cpu.inst 34736 # n
|
|||
system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 34736 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 739851499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 739851499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 739851499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 739851499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 739851499 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 739851499 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 739850999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 739850999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 739850999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 739850999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 739850999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 739850999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 11663165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 11663165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 11663165 # number of demand (read+write) accesses
|
||||
|
|
@ -530,12 +530,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.002978
|
|||
system.cpu.icache.demand_miss_rate::total 0.002978 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.002978 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.002978 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.271620 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21299.271620 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.271620 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21299.271620 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.271620 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21299.271620 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.257226 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21299.257226 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21299.257226 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21299.257226 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 1371 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked
|
||||
|
|
@ -556,38 +556,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 30960
|
|||
system.cpu.icache.demand_mshr_misses::total 30960 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 30960 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 30960 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 598675999 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 598675999 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 598675999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 598675999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 598675999 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 598675999 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 598675499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 598675499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 598675499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 598675499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 598675499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 598675499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002655 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.002655 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.002655 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.080071 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.080071 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.080071 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.080071 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.080071 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.080071 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.063921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.063921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 95631 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30087.682209 # Cycle average of tags in use
|
||||
system.cpu.l2cache.replacements 95632 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30087.760177 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 88021 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 126746 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.694468 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 126747 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.694462 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26926.189378 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26926.191457 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1374.986838 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1786.505993 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1786.581881 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.821722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.041961 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.054520 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.918203 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.054522 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.918206 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 25771 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33436 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 59207 # number of ReadReq hits
|
||||
|
|
@ -604,34 +604,34 @@ system.cpu.l2cache.overall_hits::cpu.inst 25771 # n
|
|||
system.cpu.l2cache.overall_hits::cpu.data 38219 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 63990 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 21926 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 26590 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 21927 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 26591 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 324 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 324 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102251 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102251 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 124177 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 128841 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 128842 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 4664 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124177 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 128841 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 309051000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1483283000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1792334000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 128842 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 309050500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1483446500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1792497000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6646928500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6646928500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 309051000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8130211500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8439262500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 309051000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8130211500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8439262500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6646929000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6646929000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 309050500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8130375500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8439426000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 309050500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8130375500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8439426000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55362 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 85797 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55363 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 85798 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 129075 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 129075 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 342 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -639,37 +639,37 @@ system.cpu.l2cache.UpgradeReq_accesses::total 342
|
|||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 30435 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 162396 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 192831 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 162397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 192832 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 30435 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 162396 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 192831 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 162397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 192832 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153245 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.396048 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.309918 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.396059 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.309926 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955313 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955313 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153245 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.764656 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.668155 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.764657 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.668157 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153245 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.764656 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.668155 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66263.078902 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67649.502873 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67406.318165 # average ReadReq miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.764657 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.668157 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66262.971698 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67653.874219 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67409.913129 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 70.987654 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 70.987654 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65005.999941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65005.999941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66263.078902 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65472.764683 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65501.373786 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66263.078902 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65472.764683 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65501.373786 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65006.004831 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.004831 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66262.971698 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65473.558118 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65502.134397 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66262.971698 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65473.558118 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65502.134397 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -690,99 +690,99 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 15
|
|||
system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4649 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21867 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 26516 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21868 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 26517 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102251 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102251 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4649 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 128767 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 124119 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 128768 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4649 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 128767 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 124119 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 128768 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250601778 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209164905 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1459766683 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209315656 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1459917434 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3249822 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3249822 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5391078264 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5391078264 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250601778 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6600243169 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6850844947 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6600393920 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6850995698 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250601778 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6600243169 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6850844947 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6600393920 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6850995698 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394993 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309063 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955313 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955313 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764292 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.667771 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764294 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.667773 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764292 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.667771 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764294 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.667773 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53904.447838 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55296.332602 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55052.296085 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55300.697640 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55055.905042 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.314815 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.314815 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52723.966162 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52723.966162 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53177.163417 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.421273 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53177.949548 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53204.178818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53177.163417 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.421273 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53177.949548 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53204.178818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 158299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4072.272113 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 44344927 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 162395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 273.068303 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.replacements 158300 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4072.274733 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 44344926 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 162396 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 273.066615 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 284501000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4072.272113 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994207 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994207 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 26045311 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 26045311 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4072.274733 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994208 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994208 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 26045310 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 26045310 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18267055 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 18267055 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15985 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15985 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 44312366 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44312366 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44312366 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44312366 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 124674 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 124674 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 44312365 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44312365 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44312365 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44312365 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 124675 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 124675 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1582846 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1582846 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1707520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1707520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1707520 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1707520 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4256897000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4256897000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390757481 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 98390757481 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 1707521 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1707521 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1707521 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1707521 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4257063500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4257063500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390759981 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 98390759981 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 102647654481 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 102647654481 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 102647654481 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 102647654481 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 102647823481 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 102647823481 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 102647823481 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 102647823481 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -805,16 +805,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037104
|
|||
system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34144.224137 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34144.224137 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.663439 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.663439 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34145.285743 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34145.285743 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.665018 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.665018 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.052521 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60115.052521 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.052521 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60115.052521 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60115.116289 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60115.116289 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked
|
||||
|
|
@ -835,22 +835,22 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 1544782
|
|||
system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55396 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 55396 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55397 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 55397 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 162738 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 162738 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 162738 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 162738 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809216990 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809216990 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687607990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8687607990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687607990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8687607990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 162739 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 162739 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 162739 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 162739 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878555500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878555500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809217490 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809217490 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687772990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8687772990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687772990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8687772990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -859,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33908.422991 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33908.422991 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.787781 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.787781 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33910.780367 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33910.780367 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.792439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.792439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue