make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
This commit is contained in:
parent
f4bceb9760
commit
c55a467a06
29 changed files with 84 additions and 110 deletions
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@ -87,7 +87,7 @@ handleLockedWrite(XC *xc, Request *req)
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if (stCondFailures % 100000 == 0) {
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if (stCondFailures % 100000 == 0) {
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warn("cpu %d: %d consecutive "
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warn("cpu %d: %d consecutive "
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"store conditional failures\n",
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"store conditional failures\n",
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xc->readCpuId(), stCondFailures);
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xc->cpuId(), stCondFailures);
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}
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}
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// store conditional failed already, so don't issue it to mem
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// store conditional failed already, so don't issue it to mem
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@ -85,7 +85,7 @@ handleLockedWrite(XC *xc, Request *req)
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if (stCondFailures % 10 == 0) {
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if (stCondFailures % 10 == 0) {
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warn("%i: cpu %d: %d consecutive "
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warn("%i: cpu %d: %d consecutive "
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"store conditional failures\n",
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"store conditional failures\n",
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curTick, xc->readCpuId(), stCondFailures);
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curTick, xc->cpuId(), stCondFailures);
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}
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}
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if (stCondFailures == 5000) {
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if (stCondFailures == 5000) {
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@ -257,11 +257,11 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
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temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
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temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
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// Check that the CPU array is fully populated
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// Check that the CPU array is fully populated
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// (by calling getNumCPus())
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// (by calling getNumCPus())
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assert(sys->getNumCPUs() > tc->readCpuId());
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assert(sys->getNumCPUs() > tc->cpuId());
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temp |= tc->readCpuId() << STS::shft_id;
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temp |= tc->cpuId() << STS::shft_id;
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for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
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for (x = tc->cpuId() & ~3; x < sys->threadContexts.size(); x++) {
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switch (sys->threadContexts[x]->status()) {
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switch (sys->threadContexts[x]->status()) {
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case ThreadContext::Active:
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case ThreadContext::Active:
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temp |= STS::st_run << (STS::shft_fsm0 -
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temp |= STS::st_run << (STS::shft_fsm0 -
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@ -654,7 +654,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
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*/
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*/
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// Force the access to be uncacheable.
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// Force the access to be uncacheable.
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req->setFlags(req->getFlags() | UNCACHEABLE);
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req->setFlags(req->getFlags() | UNCACHEABLE);
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req->setPaddr(x86LocalAPICAddress(tc->readCpuId(), paddr - baseAddr));
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req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
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}
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}
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#endif
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#endif
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return NoFault;
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return NoFault;
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@ -63,7 +63,7 @@ class BaseCPU(MemObject):
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abstract = True
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abstract = True
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system = Param.System(Parent.any, "system object")
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int("CPU identifier")
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cpu_id = Param.Int(-1, "CPU identifier")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace = Param.Bool(False, "Enable function trace")
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@ -94,21 +94,29 @@ CPUProgressEvent::description() const
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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BaseCPU::BaseCPU(Params *p)
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BaseCPU::BaseCPU(Params *p)
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: MemObject(p), clock(p->clock), instCnt(0), interrupts(p->interrupts),
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: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
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interrupts(p->interrupts),
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number_of_threads(p->numThreads), system(p->system),
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number_of_threads(p->numThreads), system(p->system),
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phase(p->phase)
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phase(p->phase)
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#else
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#else
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BaseCPU::BaseCPU(Params *p)
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BaseCPU::BaseCPU(Params *p)
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: MemObject(p), clock(p->clock),
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: MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
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number_of_threads(p->numThreads), system(p->system),
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number_of_threads(p->numThreads), system(p->system),
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phase(p->phase)
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phase(p->phase)
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#endif
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#endif
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{
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{
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// currentTick = curTick;
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// currentTick = curTick;
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// if Python did not provide a valid ID, do it here
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if (_cpuId == -1 ) {
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_cpuId = cpuList.size();
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}
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// add self to global list of CPUs
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// add self to global list of CPUs
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cpuList.push_back(this);
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cpuList.push_back(this);
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DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
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if (number_of_threads > maxThreadsPerCPU)
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if (number_of_threads > maxThreadsPerCPU)
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maxThreadsPerCPU = number_of_threads;
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maxThreadsPerCPU = number_of_threads;
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@ -278,13 +286,9 @@ BaseCPU::registerThreadContexts()
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ThreadContext *tc = threadContexts[i];
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ThreadContext *tc = threadContexts[i];
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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int id = params()->cpu_id;
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system->registerThreadContext(tc);
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if (id != -1)
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id += i;
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tc->setCpuId(system->registerThreadContext(tc, id));
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#else
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#else
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tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
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tc->getProcessPtr()->registerThreadContext(tc);
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#endif
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#endif
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}
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}
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}
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}
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@ -315,6 +319,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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{
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{
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assert(threadContexts.size() == oldCPU->threadContexts.size());
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assert(threadContexts.size() == oldCPU->threadContexts.size());
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_cpuId = oldCPU->cpuId();
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for (int i = 0; i < threadContexts.size(); ++i) {
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *newTC = threadContexts[i];
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ThreadContext *newTC = threadContexts[i];
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ThreadContext *oldTC = oldCPU->threadContexts[i];
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ThreadContext *oldTC = oldCPU->threadContexts[i];
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@ -323,12 +329,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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CpuEvent::replaceThreadContext(oldTC, newTC);
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CpuEvent::replaceThreadContext(oldTC, newTC);
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assert(newTC->readCpuId() == oldTC->readCpuId());
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assert(newTC->cpuId() == oldTC->cpuId());
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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system->replaceThreadContext(newTC, newTC->readCpuId());
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system->replaceThreadContext(newTC, newTC->cpuId());
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#else
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#else
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assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
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assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
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newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
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newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->cpuId());
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#endif
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#endif
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if (DTRACE(Context))
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if (DTRACE(Context))
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@ -80,8 +80,16 @@ class BaseCPU : public MemObject
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Tick clock;
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Tick clock;
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// @todo remove me after debugging with legion done
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// @todo remove me after debugging with legion done
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Tick instCnt;
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Tick instCnt;
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// every cpu has an id, put it in the base cpu
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// Set at initialization, only time a cpuId might change is during a
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// takeover (which should be done from within the BaseCPU anyway,
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// therefore no setCpuId() method is provided
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int _cpuId;
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public:
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public:
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/** Reads this CPU's ID. */
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int cpuId() { return _cpuId; }
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// Tick currentTick;
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// Tick currentTick;
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick ticks(int numCycles) const { return clock * numCycles; }
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inline Tick ticks(int numCycles) const { return clock * numCycles; }
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@ -412,7 +412,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
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void dump(std::string &outstring);
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void dump(std::string &outstring);
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/** Read this CPU's ID. */
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/** Read this CPU's ID. */
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int readCpuId() { return cpu->readCpuId(); }
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int cpuId() { return cpu->cpuId(); }
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/** Returns the fault type. */
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/** Returns the fault type. */
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Fault getFault() { return fault; }
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Fault getFault() { return fault; }
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reqMade = true;
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reqMade = true;
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Request *req = new Request();
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Request *req = new Request();
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req->setVirt(asid, vaddr, size, flags, PC);
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req->setVirt(asid, vaddr, size, flags, PC);
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req->setThreadContext(thread->readCpuId(), threadNumber);
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req->setThreadContext(thread->cpuId(), threadNumber);
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fault = cpu->translateDataReadReq(req, thread);
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fault = cpu->translateDataReadReq(req, thread);
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@ -887,7 +887,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
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reqMade = true;
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reqMade = true;
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Request *req = new Request();
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Request *req = new Request();
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req->setVirt(asid, addr, sizeof(T), flags, this->PC);
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req->setVirt(asid, addr, sizeof(T), flags, this->PC);
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req->setThreadContext(thread->readCpuId(), threadNumber);
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req->setThreadContext(thread->cpuId(), threadNumber);
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fault = cpu->translateDataReadReq(req, thread);
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fault = cpu->translateDataReadReq(req, thread);
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@ -942,7 +942,7 @@ BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
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reqMade = true;
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reqMade = true;
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Request *req = new Request();
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Request *req = new Request();
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req->setVirt(asid, vaddr, size, flags, PC);
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req->setVirt(asid, vaddr, size, flags, PC);
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req->setThreadContext(thread->readCpuId(), threadNumber);
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req->setThreadContext(thread->cpuId(), threadNumber);
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fault = cpu->translateDataWriteReq(req, thread);
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fault = cpu->translateDataWriteReq(req, thread);
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@ -966,7 +966,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
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reqMade = true;
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reqMade = true;
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Request *req = new Request();
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Request *req = new Request();
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req->setVirt(asid, addr, sizeof(T), flags, this->PC);
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req->setVirt(asid, addr, sizeof(T), flags, this->PC);
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req->setThreadContext(thread->readCpuId(), threadNumber);
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req->setThreadContext(thread->cpuId(), threadNumber);
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fault = cpu->translateDataWriteReq(req, thread);
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fault = cpu->translateDataWriteReq(req, thread);
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@ -152,7 +152,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
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memReq = new Request(inst->threadNumber, fetch_PC,
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memReq = new Request(inst->threadNumber, fetch_PC,
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sizeof(uint32_t),
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sizeof(uint32_t),
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IFETCH_FLAGS(thread->readPC()),
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IFETCH_FLAGS(thread->readPC()),
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fetch_PC, thread->readCpuId(), inst->threadNumber);
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fetch_PC, thread->cpuId(), inst->threadNumber);
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bool succeeded = translateInstReq(memReq);
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bool succeeded = translateInstReq(memReq);
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@ -82,7 +82,7 @@ class CheckerThreadContext : public ThreadContext
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checkerTC->setCpuId(id);
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checkerTC->setCpuId(id);
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}
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}
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int readCpuId() { return actualTC->readCpuId(); }
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int cpuId() { return actualTC->cpuId(); }
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TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
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TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
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@ -62,7 +62,7 @@ class BaseCPUParams;
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using namespace TheISA;
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using namespace TheISA;
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BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
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BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
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: BaseCPU(params), cpuId(0)
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: BaseCPU(params)
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{
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{
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}
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}
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@ -404,7 +404,6 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
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#endif
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#endif
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// Give the thread the TC.
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// Give the thread the TC.
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this->thread[i]->tc = tc;
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this->thread[i]->tc = tc;
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this->thread[i]->setCpuId(params->cpu_id);
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// Add the TC to the CPU's list of TC's.
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// Add the TC to the CPU's list of TC's.
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this->threadContexts.push_back(tc);
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this->threadContexts.push_back(tc);
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@ -611,7 +610,7 @@ FullO3CPU<Impl>::init()
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}
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}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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TheISA::initCPU(src_tc, src_tc->readCpuId());
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TheISA::initCPU(src_tc, src_tc->cpuId());
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#endif
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#endif
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}
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}
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@ -74,15 +74,6 @@ class BaseO3CPU : public BaseCPU
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BaseO3CPU(BaseCPUParams *params);
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BaseO3CPU(BaseCPUParams *params);
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void regStats();
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void regStats();
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/** Sets this CPU's ID. */
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void setCpuId(int id) { cpuId = id; }
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/** Reads this CPU's ID. */
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int readCpuId() { return cpuId; }
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protected:
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int cpuId;
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};
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};
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/**
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/**
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@ -593,7 +593,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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// Set the appropriate read size and flags as well.
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// Set the appropriate read size and flags as well.
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// Build request here.
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// Build request here.
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RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
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RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
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fetch_PC, cpu->readCpuId(), tid);
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fetch_PC, cpu->cpuId(), tid);
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memReq[tid] = mem_req;
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memReq[tid] = mem_req;
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@ -75,11 +75,8 @@ class O3ThreadContext : public ThreadContext
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/** Returns a pointer to this CPU. */
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/** Returns a pointer to this CPU. */
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virtual BaseCPU *getCpuPtr() { return cpu; }
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virtual BaseCPU *getCpuPtr() { return cpu; }
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/** Sets this CPU's ID. */
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virtual void setCpuId(int id) { cpu->setCpuId(id); }
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/** Reads this CPU's ID. */
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/** Reads this CPU's ID. */
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virtual int readCpuId() { return cpu->readCpuId(); }
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virtual int cpuId() { return cpu->cpuId(); }
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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/** Returns a pointer to the system. */
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/** Returns a pointer to the system. */
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@ -63,7 +63,6 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
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// copy over functional state
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// copy over functional state
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setStatus(old_context->status());
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setStatus(old_context->status());
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copyArchRegs(old_context);
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copyArchRegs(old_context);
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setCpuId(old_context->readCpuId());
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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thread->funcExeInst = old_context->readFuncExeInst();
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thread->funcExeInst = old_context->readFuncExeInst();
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@ -77,7 +77,7 @@ struct O3ThreadState : public ThreadState {
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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O3ThreadState(O3CPU *_cpu, int _thread_num)
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O3ThreadState(O3CPU *_cpu, int _thread_num)
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: ThreadState(_cpu, -1, _thread_num),
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: ThreadState(_cpu, _thread_num),
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cpu(_cpu), inSyscall(0), trapPending(0)
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cpu(_cpu), inSyscall(0), trapPending(0)
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{
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{
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if (cpu->params()->profile) {
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if (cpu->params()->profile) {
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@ -96,7 +96,7 @@ struct O3ThreadState : public ThreadState {
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}
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}
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#else
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#else
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O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
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O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
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: ThreadState(_cpu, -1, _thread_num, _process, _asid),
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: ThreadState(_cpu, _thread_num, _process, _asid),
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cpu(_cpu), inSyscall(0), trapPending(0)
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cpu(_cpu), inSyscall(0), trapPending(0)
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{ }
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{ }
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#endif
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#endif
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@ -116,10 +116,6 @@ class OzoneCPU : public BaseCPU
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||||||
|
|
||||||
BaseCPU *getCpuPtr();
|
BaseCPU *getCpuPtr();
|
||||||
|
|
||||||
void setCpuId(int id);
|
|
||||||
|
|
||||||
int readCpuId() { return thread->readCpuId(); }
|
|
||||||
|
|
||||||
TheISA::ITB *getITBPtr() { return cpu->itb; }
|
TheISA::ITB *getITBPtr() { return cpu->itb; }
|
||||||
|
|
||||||
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
|
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
|
||||||
|
@ -353,12 +349,6 @@ class OzoneCPU : public BaseCPU
|
||||||
public:
|
public:
|
||||||
BaseCPU *getCpuPtr() { return this; }
|
BaseCPU *getCpuPtr() { return this; }
|
||||||
|
|
||||||
void setCpuId(int id) { cpuId = id; }
|
|
||||||
|
|
||||||
int readCpuId() { return cpuId; }
|
|
||||||
|
|
||||||
int cpuId;
|
|
||||||
|
|
||||||
void switchOut();
|
void switchOut();
|
||||||
void signalSwitched();
|
void signalSwitched();
|
||||||
void takeOverFrom(BaseCPU *oldCPU);
|
void takeOverFrom(BaseCPU *oldCPU);
|
||||||
|
|
|
@ -417,7 +417,7 @@ OzoneCPU<Impl>::init()
|
||||||
ThreadContext *tc = threadContexts[i];
|
ThreadContext *tc = threadContexts[i];
|
||||||
|
|
||||||
// initialize CPU, including PC
|
// initialize CPU, including PC
|
||||||
TheISA::initCPU(tc, tc->readCpuId());
|
TheISA::initCPU(tc, tc->cpuId());
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
frontEnd->renameTable.copyFrom(thread.renameTable);
|
frontEnd->renameTable.copyFrom(thread.renameTable);
|
||||||
|
@ -803,7 +803,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
|
||||||
// copy over functional state
|
// copy over functional state
|
||||||
setStatus(old_context->status());
|
setStatus(old_context->status());
|
||||||
copyArchRegs(old_context);
|
copyArchRegs(old_context);
|
||||||
setCpuId(old_context->readCpuId());
|
setCpuId(old_context->cpuId());
|
||||||
|
|
||||||
thread->setInst(old_context->getInst());
|
thread->setInst(old_context->getInst());
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
|
|
|
@ -477,7 +477,7 @@ FrontEnd<Impl>::fetchCacheLine()
|
||||||
// Setup the memReq to do a read of the first isntruction's address.
|
// Setup the memReq to do a read of the first isntruction's address.
|
||||||
// Set the appropriate read size and flags as well.
|
// Set the appropriate read size and flags as well.
|
||||||
memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
|
memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
|
||||||
PC, cpu->readCpuId(), 0);
|
PC, cpu->cpuId(), 0);
|
||||||
|
|
||||||
// Translate the instruction request.
|
// Translate the instruction request.
|
||||||
fault = cpu->translateInstReq(memReq, thread);
|
fault = cpu->translateInstReq(memReq, thread);
|
||||||
|
|
|
@ -79,13 +79,12 @@ void
|
||||||
AtomicSimpleCPU::init()
|
AtomicSimpleCPU::init()
|
||||||
{
|
{
|
||||||
BaseCPU::init();
|
BaseCPU::init();
|
||||||
cpuId = tc->readCpuId();
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
for (int i = 0; i < threadContexts.size(); ++i) {
|
for (int i = 0; i < threadContexts.size(); ++i) {
|
||||||
ThreadContext *tc = threadContexts[i];
|
ThreadContext *tc = threadContexts[i];
|
||||||
|
|
||||||
// initialize CPU, including PC
|
// initialize CPU, including PC
|
||||||
TheISA::initCPU(tc, cpuId);
|
TheISA::initCPU(tc, _cpuId);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
if (hasPhysMemPort) {
|
if (hasPhysMemPort) {
|
||||||
|
@ -94,9 +93,9 @@ AtomicSimpleCPU::init()
|
||||||
physmemPort.getPeerAddressRanges(pmAddrList, snoop);
|
physmemPort.getPeerAddressRanges(pmAddrList, snoop);
|
||||||
physMemAddr = *pmAddrList.begin();
|
physMemAddr = *pmAddrList.begin();
|
||||||
}
|
}
|
||||||
ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
|
ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
|
||||||
data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
|
data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
|
||||||
data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
|
data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
|
@ -237,10 +236,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
|
||||||
_status = Idle;
|
_status = Idle;
|
||||||
}
|
}
|
||||||
assert(threadContexts.size() == 1);
|
assert(threadContexts.size() == 1);
|
||||||
cpuId = tc->readCpuId();
|
ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
|
||||||
ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
|
data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
|
||||||
data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
|
data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
|
||||||
data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -121,7 +121,6 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
*/
|
*/
|
||||||
ThreadContext *tc;
|
ThreadContext *tc;
|
||||||
protected:
|
protected:
|
||||||
int cpuId;
|
|
||||||
|
|
||||||
enum Status {
|
enum Status {
|
||||||
Idle,
|
Idle,
|
||||||
|
|
|
@ -57,13 +57,12 @@ void
|
||||||
TimingSimpleCPU::init()
|
TimingSimpleCPU::init()
|
||||||
{
|
{
|
||||||
BaseCPU::init();
|
BaseCPU::init();
|
||||||
cpuId = tc->readCpuId();
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
for (int i = 0; i < threadContexts.size(); ++i) {
|
for (int i = 0; i < threadContexts.size(); ++i) {
|
||||||
ThreadContext *tc = threadContexts[i];
|
ThreadContext *tc = threadContexts[i];
|
||||||
|
|
||||||
// initialize CPU, including PC
|
// initialize CPU, including PC
|
||||||
TheISA::initCPU(tc, cpuId);
|
TheISA::initCPU(tc, _cpuId);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -203,7 +202,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
|
||||||
_status = Idle;
|
_status = Idle;
|
||||||
}
|
}
|
||||||
assert(threadContexts.size() == 1);
|
assert(threadContexts.size() == 1);
|
||||||
cpuId = tc->readCpuId();
|
_cpuId = tc->cpuId();
|
||||||
previousTick = curTick;
|
previousTick = curTick;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -250,7 +249,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
|
||||||
{
|
{
|
||||||
Request *req =
|
Request *req =
|
||||||
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
|
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
|
||||||
cpuId, /* thread ID */ 0);
|
_cpuId, /* thread ID */ 0);
|
||||||
|
|
||||||
if (traceData) {
|
if (traceData) {
|
||||||
traceData->setAddr(req->getVaddr());
|
traceData->setAddr(req->getVaddr());
|
||||||
|
@ -301,7 +300,7 @@ TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
|
||||||
int size, unsigned flags)
|
int size, unsigned flags)
|
||||||
{
|
{
|
||||||
Request *req =
|
Request *req =
|
||||||
new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
|
new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
|
||||||
|
|
||||||
if (traceData) {
|
if (traceData) {
|
||||||
traceData->setAddr(vaddr);
|
traceData->setAddr(vaddr);
|
||||||
|
@ -373,7 +372,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
{
|
{
|
||||||
Request *req =
|
Request *req =
|
||||||
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
|
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
|
||||||
cpuId, /* thread ID */ 0);
|
_cpuId, /* thread ID */ 0);
|
||||||
|
|
||||||
if (traceData) {
|
if (traceData) {
|
||||||
traceData->setAddr(req->getVaddr());
|
traceData->setAddr(req->getVaddr());
|
||||||
|
@ -442,7 +441,7 @@ TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
|
||||||
int size, unsigned flags)
|
int size, unsigned flags)
|
||||||
{
|
{
|
||||||
Request *req =
|
Request *req =
|
||||||
new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
|
new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
|
||||||
|
|
||||||
if (traceData) {
|
if (traceData) {
|
||||||
traceData->setAddr(vaddr);
|
traceData->setAddr(vaddr);
|
||||||
|
@ -528,7 +527,7 @@ TimingSimpleCPU::fetch()
|
||||||
|
|
||||||
if (!fromRom) {
|
if (!fromRom) {
|
||||||
Request *ifetch_req = new Request();
|
Request *ifetch_req = new Request();
|
||||||
ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
|
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
|
||||||
Fault fault = setupFetchRequest(ifetch_req);
|
Fault fault = setupFetchRequest(ifetch_req);
|
||||||
|
|
||||||
ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
|
ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
|
||||||
|
|
|
@ -63,7 +63,7 @@ using namespace std;
|
||||||
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
|
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
|
||||||
TheISA::ITB *_itb, TheISA::DTB *_dtb,
|
TheISA::ITB *_itb, TheISA::DTB *_dtb,
|
||||||
bool use_kernel_stats)
|
bool use_kernel_stats)
|
||||||
: ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
|
: ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
|
||||||
dtb(_dtb)
|
dtb(_dtb)
|
||||||
|
|
||||||
{
|
{
|
||||||
|
@ -93,7 +93,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
|
||||||
#else
|
#else
|
||||||
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
|
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
|
||||||
TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
|
TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
|
||||||
: ThreadState(_cpu, -1, _thread_num, _process, _asid),
|
: ThreadState(_cpu, _thread_num, _process, _asid),
|
||||||
cpu(_cpu), itb(_itb), dtb(_dtb)
|
cpu(_cpu), itb(_itb), dtb(_dtb)
|
||||||
{
|
{
|
||||||
regs.clear();
|
regs.clear();
|
||||||
|
@ -104,9 +104,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
|
||||||
|
|
||||||
SimpleThread::SimpleThread()
|
SimpleThread::SimpleThread()
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
: ThreadState(NULL, -1, -1)
|
: ThreadState(NULL, -1)
|
||||||
#else
|
#else
|
||||||
: ThreadState(NULL, -1, -1, NULL, -1)
|
: ThreadState(NULL, -1, NULL, -1)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
tc = new ProxyThreadContext<SimpleThread>(this);
|
tc = new ProxyThreadContext<SimpleThread>(this);
|
||||||
|
@ -178,7 +178,6 @@ SimpleThread::copyState(ThreadContext *oldContext)
|
||||||
// copy over functional state
|
// copy over functional state
|
||||||
_status = oldContext->status();
|
_status = oldContext->status();
|
||||||
copyArchRegs(oldContext);
|
copyArchRegs(oldContext);
|
||||||
cpuId = oldContext->readCpuId();
|
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
funcExeInst = oldContext->readFuncExeInst();
|
funcExeInst = oldContext->readFuncExeInst();
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -74,8 +74,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
|
||||||
if (npc1 != npc2)
|
if (npc1 != npc2)
|
||||||
panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2);
|
panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2);
|
||||||
|
|
||||||
int id1 = one->readCpuId();
|
int id1 = one->cpuId();
|
||||||
int id2 = two->readCpuId();
|
int id2 = two->cpuId();
|
||||||
if (id1 != id2)
|
if (id1 != id2)
|
||||||
panic("CPU ids don't match, one: %d, two: %d", id1, id2);
|
panic("CPU ids don't match, one: %d, two: %d", id1, id2);
|
||||||
}
|
}
|
||||||
|
|
|
@ -115,9 +115,7 @@ class ThreadContext
|
||||||
|
|
||||||
virtual BaseCPU *getCpuPtr() = 0;
|
virtual BaseCPU *getCpuPtr() = 0;
|
||||||
|
|
||||||
virtual void setCpuId(int id) = 0;
|
virtual int cpuId() = 0;
|
||||||
|
|
||||||
virtual int readCpuId() = 0;
|
|
||||||
|
|
||||||
virtual TheISA::ITB *getITBPtr() = 0;
|
virtual TheISA::ITB *getITBPtr() = 0;
|
||||||
|
|
||||||
|
@ -300,9 +298,7 @@ class ProxyThreadContext : public ThreadContext
|
||||||
|
|
||||||
BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
|
BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
|
||||||
|
|
||||||
void setCpuId(int id) { actualTC->setCpuId(id); }
|
int cpuId() { return actualTC->cpuId(); }
|
||||||
|
|
||||||
int readCpuId() { return actualTC->readCpuId(); }
|
|
||||||
|
|
||||||
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
|
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
|
||||||
|
|
||||||
|
|
|
@ -43,15 +43,15 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid)
|
ThreadState::ThreadState(BaseCPU *cpu, int _tid)
|
||||||
: baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
|
: baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
|
||||||
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
|
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
|
||||||
kernelStats(NULL), physPort(NULL), virtPort(NULL),
|
kernelStats(NULL), physPort(NULL), virtPort(NULL),
|
||||||
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
|
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
|
||||||
#else
|
#else
|
||||||
ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
|
ThreadState::ThreadState(BaseCPU *cpu, int _tid, Process *_process,
|
||||||
short _asid)
|
short _asid)
|
||||||
: baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
|
: baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
|
||||||
port(NULL), process(_process), asid(_asid),
|
port(NULL), process(_process), asid(_asid),
|
||||||
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
|
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -34,6 +34,7 @@
|
||||||
#include "arch/types.hh"
|
#include "arch/types.hh"
|
||||||
#include "cpu/profile.hh"
|
#include "cpu/profile.hh"
|
||||||
#include "cpu/thread_context.hh"
|
#include "cpu/thread_context.hh"
|
||||||
|
#include "cpu/base.hh"
|
||||||
|
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
#include "mem/mem_object.hh"
|
#include "mem/mem_object.hh"
|
||||||
|
@ -51,7 +52,6 @@ namespace TheISA {
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
class BaseCPU;
|
|
||||||
class Checkpoint;
|
class Checkpoint;
|
||||||
class Port;
|
class Port;
|
||||||
class TranslatingPort;
|
class TranslatingPort;
|
||||||
|
@ -66,9 +66,9 @@ struct ThreadState {
|
||||||
typedef ThreadContext::Status Status;
|
typedef ThreadContext::Status Status;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
|
ThreadState(BaseCPU *cpu, int _tid);
|
||||||
#else
|
#else
|
||||||
ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
|
ThreadState(BaseCPU *cpu, int _tid, Process *_process,
|
||||||
short _asid);
|
short _asid);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -78,9 +78,7 @@ struct ThreadState {
|
||||||
|
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
void setCpuId(int id) { cpuId = id; }
|
int cpuId() { return baseCpu->cpuId(); }
|
||||||
|
|
||||||
int readCpuId() { return cpuId; }
|
|
||||||
|
|
||||||
void setTid(int id) { tid = id; }
|
void setTid(int id) { tid = id; }
|
||||||
|
|
||||||
|
@ -171,10 +169,6 @@ struct ThreadState {
|
||||||
// Pointer to the base CPU.
|
// Pointer to the base CPU.
|
||||||
BaseCPU *baseCpu;
|
BaseCPU *baseCpu;
|
||||||
|
|
||||||
// ID of this context w.r.t. the System or Process object to which
|
|
||||||
// it belongs. For full-system mode, this is the system CPU ID.
|
|
||||||
int cpuId;
|
|
||||||
|
|
||||||
// Index of hardware thread context on the CPU that this represents.
|
// Index of hardware thread context on the CPU that this represents.
|
||||||
int tid;
|
int tid;
|
||||||
|
|
||||||
|
|
|
@ -166,14 +166,13 @@ bool System::breakpoint()
|
||||||
}
|
}
|
||||||
|
|
||||||
int
|
int
|
||||||
System::registerThreadContext(ThreadContext *tc, int id)
|
System::registerThreadContext(ThreadContext *tc)
|
||||||
{
|
{
|
||||||
if (id == -1) {
|
int id;
|
||||||
for (id = 0; id < threadContexts.size(); id++) {
|
for (id = 0; id < threadContexts.size(); id++) {
|
||||||
if (!threadContexts[id])
|
if (!threadContexts[id])
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
|
|
||||||
if (threadContexts.size() <= id)
|
if (threadContexts.size() <= id)
|
||||||
threadContexts.resize(id + 1);
|
threadContexts.resize(id + 1);
|
||||||
|
|
|
@ -219,7 +219,7 @@ class System : public SimObject
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
int registerThreadContext(ThreadContext *tc, int tcIndex);
|
int registerThreadContext(ThreadContext *tc);
|
||||||
void replaceThreadContext(ThreadContext *tc, int tcIndex);
|
void replaceThreadContext(ThreadContext *tc, int tcIndex);
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
void serialize(std::ostream &os);
|
||||||
|
|
Loading…
Reference in a new issue