arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
This commit is contained in:
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49538a7118
commit
c53a57f74f
4 changed files with 97 additions and 23 deletions
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@ -1621,6 +1621,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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case MISCREG_DACR:
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case MISCREG_VTTBR:
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case MISCREG_SCR_EL3:
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case MISCREG_HCR_EL2:
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case MISCREG_TCR_EL1:
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case MISCREG_TCR_EL2:
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case MISCREG_TCR_EL3:
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010-2015 ARM Limited
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* Copyright (c) 2010-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -1735,10 +1735,12 @@ namespace ArmISA
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BitUnion32(VTCR_t)
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Bitfield<3, 0> t0sz;
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Bitfield<4> s;
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Bitfield<5, 0> t0sz64;
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Bitfield<7, 6> sl0;
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Bitfield<9, 8> irgn0;
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Bitfield<11, 10> orgn0;
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Bitfield<13, 12> sh0;
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Bitfield<15, 14> tg0;
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EndBitUnion(VTCR_t)
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BitUnion32(PRRR)
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@ -249,7 +249,10 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
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currState->vaddr = currState->vaddr_tainted;
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if (currState->aarch64) {
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switch (currState->el) {
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if (isStage2) {
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
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currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2);
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} else switch (currState->el) {
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case EL0:
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case EL1:
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
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@ -269,6 +272,7 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
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panic("Invalid exception level");
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break;
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}
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currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
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} else {
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currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
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MISCREG_SCTLR, currState->tc, !currState->isSecure));
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@ -289,9 +293,8 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
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// hyp mode, the second stage MMU is enabled, and this table walker
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// instance is the first stage.
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currState->doingStage2 = false;
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// @todo: for now disable this in AArch64 (HCR is not set)
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currState->stage2Req = !currState->aarch64 && currState->hcr.vm &&
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!isStage2 && !currState->isSecure && !currState->isHyp;
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currState->stage2Req = currState->hcr.vm && !isStage2 &&
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!currState->isSecure && !currState->isHyp;
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bool long_desc_format = currState->aarch64 || _isHyp || isStage2 ||
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longDescFormatInUse(currState->tc);
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@ -743,10 +746,32 @@ TableWalker::processWalkAArch64()
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int tsz = 0, ps = 0;
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GrainSize tg = Grain4KB; // grain size computed from tg* field
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bool fault = false;
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LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
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switch (currState->el) {
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case EL0:
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case EL1:
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switch (bits(currState->vaddr, 63,48)) {
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if (isStage2) {
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DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
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ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
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tsz = 64 - currState->vtcr.t0sz64;
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tg = GrainMapDefault[currState->vtcr.tg0];
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// ARM DDI 0487A.f D7-2148
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// The starting level of stage 2 translation depends on
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// VTCR_EL2.SL0 and VTCR_EL2.TG0
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LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level
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uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0;
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static const LookupLevel SLL[] = {
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L2, L3, L3, __, // sl0 == 0
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L1, L2, L2, __, // sl0 == 1, etc.
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L0, L1, L1, __,
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__, __, __, __
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};
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start_lookup_level = SLL[sl_tg];
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panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
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"Cannot discern lookup level from vtcr.{sl0,tg0}");
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} else switch (bits(currState->vaddr, 63,48)) {
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case 0:
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DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
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ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
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@ -824,16 +849,13 @@ TableWalker::processWalkAArch64()
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tg = Grain4KB;
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}
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int stride = tg - 3;
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LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
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// Determine starting lookup level
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// See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library
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// in ARM DDI 0487A. These table values correspond to the cascading tests
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// to compute the lookup level and are of the form
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// (grain_size + N*stride), for N = {1, 2, 3}.
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// A value of 64 will never succeed and a value of 0 will always succeed.
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{
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if (start_lookup_level == MAX_LOOKUP_LEVELS) {
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struct GrainMap {
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GrainSize grain_size;
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unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS];
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@ -864,6 +886,8 @@ TableWalker::processWalkAArch64()
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"Table walker couldn't find lookup level\n");
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}
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int stride = tg - 3;
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// Determine table base address
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int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg;
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Addr base_addr = mbits(ttbr, 47, base_addr_lo);
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@ -969,10 +993,9 @@ TableWalker::processWalkAArch64()
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stateQueues[start_lookup_level].push_back(currState);
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currState = NULL;
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} else if (!currState->functional) {
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port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
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NULL, (uint8_t*) &currState->longDesc.data,
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currState->tc->getCpuPtr()->clockPeriod(), flag);
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doLongDescriptor();
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fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
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sizeof(uint64_t), flag, -1, NULL,
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&TableWalker::doLongDescriptor);
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f = currState->fault;
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} else {
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RequestPtr req = new Request(desc_addr, sizeof(uint64_t), flag,
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@ -1913,8 +1936,12 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
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{
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bool isTiming = currState->timing;
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// do the requests for the page table descriptors have to go through the
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// second stage MMU
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DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n",
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descAddr, currState->stage2Req);
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// If this translation has a stage 2 then we know descAddr is an IPA and
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// needs to be translated before we can access the page table. Do that
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// check here.
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if (currState->stage2Req) {
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Fault fault;
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flags = flags | TLB::MustBeOne;
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@ -811,7 +811,19 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
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"w:%d, x:%d\n", ap, xn, pxn, r, w, x);
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if (isStage2) {
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panic("Virtualization in AArch64 state is not supported yet");
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assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2);
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// In stage 2 we use the hypervisor access permission bits.
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// The following permissions are described in ARM DDI 0487A.f
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// D4-1802
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uint8_t hap = 0x3 & te->hap;
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if (is_fetch) {
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// sctlr.wxn overrides the xn bit
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grant = !sctlr.wxn && !xn;
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} else if (is_write) {
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grant = hap & 0x2;
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} else { // is_read
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grant = hap & 0x1;
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}
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} else {
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switch (aarch64EL) {
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case EL0:
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@ -1233,14 +1245,27 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
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asid = -1;
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break;
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}
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hcr = tc->readMiscReg(MISCREG_HCR_EL2);
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scr = tc->readMiscReg(MISCREG_SCR_EL3);
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isPriv = aarch64EL != EL0;
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// @todo: modify this behaviour to support Virtualization in
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// AArch64
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if (haveVirtualization) {
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vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
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isHyp = tranType & HypMode;
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isHyp &= (tranType & S1S2NsTran) == 0;
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isHyp &= (tranType & S1CTran) == 0;
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// Work out if we should skip the first stage of translation and go
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// directly to stage 2. This value is cached so we don't have to
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// compute it for every translation.
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stage2Req = isStage2 ||
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(hcr.vm && !isHyp && !isSecure &&
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!(tranType & S1CTran) && (aarch64EL < EL2));
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directToStage2 = !isStage2 && stage2Req && !sctlr.m;
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} else {
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vmid = 0;
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isHyp = false;
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directToStage2 = false;
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stage2Req = false;
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}
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} else { // AArch32
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sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc,
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!isSecure));
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@ -1362,6 +1387,25 @@ TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
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TlbEntry *mergeTe)
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{
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Fault fault;
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if (isStage2) {
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// We are already in the stage 2 TLB. Grab the table entry for stage
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// 2 only. We are here because stage 1 translation is disabled.
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TlbEntry *s2Te = NULL;
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// Get the stage 2 table entry
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fault = getTE(&s2Te, req, tc, mode, translation, timing, functional,
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isSecure, curTranType);
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// Check permissions of stage 2
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if ((s2Te != NULL) && (fault = NoFault)) {
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if(aarch64)
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fault = checkPermissions64(s2Te, req, mode, tc);
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else
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fault = checkPermissions(s2Te, req, mode);
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}
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*te = s2Te;
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return fault;
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}
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TlbEntry *s1Te = NULL;
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Addr vaddr_tainted = req->getVaddr();
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