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CPU: Eliminate the get_vec function.

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This commit is contained in:
Gabe Black 2008-10-12 08:24:09 -07:00
parent 0c3848732e
commit c4f1cc3b48
7 changed files with 24 additions and 45 deletions
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7
src/arch/alpha/interrupts.hh
View file

@ -171,13 +171,6 @@ class Interrupts
tc->setMiscRegNoEffect(IPR_INTID, newIpl);
newInfoSet = false;
}
uint64_t
get_vec(int int_num)
{
panic("Shouldn't be called for Alpha\n");
M5_DUMMY_RETURN;
}
};
} // namespace AlphaISA

12
src/arch/mips/interrupts.cc
View file

@ -156,12 +156,6 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) {
return false;
}
uint64_t Interrupts::get_vec(int int_num)
{
panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
M5_DUMMY_RETURN
}
*/
void Interrupts::post(int int_num, ThreadContext* tc)
{
@ -252,12 +246,6 @@ void Interrupts::updateIntrInfo(ThreadContext *tc) const
;
}
uint64_t Interrupts::get_vec(int int_num)
{
panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
M5_DUMMY_RETURN
}
bool Interrupts::interruptsPending(ThreadContext *tc) const
{
//if there is a on cpu timer interrupt (i.e. Compare == Count)

4
src/arch/mips/interrupts.hh
View file

@ -91,8 +91,6 @@ class Interrupts
void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
uint64_t get_vec(int int_num);
bool check_interrupts(ThreadContext * tc) const{
//return (intstatus != 0) && !(tc->readPC() & 0x3);
if (oncputimerintr == false){
@ -160,8 +158,6 @@ class Interrupts
bool interruptsPending(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
uint64_t get_vec(int int_num);
bool check_interrupts(ThreadContext * tc) const{
return interruptsPending(tc);
}

23
src/arch/sparc/tlb.cc
View file

@ -1008,12 +1008,22 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
itb->cx_config));
break;
case ASI_SWVR_INTR_RECEIVE:
pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
{
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController());
pkt->set(interrupts->get_vec(IT_INT_VEC));
}
break;
case ASI_SWVR_UDB_INTR_R:
temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
{
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController());
temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
pkt->set(temp);
}
break;
default:
doMmuReadError:
@ -1252,12 +1262,17 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
}
break;
case ASI_SWVR_INTR_RECEIVE:
{
int msb;
// clear all the interrupts that aren't set in the write
while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data);
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController());
while(interrupts->get_vec(IT_INT_VEC) & data) {
msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
}
}
break;
case ASI_SWVR_UDB_INTR_W:
tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->

6
src/arch/x86/interrupts.hh
View file

@ -108,12 +108,6 @@ class Interrupts
panic("Interrupts::updateIntrInfo unimplemented!\n");
}
uint64_t get_vec(int int_num)
{
panic("Interrupts::get_vec unimplemented!\n");
return 0;
}
void serialize(std::ostream & os)
{
panic("Interrupts::serialize unimplemented!\n");

6
src/cpu/base.cc
View file

@ -396,12 +396,6 @@ BaseCPU::clear_interrupts()
interrupts.clear_all();
}
uint64_t
BaseCPU::get_interrupts(int int_num)
{
return interrupts.get_vec(int_num);
}
void
BaseCPU::serialize(std::ostream &os)
{

1
src/cpu/base.hh
View file

@ -119,7 +119,6 @@ class BaseCPU : public MemObject
virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts();
virtual uint64_t get_interrupts(int int_num);
bool check_interrupts(ThreadContext * tc) const
{ return interrupts.check_interrupts(tc); }