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ruby: add option for number of transitions per cycle

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The number of transitions per cycle that a controller can carry out is
a proxy for the number of ports that a controller has. This value is
currently 32 which is way too high. The patch introduces an option
for the number of ports and uses this option in the protocol files
to set the number of transitions. The default value is being set to
4. None of the se regressions change. Ruby stats for the fs regression
change and are being updated.
This commit is contained in:
Nilay Vaish 2013-08-20 11:32:31 -05:00
parent c6062a3981
commit c4e7e18eeb
8 changed files with 25 additions and 0 deletions
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4
configs/ruby/MESI_CMP_directory.py
View file

@ -98,6 +98,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
options.cpu_type == "detailed"), options.cpu_type == "detailed"),
prefetcher = prefetcher, prefetcher = prefetcher,
ruby_system = ruby_system, ruby_system = ruby_system,
transitions_per_cycle=options.ports,
enable_prefetch = False) enable_prefetch = False)
cpu_seq = RubySequencer(version = i, cpu_seq = RubySequencer(version = i,
@ -133,6 +134,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_cntrl = L2Cache_Controller(version = i, l2_cntrl = L2Cache_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
L2cache = l2_cache, L2cache = l2_cache,
transitions_per_cycle=options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
@ -172,6 +174,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
use_map = use_map =
options.use_map), options.use_map),
memBuffer = mem_cntrl, memBuffer = mem_cntrl,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@ -189,6 +192,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq, dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)

3
configs/ruby/MI_example.py
View file

@ -84,6 +84,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cacheMemory = cache, cacheMemory = cache,
send_evictions = ( send_evictions = (
options.cpu_type == "detailed"), options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i, cpu_seq = RubySequencer(version = i,
@ -139,6 +140,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
map_levels = \ map_levels = \
options.map_levels), options.map_levels),
memBuffer = mem_cntrl, memBuffer = mem_cntrl,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@ -156,6 +158,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq, dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)

4
configs/ruby/MOESI_CMP_directory.py
View file

@ -94,6 +94,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_select_num_bits = l2_bits, l2_select_num_bits = l2_bits,
send_evictions = ( send_evictions = (
options.cpu_type == "detailed"), options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i, cpu_seq = RubySequencer(version = i,
@ -128,6 +129,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_cntrl = L2Cache_Controller(version = i, l2_cntrl = L2Cache_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
L2cache = l2_cache, L2cache = l2_cache,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
@ -166,6 +168,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
size = dir_size, size = dir_size,
use_map = options.use_map), use_map = options.use_map),
memBuffer = mem_cntrl, memBuffer = mem_cntrl,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@ -183,6 +186,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq, dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)

4
configs/ruby/MOESI_CMP_token.py
View file

@ -114,6 +114,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
options.allow_atomic_migration, options.allow_atomic_migration,
send_evictions = ( send_evictions = (
options.cpu_type == "detailed"), options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i, cpu_seq = RubySequencer(version = i,
@ -149,6 +150,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
L2cache = l2_cache, L2cache = l2_cache,
N_tokens = n_tokens, N_tokens = n_tokens,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
@ -188,6 +190,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
size = dir_size), size = dir_size),
memBuffer = mem_cntrl, memBuffer = mem_cntrl,
l2_select_num_bits = l2_bits, l2_select_num_bits = l2_bits,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@ -205,6 +208,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq, dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)

3
configs/ruby/MOESI_hammer.py
View file

@ -107,6 +107,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
options.allow_atomic_migration, options.allow_atomic_migration,
send_evictions = ( send_evictions = (
options.cpu_type == "detailed"), options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i, cpu_seq = RubySequencer(version = i,
@ -196,6 +197,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
memBuffer = mem_cntrl, memBuffer = mem_cntrl,
probe_filter_enabled = options.pf_on, probe_filter_enabled = options.pf_on,
full_bit_dir_enabled = options.dir_on, full_bit_dir_enabled = options.dir_on,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
if options.recycle_latency: if options.recycle_latency:
@ -216,6 +218,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq, dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system) ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)

5
configs/ruby/Ruby.py
View file

@ -52,6 +52,11 @@ def define_options(parser):
default='2GHz', default='2GHz',
help="Clock for blocks running at Ruby system's speed") help="Clock for blocks running at Ruby system's speed")
# Options related to cache structure
parser.add_option("--ports", action="store", type="int", default=4,
help="used of transitions per cycle which is a proxy \
for the number of ports.")
# ruby network options # ruby network options
parser.add_option("--topology", type="string", default="Crossbar", parser.add_option("--topology", type="string", default="Crossbar",
help="check src/mem/ruby/network/topologies for complete set") help="check src/mem/ruby/network/topologies for complete set")

1
tests/configs/memtest-ruby.py
View file

@ -64,6 +64,7 @@ options.l1d_assoc=2
options.l1i_assoc=2 options.l1i_assoc=2
options.l2_assoc=2 options.l2_assoc=2
options.l3_assoc=2 options.l3_assoc=2
options.ports=32
#MAX CORES IS 8 with the fals sharing method #MAX CORES IS 8 with the fals sharing method
nb_cores = 8 nb_cores = 8

1
tests/configs/rubytest-ruby.py
View file

@ -65,6 +65,7 @@ options.l1d_assoc=2
options.l1i_assoc=2 options.l1i_assoc=2
options.l2_assoc=2 options.l2_assoc=2
options.l3_assoc=2 options.l3_assoc=2
options.ports=32
# Turn on flush check for the hammer protocol # Turn on flush check for the hammer protocol
check_flush = False check_flush = False