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Fix up #defines to use full path; fix up code for g++ 3.4

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SConscript:
    Remove efence option from automatically being used.

--HG--
extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69
This commit is contained in:
Kevin Lim 2005-02-11 17:54:33 -05:00
parent 1e7a744c09
commit c4d0ebd25c
21 changed files with 69 additions and 91 deletions
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2
SConscript
View file

@ -432,7 +432,7 @@ env.Append(CPPPATH='.')
# Debug binary # Debug binary
debug = env.Copy(OBJSUFFIX='.do') debug = env.Copy(OBJSUFFIX='.do')
debug.Append(CCFLAGS=Split('-g -gstabs+ -O0 -lefence')) debug.Append(CCFLAGS=Split('-g -gstabs+ -O0'))
debug.Append(CPPDEFINES='DEBUG') debug.Append(CPPDEFINES='DEBUG')
debug.Program(target = 'm5.debug', source = make_objs(sources, debug)) debug.Program(target = 'm5.debug', source = make_objs(sources, debug))

6
cpu/beta_cpu/alpha_dyn_inst.hh
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@ -1,7 +1,7 @@
//Todo: //Todo:
#ifndef __ALPHA_DYN_INST_HH__ #ifndef __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
#define __ALPHA_DYN_INST_HH__ #define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
#include "cpu/base_dyn_inst.hh" #include "cpu/base_dyn_inst.hh"
#include "cpu/beta_cpu/alpha_full_cpu.hh" #include "cpu/beta_cpu/alpha_full_cpu.hh"
@ -76,5 +76,5 @@ class AlphaDynInst : public BaseDynInst<Impl>
}; };
#endif // __ALPHA_DYN_INST_HH__ #endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__

10
cpu/beta_cpu/alpha_full_cpu.hh
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@ -3,16 +3,12 @@
// Read and write are horribly hacked up between not being sure where to // Read and write are horribly hacked up between not being sure where to
// copy their code from, and Ron's memory changes. // copy their code from, and Ron's memory changes.
#ifndef __ALPHA_FULL_CPU_HH__ #ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
#define __ALPHA_FULL_CPU_HH__ #define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
// To include: comm, full cpu, ITB/DTB if full sys, // To include: comm, full cpu, ITB/DTB if full sys,
//#include "cpu/beta_cpu/comm.hh"
//#include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/beta_cpu/full_cpu.hh" #include "cpu/beta_cpu/full_cpu.hh"
using namespace std;
template <class Impl> template <class Impl>
class AlphaFullCPU : public FullBetaCPU<Impl> class AlphaFullCPU : public FullBetaCPU<Impl>
{ {
@ -250,4 +246,4 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
}; };
#endif // __ALPHA_FULL_CPU_HH__ #endif // __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__

6
cpu/beta_cpu/alpha_impl.hh
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@ -1,5 +1,5 @@
#ifndef __ALPHA_IMPL_HH__ #ifndef __CPU_BETA_CPU_ALPHA_IMPL_HH__
#define __ALPHA_IMPL_HH__ #define __CPU_BETA_CPU_ALPHA_IMPL_HH__
#include "arch/alpha/isa_traits.hh" #include "arch/alpha/isa_traits.hh"
@ -51,4 +51,4 @@ struct AlphaSimpleImpl
}; };
}; };
#endif // __ALPHA_IMPL_HH__ #endif // __CPU_BETA_CPU_ALPHA_IMPL_HH__

18
cpu/beta_cpu/comm.hh
View file

@ -1,13 +1,11 @@
#ifndef __COMM_HH__ #ifndef __CPU_BETA_CPU_COMM_HH__
#define __COMM_HH__ #define __CPU_BETA_CPU_COMM_HH__
#include <stdint.h> #include <stdint.h>
#include <vector> #include <vector>
#include "arch/alpha/isa_traits.hh" #include "arch/alpha/isa_traits.hh"
#include "cpu/inst_seq.hh" #include "cpu/inst_seq.hh"
using namespace std;
// Find better place to put this typedef. // Find better place to put this typedef.
// The impl might be the best place for this. // The impl might be the best place for this.
typedef short int PhysRegIndex; typedef short int PhysRegIndex;
@ -18,7 +16,7 @@ struct SimpleFetchSimpleDecode {
int size; int size;
DynInstPtr insts[Impl::MaxWidth + 1]; DynInstPtr insts[Impl::MaxWidth];
}; };
template<class Impl> template<class Impl>
@ -27,7 +25,7 @@ struct SimpleDecodeSimpleRename {
int size; int size;
DynInstPtr insts[Impl::MaxWidth + 1]; DynInstPtr insts[Impl::MaxWidth];
}; };
template<class Impl> template<class Impl>
@ -36,7 +34,7 @@ struct SimpleRenameSimpleIEW {
int size; int size;
DynInstPtr insts[Impl::MaxWidth + 1]; DynInstPtr insts[Impl::MaxWidth];
}; };
template<class Impl> template<class Impl>
@ -45,7 +43,7 @@ struct SimpleIEWSimpleCommit {
int size; int size;
DynInstPtr insts[Impl::MaxWidth + 1]; DynInstPtr insts[Impl::MaxWidth];
bool squash; bool squash;
bool branchMispredict; bool branchMispredict;
@ -62,7 +60,7 @@ struct IssueStruct {
int size; int size;
DynInstPtr insts[Impl::MaxWidth + 1]; DynInstPtr insts[Impl::MaxWidth];
}; };
struct TimeBufStruct { struct TimeBufStruct {
@ -142,4 +140,4 @@ struct TimeBufStruct {
commitComm commitInfo; commitComm commitInfo;
}; };
#endif //__COMM_HH__ #endif //__CPU_BETA_CPU_COMM_HH__

4
cpu/beta_cpu/commit.cc
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@ -1,6 +1,6 @@
#include "cpu/beta_cpu/alpha_dyn_inst.hh" #include "cpu/beta_cpu/alpha_dyn_inst.hh"
#include "cpu/beta_cpu/commit_impl.hh"
#include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/beta_cpu/commit_impl.hh"
template SimpleCommit<AlphaSimpleImpl>; template class SimpleCommit<AlphaSimpleImpl>;

11
cpu/beta_cpu/commit.hh
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@ -12,14 +12,11 @@
// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just // Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
// have the original function handle writing to the IPR register. // have the original function handle writing to the IPR register.
#ifndef __SIMPLE_COMMIT_HH__ #ifndef __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
#define __SIMPLE_COMMIT_HH__ #define __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
//#include "arch/alpha/isa_traits.hh" #include "base/statistics.hh"
#include "base/timebuf.hh" #include "base/timebuf.hh"
//#include "cpu/beta_cpu/comm.hh"
//#include "cpu/beta_cpu/rename_map.hh"
//#include "cpu/beta_cpu/rob.hh"
#include "mem/memory_interface.hh" #include "mem/memory_interface.hh"
template<class Impl> template<class Impl>
@ -157,4 +154,4 @@ class SimpleCommit
Stats::Distribution<> n_committed_dist; Stats::Distribution<> n_committed_dist;
}; };
#endif // __SIMPLE_COMMIT_HH__ #endif // __CPU_BETA_CPU_SIMPLE_COMMIT_HH__

6
cpu/beta_cpu/cpu_policy.hh
View file

@ -1,5 +1,5 @@
#ifndef __CPU_POLICY_HH__ #ifndef __CPU_BETA_CPU_CPU_POLICY_HH__
#define __CPU_POLICY_HH__ #define __CPU_BETA_CPU_CPU_POLICY_HH__
#include "cpu/beta_cpu/bpred_unit.hh" #include "cpu/beta_cpu/bpred_unit.hh"
#include "cpu/beta_cpu/inst_queue.hh" #include "cpu/beta_cpu/inst_queue.hh"
@ -57,4 +57,4 @@ struct SimpleCPUPolicy
}; };
#endif //__CPU_POLICY_HH__ #endif //__CPU_BETA_CPU_CPU_POLICY_HH__

4
cpu/beta_cpu/decode.cc
View file

@ -1,6 +1,6 @@
#include "cpu/beta_cpu/alpha_dyn_inst.hh" #include "cpu/beta_cpu/alpha_dyn_inst.hh"
#include "cpu/beta_cpu/decode_impl.hh"
#include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/beta_cpu/decode_impl.hh"
template SimpleDecode<AlphaSimpleImpl>; template class SimpleDecode<AlphaSimpleImpl>;

7
cpu/beta_cpu/decode.hh
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@ -5,11 +5,12 @@
// Fix up squashing too, as it's too // Fix up squashing too, as it's too
// dependent upon the iew stage continually telling it to squash. // dependent upon the iew stage continually telling it to squash.
#ifndef __SIMPLE_DECODE_HH__ #ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
#define __SIMPLE_DECODE_HH__ #define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
#include <queue> #include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh" #include "base/timebuf.hh"
template<class Impl> template<class Impl>
@ -141,4 +142,4 @@ class SimpleDecode
Stats::Scalar<> decodeSquashedInsts; Stats::Scalar<> decodeSquashedInsts;
}; };
#endif // __SIMPLE_DECODE_HH__ #endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__

5
cpu/beta_cpu/decode_impl.hh
View file

@ -1,6 +1,3 @@
#ifndef __SIMPLE_DECODE_CC__
#define __SIMPLE_DECODE_CC__
#include "cpu/beta_cpu/decode.hh" #include "cpu/beta_cpu/decode.hh"
template<class Impl> template<class Impl>
@ -392,5 +389,3 @@ SimpleDecode<Impl>::decode()
numInst = 0; numInst = 0;
} }
#endif // __SIMPLE_DECODE_CC__

5
cpu/beta_cpu/fetch.cc
View file

@ -1,7 +1,6 @@
#include "cpu/beta_cpu/alpha_dyn_inst.hh" #include "cpu/beta_cpu/alpha_dyn_inst.hh"
#include "cpu/beta_cpu/alpha_full_cpu.hh"
#include "cpu/beta_cpu/fetch_impl.hh"
#include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/beta_cpu/fetch_impl.hh"
template SimpleFetch<AlphaSimpleImpl>; template class SimpleFetch<AlphaSimpleImpl>;

10
cpu/beta_cpu/fetch.hh
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@ -4,17 +4,17 @@
// Figure out where to advance time buffer. Add a way to get a // Figure out where to advance time buffer. Add a way to get a
// stage's current status. // stage's current status.
#ifndef __SIMPLE_FETCH_HH__ #ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__
#define __SIMPLE_FETCH_HH__ #define __CPU_BETA_CPU_SIMPLE_FETCH_HH__
//Will want to include: time buffer, structs, MemInterface, Event, //Will want to include: time buffer, structs, MemInterface, Event,
//whatever class bzero uses, MemReqPtr //whatever class bzero uses, MemReqPtr
#include "base/statistics.hh"
#include "base/timebuf.hh" #include "base/timebuf.hh"
#include "sim/eventq.hh"
#include "cpu/pc_event.hh" #include "cpu/pc_event.hh"
#include "mem/mem_interface.hh" #include "mem/mem_interface.hh"
#include "base/statistics.hh" #include "sim/eventq.hh"
/** /**
* SimpleFetch class to fetch a single instruction each cycle. SimpleFetch * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
@ -207,4 +207,4 @@ class SimpleFetch
Stats::Distribution<> fetch_nisn_dist; Stats::Distribution<> fetch_nisn_dist;
}; };
#endif //__SIMPLE_FETCH_HH__ #endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__

2
cpu/beta_cpu/full_cpu.hh
View file

@ -20,8 +20,6 @@
#include "cpu/beta_cpu/cpu_policy.hh" #include "cpu/beta_cpu/cpu_policy.hh"
#include "sim/process.hh" #include "sim/process.hh"
using namespace std;
class FunctionalMemory; class FunctionalMemory;
class Process; class Process;

7
cpu/beta_cpu/iew.cc
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@ -1,8 +1,7 @@
#include "cpu/beta_cpu/alpha_dyn_inst.hh" #include "cpu/beta_cpu/alpha_dyn_inst.hh"
#include "cpu/beta_cpu/inst_queue.hh"
#include "cpu/beta_cpu/iew_impl.hh"
#include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/beta_cpu/iew_impl.hh"
#include "cpu/beta_cpu/inst_queue.hh"
template SimpleIEW<AlphaSimpleImpl, template class SimpleIEW<AlphaSimpleImpl, AlphaSimpleImpl::CPUPol::IQ>;
AlphaSimpleImpl::CPUPol::IQ>;

8
cpu/beta_cpu/iew.hh
View file

@ -2,14 +2,14 @@
//Need to handle delaying writes to the writeback bus if it's full at the //Need to handle delaying writes to the writeback bus if it's full at the
//given time. Load store queue. //given time. Load store queue.
#ifndef __SIMPLE_IEW_HH__ #ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__
#define __SIMPLE_IEW_HH__ #define __CPU_BETA_CPU_SIMPLE_IEW_HH__
#include <queue> #include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh" #include "base/timebuf.hh"
#include "cpu/beta_cpu/comm.hh" #include "cpu/beta_cpu/comm.hh"
#include "base/statistics.hh"
//Can IEW even stall? Space should be available/allocated already...maybe //Can IEW even stall? Space should be available/allocated already...maybe
//if there's not enough write ports on the ROB or waiting for CDB //if there's not enough write ports on the ROB or waiting for CDB
@ -187,4 +187,4 @@ class SimpleIEW
Stats::Scalar<> predictedTakenIncorrect; Stats::Scalar<> predictedTakenIncorrect;
}; };
#endif #endif // __CPU_BETA_CPU_IEW_HH__

2
cpu/beta_cpu/regfile.hh
View file

@ -3,8 +3,6 @@
// @todo: Destructor // @todo: Destructor
using namespace std;
#include "arch/alpha/isa_traits.hh" #include "arch/alpha/isa_traits.hh"
#include "cpu/beta_cpu/comm.hh" #include "cpu/beta_cpu/comm.hh"

4
cpu/beta_cpu/rename.cc
View file

@ -1,6 +1,6 @@
#include "cpu/beta_cpu/alpha_dyn_inst.hh" #include "cpu/beta_cpu/alpha_dyn_inst.hh"
#include "cpu/beta_cpu/rename_impl.hh"
#include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/beta_cpu/rename_impl.hh"
template SimpleRename<AlphaSimpleImpl>; template class SimpleRename<AlphaSimpleImpl>;

7
cpu/beta_cpu/rename.hh
View file

@ -3,11 +3,12 @@
// May want to have different statuses to differentiate the different stall // May want to have different statuses to differentiate the different stall
// conditions. // conditions.
#ifndef __SIMPLE_RENAME_HH__ #ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__
#define __SIMPLE_RENAME_HH__ #define __CPU_BETA_CPU_SIMPLE_RENAME_HH__
#include <list> #include <list>
#include "base/statistics.hh"
#include "base/timebuf.hh" #include "base/timebuf.hh"
// Will need rename maps for both the int reg file and fp reg file. // Will need rename maps for both the int reg file and fp reg file.
@ -202,4 +203,4 @@ class SimpleRename
Stats::Scalar<> renameValidUndoneMaps; Stats::Scalar<> renameValidUndoneMaps;
}; };
#endif // __SIMPLE_RENAME_HH__ #endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__

20
cpu/beta_cpu/rename_map.hh
View file

@ -2,17 +2,15 @@
// Have it so that there's a more meaningful name given to the variable // Have it so that there's a more meaningful name given to the variable
// that marks the beginning of the FP registers. // that marks the beginning of the FP registers.
#ifndef __RENAME_MAP_HH__ #ifndef __CPU_BETA_CPU_RENAME_MAP_HH__
#define __RENAME_MAP_HH__ #define __CPU_BETA_CPU_RENAME_MAP_HH__
#include <iostream> #include <iostream>
#include <vector>
#include <utility> #include <utility>
#include <vector>
#include "cpu/beta_cpu/free_list.hh" #include "cpu/beta_cpu/free_list.hh"
using namespace std;
class SimpleRenameMap class SimpleRenameMap
{ {
public: public:
@ -21,7 +19,7 @@ class SimpleRenameMap
* previous mapping of a logical register to a physical register. * previous mapping of a logical register to a physical register.
* Used to roll back the rename map to a previous state. * Used to roll back the rename map to a previous state.
*/ */
typedef pair<RegIndex, PhysRegIndex> UnmapInfo; typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
/** /**
* Pair of a physical register and a physical register. Used to * Pair of a physical register and a physical register. Used to
@ -29,7 +27,7 @@ class SimpleRenameMap
* renamed to, and the previous physical register that the same * renamed to, and the previous physical register that the same
* logical register was previously mapped to. * logical register was previously mapped to.
*/ */
typedef pair<PhysRegIndex, PhysRegIndex> RenameInfo; typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
public: public:
//Constructor //Constructor
@ -128,17 +126,17 @@ class SimpleRenameMap
/** Scoreboard of physical integer registers, saying whether or not they /** Scoreboard of physical integer registers, saying whether or not they
* are ready. * are ready.
*/ */
vector<bool> intScoreboard; std::vector<bool> intScoreboard;
/** Scoreboard of physical floating registers, saying whether or not they /** Scoreboard of physical floating registers, saying whether or not they
* are ready. * are ready.
*/ */
vector<bool> floatScoreboard; std::vector<bool> floatScoreboard;
/** Scoreboard of miscellaneous registers, saying whether or not they /** Scoreboard of miscellaneous registers, saying whether or not they
* are ready. * are ready.
*/ */
vector<bool> miscScoreboard; std::vector<bool> miscScoreboard;
}; };
#endif //__RENAME_MAP_HH__ #endif //__CPU_BETA_CPU_RENAME_MAP_HH__

16
cpu/beta_cpu/rob.hh
View file

@ -4,15 +4,13 @@
// all instructions after the instruction, and all instructions after *and* // all instructions after the instruction, and all instructions after *and*
// including that instruction. // including that instruction.
#ifndef __ROB_HH__ #ifndef __CPU_BETA_CPU_ROB_HH__
#define __ROB_HH__ #define __CPU_BETA_CPU_ROB_HH__
#include<utility> #include <utility>
#include<vector> #include <vector>
#include "arch/alpha/isa_traits.hh" //#include "arch/alpha/isa_traits.hh"
using namespace std;
/** /**
* ROB class. Uses the instruction list that exists within the CPU to * ROB class. Uses the instruction list that exists within the CPU to
@ -28,7 +26,7 @@ class ROB
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef pair<RegIndex, PhysRegIndex> UnmapInfo_t; typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t;
typedef typename list<DynInstPtr>::iterator InstIt_t; typedef typename list<DynInstPtr>::iterator InstIt_t;
public: public:
@ -135,4 +133,4 @@ class ROB
bool doneSquashing; bool doneSquashing;
}; };
#endif //__ROB_HH__ #endif //__CPU_BETA_CPU_ROB_HH__