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devices should increment pkt.time instead of assiging to it

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--HG--
extra : convert_revision : b4ca3c7fc13bf0856eb2a800a11d5611b473ec3e
This commit is contained in:
Ali Saidi 2006-04-28 15:38:43 -04:00
parent 53d93ef918
commit c4b3a2fa0f
12 changed files with 28 additions and 22 deletions
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4
dev/alpha_console.cc
View file

@ -99,7 +99,7 @@ AlphaConsole::read(Packet &pkt)
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
Addr daddr = pkt.addr - pioAddr;
pkt.allocate();
@ -191,7 +191,7 @@ AlphaConsole::read(Packet &pkt)
Tick
AlphaConsole::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);

4
dev/ide_ctrl.cc
View file

@ -430,7 +430,7 @@ IdeController::read(Packet &pkt)
IdeRegType reg_type;
int disk;
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
pkt.allocate();
if (pkt.size != 1 && pkt.size != 2 && pkt.size !=4)
panic("Bad IDE read size: %d\n", pkt.size);
@ -518,7 +518,7 @@ IdeController::write(Packet &pkt)
int disk;
uint8_t oldVal, newVal;
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
parseAddr(pkt.addr, offset, channel, reg_type);

6
dev/io_device.cc
View file

@ -116,7 +116,13 @@ DmaPort::recvTiming(Packet &pkt)
DmaReqState *state;
state = (DmaReqState*)pkt.senderState;
state->completionEvent->schedule(pkt.time - pkt.req->getTime());
delete pkt.req;
delete &pkt;
} else {
delete pkt.req;
delete &pkt;
}
return Success;
}

2
dev/io_device.hh
View file

@ -167,7 +167,7 @@ class DmaPort : public Port
friend class DmaPort;
};
void sendDma(Packet &pkt);
void sendDma(Packet *pkt);
public:
DmaPort(DmaDevice *dev, Platform *p);

4
dev/isa_fake.cc
View file

@ -54,7 +54,7 @@ IsaFake::read(Packet &pkt)
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
@ -80,7 +80,7 @@ IsaFake::read(Packet &pkt)
Tick
IsaFake::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
pkt.result = Success;
return pioDelay;

4
dev/ns_gige.cc
View file

@ -493,7 +493,7 @@ NSGigE::read(Packet &pkt)
{
assert(ioEnable);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
pkt.allocate();
//The mask is to give you only the offset into the device register file
@ -729,7 +729,7 @@ NSGigE::write(Packet &pkt)
DPRINTF(EthernetPIO, "write da=%#x pa=%#x size=%d\n",
daddr, pkt.addr, pkt.size);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
if (daddr > LAST && daddr <= RESERVED) {
panic("Accessing reserved register");

4
dev/pciconfigall.cc
View file

@ -99,7 +99,7 @@ PciConfigAll::read(Packet &pkt)
int func = (daddr >> 8) & 0x7;
int reg = daddr & 0xFF;
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
pkt.allocate();
DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr,
@ -134,7 +134,7 @@ PciConfigAll::read(Packet &pkt)
Tick
PciConfigAll::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);

4
dev/sinic.cc
View file

@ -321,7 +321,7 @@ Device::read(Packet &pkt)
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
pkt.allocate();
if (!regValid(raddr))
@ -408,7 +408,7 @@ Device::write(Packet &pkt)
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
if (!regValid(raddr))
panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",

4
dev/tsunami_cchip.cc
View file

@ -76,7 +76,7 @@ TsunamiCChip::read(Packet &pkt)
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
Addr regnum = (pkt.addr - pioAddr) >> 6;
Addr daddr = (pkt.addr - pioAddr);
@ -182,7 +182,7 @@ TsunamiCChip::read(Packet &pkt)
Tick
TsunamiCChip::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);

4
dev/tsunami_io.cc
View file

@ -441,7 +441,7 @@ TsunamiIO::read(Packet &pkt)
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
Addr daddr = pkt.addr - pioAddr;
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt.addr,
@ -505,7 +505,7 @@ TsunamiIO::read(Packet &pkt)
Tick
TsunamiIO::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);

4
dev/tsunami_pchip.cc
View file

@ -71,7 +71,7 @@ TsunamiPChip::read(Packet &pkt)
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
pkt.allocate();
Addr daddr = (pkt.addr - pioAddr) >> 6;;
assert(pkt.size == sizeof(uint64_t));
@ -151,7 +151,7 @@ TsunamiPChip::read(Packet &pkt)
Tick
TsunamiPChip::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);

4
dev/uart8250.cc
View file

@ -114,7 +114,7 @@ Uart8250::read(Packet &pkt)
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
assert(pkt.size == 1);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
Addr daddr = pkt.addr - pioAddr;
pkt.allocate();
@ -198,7 +198,7 @@ Uart8250::write(Packet &pkt)
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
assert(pkt.size == 1);
pkt.time = curTick + pioDelay;
pkt.time += pioDelay;
Addr daddr = pkt.addr - pioAddr;
DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt.get<uint8_t>());