devices should increment pkt.time instead of assiging to it
--HG-- extra : convert_revision : b4ca3c7fc13bf0856eb2a800a11d5611b473ec3e
This commit is contained in:
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53d93ef918
commit
c4b3a2fa0f
12 changed files with 28 additions and 22 deletions
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@ -99,7 +99,7 @@ AlphaConsole::read(Packet &pkt)
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = pkt.addr - pioAddr;
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pkt.allocate();
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pkt.allocate();
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@ -191,7 +191,7 @@ AlphaConsole::read(Packet &pkt)
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Tick
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Tick
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AlphaConsole::write(Packet &pkt)
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AlphaConsole::write(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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@ -430,7 +430,7 @@ IdeController::read(Packet &pkt)
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IdeRegType reg_type;
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IdeRegType reg_type;
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int disk;
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int disk;
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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pkt.allocate();
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pkt.allocate();
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if (pkt.size != 1 && pkt.size != 2 && pkt.size !=4)
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if (pkt.size != 1 && pkt.size != 2 && pkt.size !=4)
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panic("Bad IDE read size: %d\n", pkt.size);
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panic("Bad IDE read size: %d\n", pkt.size);
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@ -518,7 +518,7 @@ IdeController::write(Packet &pkt)
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int disk;
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int disk;
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uint8_t oldVal, newVal;
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uint8_t oldVal, newVal;
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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parseAddr(pkt.addr, offset, channel, reg_type);
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parseAddr(pkt.addr, offset, channel, reg_type);
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@ -116,7 +116,13 @@ DmaPort::recvTiming(Packet &pkt)
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DmaReqState *state;
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DmaReqState *state;
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state = (DmaReqState*)pkt.senderState;
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state = (DmaReqState*)pkt.senderState;
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state->completionEvent->schedule(pkt.time - pkt.req->getTime());
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state->completionEvent->schedule(pkt.time - pkt.req->getTime());
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delete pkt.req;
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delete &pkt;
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} else {
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delete pkt.req;
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delete &pkt;
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}
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}
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return Success;
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return Success;
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}
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}
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@ -203,7 +209,7 @@ DmaPort::sendDma(Packet *pkt)
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if (state == Timing) {
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if (state == Timing) {
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if (sendTiming(pkt) == Failure)
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if (sendTiming(pkt) == Failure)
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transmitList.push_back(&packet);
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transmitList.push_back(&packet);
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} else if (state == Atomic) {*/
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} else if (state == Atomic) {*/
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sendAtomic(*pkt);
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sendAtomic(*pkt);
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if (pkt->senderState) {
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if (pkt->senderState) {
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DmaReqState *state = (DmaReqState*)pkt->senderState;
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DmaReqState *state = (DmaReqState*)pkt->senderState;
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@ -167,7 +167,7 @@ class DmaPort : public Port
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friend class DmaPort;
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friend class DmaPort;
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};
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};
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void sendDma(Packet &pkt);
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void sendDma(Packet *pkt);
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public:
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public:
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DmaPort(DmaDevice *dev, Platform *p);
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DmaPort(DmaDevice *dev, Platform *p);
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@ -54,7 +54,7 @@ IsaFake::read(Packet &pkt)
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
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@ -80,7 +80,7 @@ IsaFake::read(Packet &pkt)
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Tick
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Tick
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IsaFake::write(Packet &pkt)
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IsaFake::write(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
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DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
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pkt.result = Success;
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pkt.result = Success;
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return pioDelay;
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return pioDelay;
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@ -493,7 +493,7 @@ NSGigE::read(Packet &pkt)
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{
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{
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assert(ioEnable);
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assert(ioEnable);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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pkt.allocate();
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pkt.allocate();
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//The mask is to give you only the offset into the device register file
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//The mask is to give you only the offset into the device register file
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@ -729,7 +729,7 @@ NSGigE::write(Packet &pkt)
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DPRINTF(EthernetPIO, "write da=%#x pa=%#x size=%d\n",
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DPRINTF(EthernetPIO, "write da=%#x pa=%#x size=%d\n",
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daddr, pkt.addr, pkt.size);
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daddr, pkt.addr, pkt.size);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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if (daddr > LAST && daddr <= RESERVED) {
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if (daddr > LAST && daddr <= RESERVED) {
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panic("Accessing reserved register");
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panic("Accessing reserved register");
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@ -99,7 +99,7 @@ PciConfigAll::read(Packet &pkt)
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int func = (daddr >> 8) & 0x7;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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int reg = daddr & 0xFF;
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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pkt.allocate();
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pkt.allocate();
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DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr,
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DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr,
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@ -134,7 +134,7 @@ PciConfigAll::read(Packet &pkt)
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Tick
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Tick
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PciConfigAll::write(Packet &pkt)
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PciConfigAll::write(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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@ -321,7 +321,7 @@ Device::read(Packet &pkt)
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Addr index = daddr >> Regs::VirtualShift;
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Addr index = daddr >> Regs::VirtualShift;
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Addr raddr = daddr & Regs::VirtualMask;
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Addr raddr = daddr & Regs::VirtualMask;
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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pkt.allocate();
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pkt.allocate();
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if (!regValid(raddr))
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if (!regValid(raddr))
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@ -408,7 +408,7 @@ Device::write(Packet &pkt)
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Addr index = daddr >> Regs::VirtualShift;
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Addr index = daddr >> Regs::VirtualShift;
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Addr raddr = daddr & Regs::VirtualMask;
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Addr raddr = daddr & Regs::VirtualMask;
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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if (!regValid(raddr))
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if (!regValid(raddr))
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panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
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panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
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@ -76,7 +76,7 @@ TsunamiCChip::read(Packet &pkt)
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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Addr regnum = (pkt.addr - pioAddr) >> 6;
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Addr regnum = (pkt.addr - pioAddr) >> 6;
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Addr daddr = (pkt.addr - pioAddr);
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Addr daddr = (pkt.addr - pioAddr);
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@ -182,7 +182,7 @@ TsunamiCChip::read(Packet &pkt)
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Tick
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Tick
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TsunamiCChip::write(Packet &pkt)
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TsunamiCChip::write(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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@ -441,7 +441,7 @@ TsunamiIO::read(Packet &pkt)
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = pkt.addr - pioAddr;
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DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt.addr,
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DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt.addr,
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@ -505,7 +505,7 @@ TsunamiIO::read(Packet &pkt)
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Tick
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Tick
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TsunamiIO::write(Packet &pkt)
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TsunamiIO::write(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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@ -71,7 +71,7 @@ TsunamiPChip::read(Packet &pkt)
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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pkt.allocate();
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pkt.allocate();
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Addr daddr = (pkt.addr - pioAddr) >> 6;;
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Addr daddr = (pkt.addr - pioAddr) >> 6;;
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assert(pkt.size == sizeof(uint64_t));
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assert(pkt.size == sizeof(uint64_t));
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@ -151,7 +151,7 @@ TsunamiPChip::read(Packet &pkt)
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Tick
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Tick
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TsunamiPChip::write(Packet &pkt)
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TsunamiPChip::write(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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@ -114,7 +114,7 @@ Uart8250::read(Packet &pkt)
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.size == 1);
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assert(pkt.size == 1);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = pkt.addr - pioAddr;
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pkt.allocate();
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pkt.allocate();
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@ -198,7 +198,7 @@ Uart8250::write(Packet &pkt)
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.size == 1);
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assert(pkt.size == 1);
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pkt.time = curTick + pioDelay;
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pkt.time += pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = pkt.addr - pioAddr;
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt.get<uint8_t>());
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt.get<uint8_t>());
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