mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.
This commit is contained in:
Andreas Hansson
parent
eaa37e611f
commit
c4898b15bc
7 changed files with 111 additions and 35 deletions
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@ -73,7 +73,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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# base address (including the PCI config space)
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self.bridge = Bridge(delay='50ns',
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ranges = [AddrRange(IO_address_space_base, Addr.max)])
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self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
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self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
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self.mem_ranges = [self.physmem.range]
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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@ -110,7 +110,7 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
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physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
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self = LinuxAlphaSystem(physmem = physmem)
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self.mem_ranges = [self.physmem.range]
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if not mdesc:
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@ -180,9 +180,9 @@ def makeSparcSystem(mem_mode, mdesc = None):
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self.t1000 = T1000()
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self.t1000.attachOnChipIO(self.membus)
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self.t1000.attachIO(self.iobus)
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self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'),
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self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'),
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zero = True)
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self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'),
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self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'),
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zero = True)
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self.mem_ranges = [self.physmem.range, self.physmem2.range]
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self.bridge.master = self.iobus.slave
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@ -274,7 +274,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart.end_on_eot = True
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self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())),
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self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())),
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zero = True)
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self.mem_ranges = [self.physmem.range]
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else:
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@ -289,7 +289,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
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'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
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self.physmem = SimpleDRAM(range =
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self.physmem = SimpleDDR3(range =
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AddrRange(self.realview.mem_start_addr,
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size = mdesc.mem()),
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conf_table_reported = True)
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@ -328,7 +328,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
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self.iobus = NoncoherentBus()
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self.membus = MemBus()
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self.bridge = Bridge(delay='50ns')
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self.physmem = SimpleDRAM(range = AddrRange('1GB'))
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self.physmem = SimpleDDR3(range = AddrRange('1GB'))
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self.mem_ranges = [self.physmem.range]
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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@ -434,7 +434,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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self.mem_mode = mem_mode
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# Physical memory
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self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
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self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
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self.mem_ranges = [self.physmem.range]
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# Platform
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@ -63,11 +63,6 @@ class SimpleDRAM(AbstractMemory):
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# bus in front of the controller for multiple ports
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port = SlavePort("Slave port")
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# the physical organisation of the DRAM
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lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines")
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ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel")
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banks_per_rank = Param.Unsigned(8, "Number of banks per rank")
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# the basic configuration of the controller architecture
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write_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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read_buffer_size = Param.Unsigned(32, "Number of write queue entries")
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@ -77,21 +72,26 @@ class SimpleDRAM(AbstractMemory):
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write_thresh_perc = Param.Percent(70, "Threshold to trigger writes")
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# scheduler, address map and page policy
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mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy")
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mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
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addr_mapping = Param.AddrMap('openmap', "Address mapping policy")
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page_policy = Param.PageManage('open', "Page closure management policy")
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# the physical organisation of the DRAM
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lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines")
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ranks_per_channel = Param.Unsigned("Number of ranks per channel")
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banks_per_rank = Param.Unsigned("Number of banks per rank")
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# timing behaviour and constraints - all in nanoseconds
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# the amount of time in nanoseconds from issuing an activate command
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# to the data being available in the row buffer for a read/write
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tRCD = Param.Latency("14ns", "RAS to CAS delay")
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tRCD = Param.Latency("RAS to CAS delay")
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# the time from issuing a read/write command to seeing the actual data
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tCL = Param.Latency("14ns", "CAS latency")
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tCL = Param.Latency("CAS latency")
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# minimum time between a precharge and subsequent activate
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tRP = Param.Latency("14ns", "Row precharge time")
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tRP = Param.Latency("Row precharge time")
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# time to complete a burst transfer, typically the burst length
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# divided by two due to the DDR bus, but by making it a parameter
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@ -99,23 +99,22 @@ class SimpleDRAM(AbstractMemory):
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# This parameter has to account for bus width and burst length.
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# Adjustment also necessary if cache line size is greater than
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# data size read/written by one full burst.
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tBURST = Param.Latency("4ns",
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"Burst duration (for DDR burst length / 2 cycles)")
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tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
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# time taken to complete one refresh cycle (N rows in all banks)
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tRFC = Param.Latency("300ns", "Refresh cycle time")
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tRFC = Param.Latency("Refresh cycle time")
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# refresh command interval, how often a "ref" command needs
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# to be sent. It is 7.8 us for a 64ms refresh requirement
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tREFI = Param.Latency("7.8us", "Refresh command interval")
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tREFI = Param.Latency("Refresh command interval")
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# write-to-read turn around penalty, assumed same as read-to-write
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tWTR = Param.Latency("1ns", "Write to read switching time")
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tWTR = Param.Latency("Write to read switching time")
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# time window in which a maximum number of activates are allowed
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# to take place, set to 0 to disable
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tXAW = Param.Latency("0ns", "X activation window")
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activation_limit = Param.Unsigned(4, "Max number of activates in window")
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tXAW = Param.Latency("X activation window")
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activation_limit = Param.Unsigned("Max number of activates in window")
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# Currently rolled into other params
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######################################################################
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@ -127,3 +126,80 @@ class SimpleDRAM(AbstractMemory):
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# tRC - assumed to be 4 * tRP
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# burst length for an access derived from peerBlockSize
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# High-level model of a single DDR3 x64 interface (one command and
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# address bus), with default timings based on a DDR3-1600 4 Gbit part,
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# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4
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# configuration.
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class SimpleDDR3(SimpleDRAM):
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# Assuming 64 byte cache lines, use a 2kbyte page size, this
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# depends on the memory density
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lines_per_rowbuffer = 32
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# Use two ranks
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ranks_per_channel = 2
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# DDR3 has 8 banks in all configurations
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banks_per_rank = 8
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# DDR3-1600 11-11-11
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tRCD = '13.75ns'
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tCL = '13.75ns'
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tRP = '13.75ns'
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# Assuming 64 byte cache lines, across an x64 (8x8 or 16x4)
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# interface, translates to BL8, 4 clocks @ 800 MHz
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tBURST = '5ns'
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# DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns
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tRFC = '300ns'
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# DDR3, <=85C, half for >85C
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tREFI = '7.8us'
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# Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
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tWTR = '7.5ns'
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# With a 2kbyte page size, DDR3-1600 lands around 40 ns
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tXAW = '40ns'
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activation_limit = 4
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# High-level model of a single LPDDR2-S4 x64 interface (one
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# command/address bus), with default timings based on a LPDDR2-1066
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# 4Gbit part, which whould amount to 1 GByte of memory in 2x32 or
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# 2GByte in 4x16 configuration.
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class SimpleLPDDR2_S4(SimpleDRAM):
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# Assuming 64 byte cache lines, use a 2kbyte page size, this
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# depends on the memory density
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lines_per_rowbuffer = 32
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# Use two ranks
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ranks_per_channel = 2
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# LPDDR2-S4 has 8 banks in all configurations
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banks_per_rank = 8
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# Fixed at 15 ns
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tRCD = '15ns'
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# 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
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tCL = '15ns'
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# Pre-charge one bank 15 ns and all banks 18 ns
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tRP = '18ns'
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# Assuming 64 byte cache lines, across a x64 interface (2x32 or
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# 4x16), translates to BL8, 4 clocks @ 533 MHz
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tBURST = '7.5ns'
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# LPDDR2-S4, 4 Gb
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tRFC = '130ns'
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tREFI = '3.9us'
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# Irrespective of speed grade, tWTR is 7.5 ns
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tWTR = '7.5ns'
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# Irrespective of size, tFAW is 50 ns
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tXAW = '50ns'
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activation_limit = 4
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@ -39,7 +39,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleDRAM(),
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physmem = SimpleDDR3(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleDRAM(),
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physmem = SimpleDDR3(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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@ -36,7 +36,7 @@ cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus,
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physmem = SimpleDRAM(),
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physmem = SimpleDDR3(),
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membus = CoherentBus(),
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mem_mode = "timing")
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@ -41,7 +41,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleDRAM(),
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physmem = SimpleDDR3(),
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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@ -48,7 +48,7 @@ require_sim_object("CommMonitor")
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cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
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# system simulated
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system = System(cpu = cpu, physmem = SimpleDRAM(),
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system = System(cpu = cpu, physmem = SimpleDDR3(),
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membus = NoncoherentBus(clock="1GHz", width = 16))
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# add a communication monitor
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