Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 2f7f50f4ad31f741c0c67db96e49d30ca078fc94
This commit is contained in:
Ali Saidi
commit
c46e946c94
8 changed files with 487 additions and 97 deletions
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@ -647,11 +647,9 @@ void MiscRegFile::setReg(int miscReg,
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return;
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case MISCREG_CWP:
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new_val = val >= NWindows ? NWindows - 1 : val;
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if (val >= NWindows) {
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if (val >= NWindows)
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new_val = NWindows - 1;
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warn("Attempted to set the CWP to %d with NWindows = %d\n",
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val, NWindows);
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}
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tc->changeRegFileContext(CONTEXT_CWP, new_val);
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break;
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case MISCREG_GL:
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@ -55,10 +55,10 @@ using namespace iGbReg;
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using namespace Net;
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IGbE::IGbE(Params *p)
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: PciDev(p), etherInt(NULL), useFlowControl(p->use_flow_control),
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: PciDev(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
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txTick(false), rdtrEvent(this), radvEvent(this), tadvEvent(this),
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tidvEvent(this), tickEvent(this), interEvent(this),
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txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this),
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tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
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rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
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txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
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{
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@ -223,6 +223,7 @@ IGbE::read(PacketPtr pkt)
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pkt->set<uint32_t>(regs.rdtr());
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if (regs.rdtr.fpd()) {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting interrupt because of RDTR.FPD write\n");
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postInterrupt(IT_RXT);
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regs.rdtr.fpd(0);
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}
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@ -411,6 +412,7 @@ IGbE::write(PacketPtr pkt)
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regs.itr = val;
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break;
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case REG_ICS:
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DPRINTF(EthernetIntr, "Posting interrupt because of ICS write\n");
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postInterrupt((IntTypes)val);
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break;
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case REG_IMS:
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@ -429,6 +431,7 @@ IGbE::write(PacketPtr pkt)
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regs.rctl = val;
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if (regs.rctl.rst()) {
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rxDescCache.reset();
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DPRINTF(EthernetSM, "RXS: Got RESET!\n");
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rxFifo.clear();
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regs.rctl.rst(0);
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}
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@ -568,7 +571,7 @@ IGbE::postInterrupt(IntTypes t, bool now)
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} else {
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DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
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Clock::Int::ns * 256 * regs.itr.interval());
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assert(!interEvent.scheduled());
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if (!interEvent.scheduled())
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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}
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}
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@ -676,39 +679,39 @@ IGbE::RxDescCache::pktComplete()
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// no support for anything but starting at 0
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assert(igbe->regs.rxcsum.pcss() == 0);
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DPRINTF(EthernetDesc, "RxDesc: Packet written to memory updating Descriptor\n");
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DPRINTF(EthernetDesc, "Packet written to memory updating Descriptor\n");
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uint8_t status = RXDS_DD | RXDS_EOP;
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uint8_t err = 0;
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IpPtr ip(pktPtr);
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if (ip) {
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if (igbe->regs.rxcsum.ipofld()) {
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DPRINTF(EthernetDesc, "RxDesc: Checking IP checksum\n");
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DPRINTF(EthernetDesc, "Checking IP checksum\n");
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status |= RXDS_IPCS;
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desc->csum = htole(cksum(ip));
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if (cksum(ip) != 0) {
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err |= RXDE_IPE;
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DPRINTF(EthernetDesc, "RxDesc: Checksum is bad!!\n");
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DPRINTF(EthernetDesc, "Checksum is bad!!\n");
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}
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}
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TcpPtr tcp(ip);
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if (tcp && igbe->regs.rxcsum.tuofld()) {
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DPRINTF(EthernetDesc, "RxDesc: Checking TCP checksum\n");
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DPRINTF(EthernetDesc, "Checking TCP checksum\n");
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status |= RXDS_TCPCS;
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desc->csum = htole(cksum(tcp));
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if (cksum(tcp) != 0) {
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DPRINTF(EthernetDesc, "RxDesc: Checksum is bad!!\n");
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DPRINTF(EthernetDesc, "Checksum is bad!!\n");
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err |= RXDE_TCPE;
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}
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}
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UdpPtr udp(ip);
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if (udp && igbe->regs.rxcsum.tuofld()) {
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DPRINTF(EthernetDesc, "RxDesc: Checking UDP checksum\n");
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DPRINTF(EthernetDesc, "Checking UDP checksum\n");
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status |= RXDS_UDPCS;
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desc->csum = htole(cksum(udp));
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if (cksum(tcp) != 0) {
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DPRINTF(EthernetDesc, "RxDesc: Checksum is bad!!\n");
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DPRINTF(EthernetDesc, "Checksum is bad!!\n");
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err |= RXDE_TCPE;
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}
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}
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@ -748,15 +751,18 @@ IGbE::RxDescCache::pktComplete()
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// If the packet is small enough, interrupt appropriately
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// I wonder if this is delayed or not?!
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if (pktPtr->length <= igbe->regs.rsrpd.idv())
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if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
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DPRINTF(EthernetSM, "RXS: Posting IT_SRPD beacuse small packet received\n");
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igbe->postInterrupt(IT_SRPD);
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}
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DPRINTF(EthernetDesc, "RxDesc: Processing of this descriptor complete\n");
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DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
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unusedCache.pop_front();
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usedCache.push_back(desc);
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pktPtr = NULL;
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enableSm();
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pktDone = true;
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igbe->checkDrain();
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}
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void
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@ -776,11 +782,33 @@ IGbE::RxDescCache::packetDone()
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return false;
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}
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bool
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IGbE::RxDescCache::hasOutstandingEvents()
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{
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return pktEvent.scheduled() || wbEvent.scheduled() ||
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fetchEvent.scheduled();
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}
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void
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IGbE::RxDescCache::serialize(std::ostream &os)
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{
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DescCache<RxDesc>::serialize(os);
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SERIALIZE_SCALAR(pktDone);
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}
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void
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IGbE::RxDescCache::unserialize(Checkpoint *cp, const std::string §ion)
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{
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DescCache<RxDesc>::unserialize(cp, section);
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UNSERIALIZE_SCALAR(pktDone);
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}
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///////////////////////////////////// IGbE::TxDesc /////////////////////////////////
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IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
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: DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), pktWaiting(false),
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hLen(0), pktEvent(this)
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pktEvent(this)
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{
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}
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@ -792,10 +820,10 @@ IGbE::TxDescCache::getPacketSize()
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TxDesc *desc;
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DPRINTF(EthernetDesc, "TxDesc: Starting processing of descriptor\n");
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DPRINTF(EthernetDesc, "Starting processing of descriptor\n");
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while (unusedCache.size() && TxdOp::isContext(unusedCache.front())) {
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DPRINTF(EthernetDesc, "TxDesc: Got context descriptor type... skipping\n");
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DPRINTF(EthernetDesc, "Got context descriptor type... skipping\n");
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// I think we can just ignore these for now?
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desc = unusedCache.front();
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@ -813,7 +841,7 @@ IGbE::TxDescCache::getPacketSize()
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if (!unusedCache.size())
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return -1;
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DPRINTF(EthernetDesc, "TxDesc: Next TX packet is %d bytes\n",
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DPRINTF(EthernetDesc, "Next TX packet is %d bytes\n",
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TxdOp::getLen(unusedCache.front()));
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return TxdOp::getLen(unusedCache.front());
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@ -833,9 +861,9 @@ IGbE::TxDescCache::getPacketData(EthPacketPtr p)
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pktWaiting = true;
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DPRINTF(EthernetDesc, "TxDesc: Starting DMA of packet\n");
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DPRINTF(EthernetDesc, "Starting DMA of packet\n");
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igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
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TxdOp::getLen(desc), &pktEvent, p->data + hLen);
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TxdOp::getLen(desc), &pktEvent, p->data + p->length);
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}
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@ -848,7 +876,7 @@ IGbE::TxDescCache::pktComplete()
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assert(unusedCache.size());
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assert(pktPtr);
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DPRINTF(EthernetDesc, "TxDesc: DMA of packet complete\n");
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DPRINTF(EthernetDesc, "DMA of packet complete\n");
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desc = unusedCache.front();
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@ -857,20 +885,21 @@ IGbE::TxDescCache::pktComplete()
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DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
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if (!TxdOp::eop(desc)) {
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assert(hLen == 0);
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hLen = TxdOp::getLen(desc);
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// This only supports two descriptors per tx packet
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assert(pktPtr->length == 0);
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pktPtr->length = TxdOp::getLen(desc);
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unusedCache.pop_front();
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usedCache.push_back(desc);
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pktDone = true;
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pktWaiting = false;
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pktPtr = NULL;
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DPRINTF(EthernetDesc, "TxDesc: Partial Packet Descriptor Done\n");
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DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n");
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return;
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}
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// Set the length of the data in the EtherPacket
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pktPtr->length = TxdOp::getLen(desc) + hLen;
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pktPtr->length += TxdOp::getLen(desc);
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// no support for vlans
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assert(!TxdOp::vle(desc));
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@ -888,33 +917,33 @@ IGbE::TxDescCache::pktComplete()
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// Checksums are only ofloaded for new descriptor types
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if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
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DPRINTF(EthernetDesc, "TxDesc: Calculating checksums for packet\n");
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DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
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IpPtr ip(pktPtr);
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if (TxdOp::ixsm(desc)) {
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ip->sum(0);
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ip->sum(cksum(ip));
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DPRINTF(EthernetDesc, "TxDesc: Calculated IP checksum\n");
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DPRINTF(EthernetDesc, "Calculated IP checksum\n");
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}
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if (TxdOp::txsm(desc)) {
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if (isTcp) {
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TcpPtr tcp(ip);
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tcp->sum(0);
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tcp->sum(cksum(tcp));
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DPRINTF(EthernetDesc, "TxDesc: Calculated TCP checksum\n");
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DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
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} else {
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UdpPtr udp(ip);
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udp->sum(0);
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udp->sum(cksum(udp));
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DPRINTF(EthernetDesc, "TxDesc: Calculated UDP checksum\n");
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DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
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}
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}
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}
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if (TxdOp::ide(desc)) {
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// Deal with the rx timer interrupts
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DPRINTF(EthernetDesc, "TxDesc: Descriptor had IDE set\n");
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DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
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if (igbe->regs.tidv.idv()) {
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DPRINTF(EthernetDesc, "TxDesc: setting tidv\n");
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DPRINTF(EthernetDesc, "setting tidv\n");
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if (igbe->tidvEvent.scheduled())
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igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
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igbe->intClock());
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@ -924,7 +953,7 @@ IGbE::TxDescCache::pktComplete()
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}
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if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
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DPRINTF(EthernetDesc, "TxDesc: setting tadv\n");
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DPRINTF(EthernetDesc, "setting tadv\n");
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if (!igbe->tadvEvent.scheduled())
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igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
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igbe->intClock());
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@ -939,17 +968,34 @@ IGbE::TxDescCache::pktComplete()
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pktWaiting = false;
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pktPtr = NULL;
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hLen = 0;
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DPRINTF(EthernetDesc, "TxDesc: Descriptor Done\n");
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DPRINTF(EthernetDesc, "Descriptor Done\n");
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if (igbe->regs.txdctl.wthresh() == 0) {
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DPRINTF(EthernetDesc, "TxDesc: WTHRESH == 0, writing back descriptor\n");
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DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n");
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writeback(0);
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} else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) {
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DPRINTF(EthernetDesc, "TxDesc: used > WTHRESH, writing back descriptor\n");
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DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
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writeback((igbe->cacheBlockSize()-1)>>4);
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}
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igbe->checkDrain();
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}
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void
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IGbE::TxDescCache::serialize(std::ostream &os)
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{
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DescCache<TxDesc>::serialize(os);
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SERIALIZE_SCALAR(pktDone);
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SERIALIZE_SCALAR(isTcp);
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SERIALIZE_SCALAR(pktWaiting);
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}
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void
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IGbE::TxDescCache::unserialize(Checkpoint *cp, const std::string §ion)
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{
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DescCache<TxDesc>::unserialize(cp, section);
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UNSERIALIZE_SCALAR(pktDone);
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UNSERIALIZE_SCALAR(isTcp);
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UNSERIALIZE_SCALAR(pktWaiting);
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}
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bool
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@ -969,7 +1015,12 @@ IGbE::TxDescCache::enableSm()
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igbe->restartClock();
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}
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bool
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IGbE::TxDescCache::hasOutstandingEvents()
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{
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return pktEvent.scheduled() || wbEvent.scheduled() ||
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fetchEvent.scheduled();
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}
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///////////////////////////////////// IGbE /////////////////////////////////
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@ -977,10 +1028,61 @@ IGbE::TxDescCache::enableSm()
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void
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IGbE::restartClock()
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{
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if (!tickEvent.scheduled() && (rxTick || txTick))
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if (!tickEvent.scheduled() && (rxTick || txTick) && getState() ==
|
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SimObject::Running)
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tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1));
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}
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unsigned int
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IGbE::drain(Event *de)
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{
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unsigned int count;
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count = pioPort->drain(de) + dmaPort->drain(de);
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if (rxDescCache.hasOutstandingEvents() ||
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txDescCache.hasOutstandingEvents()) {
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count++;
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drainEvent = de;
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}
|
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|
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txFifoTick = false;
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txTick = false;
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rxTick = false;
|
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|
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if (tickEvent.scheduled())
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tickEvent.deschedule();
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if (count)
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changeState(Draining);
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else
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changeState(Drained);
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return count;
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}
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|
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void
|
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IGbE::resume()
|
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{
|
||||
SimObject::resume();
|
||||
|
||||
txFifoTick = true;
|
||||
txTick = true;
|
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rxTick = true;
|
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|
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restartClock();
|
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}
|
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|
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void
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IGbE::checkDrain()
|
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{
|
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if (!drainEvent)
|
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return;
|
||||
|
||||
if (rxDescCache.hasOutstandingEvents() ||
|
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txDescCache.hasOutstandingEvents()) {
|
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drainEvent->process();
|
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drainEvent = NULL;
|
||||
}
|
||||
}
|
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|
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void
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IGbE::txStateMachine()
|
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|
|
@ -998,8 +1100,10 @@ IGbE::txStateMachine()
|
|||
bool success;
|
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DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
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success = txFifo.push(txPacket);
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txFifoTick = true;
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assert(success);
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txPacket = NULL;
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txDescCache.writeback((cacheBlockSize()-1)>>4);
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return;
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}
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|
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@ -1021,6 +1125,7 @@ IGbE::txStateMachine()
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txDescCache.writeback(0);
|
||||
txTick = false;
|
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postInterrupt(IT_TXQE, true);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1038,11 +1143,17 @@ IGbE::txStateMachine()
|
|||
"DMA of next packet\n", size);
|
||||
txFifo.reserve(size);
|
||||
txDescCache.getPacketData(txPacket);
|
||||
} else {
|
||||
} else if (size <= 0) {
|
||||
DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
|
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txDescCache.writeback(0);
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||||
} else {
|
||||
DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
|
||||
"available in FIFO\n");
|
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txDescCache.writeback((cacheBlockSize()-1)>>4);
|
||||
txTick = false;
|
||||
}
|
||||
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -1095,9 +1206,9 @@ IGbE::rxStateMachine()
|
|||
}
|
||||
|
||||
if (descLeft == 0) {
|
||||
DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing writeback\n");
|
||||
DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
|
||||
" writeback and stopping ticking\n");
|
||||
rxDescCache.writeback(0);
|
||||
DPRINTF(EthernetSM, "RXS: No descriptors left, stopping ticking\n");
|
||||
rxTick = false;
|
||||
}
|
||||
|
||||
|
|
@ -1119,9 +1230,9 @@ IGbE::rxStateMachine()
|
|||
}
|
||||
|
||||
if (rxDescCache.descUnused() == 0) {
|
||||
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
|
||||
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
|
||||
"fetching descriptors and stopping ticking\n");
|
||||
rxTick = false;
|
||||
DPRINTF(EthernetSM, "RXS: Fetching descriptors because none available\n");
|
||||
rxDescCache.fetchDescriptors();
|
||||
}
|
||||
return;
|
||||
|
|
@ -1159,15 +1270,18 @@ void
|
|||
IGbE::txWire()
|
||||
{
|
||||
if (txFifo.empty()) {
|
||||
txFifoTick = false;
|
||||
return;
|
||||
}
|
||||
|
||||
txTick = true;
|
||||
|
||||
if (etherInt->sendPacket(txFifo.front())) {
|
||||
DPRINTF(Ethernet, "TxFIFO: Successful transmit, bytes in fifo: %d\n",
|
||||
DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
|
||||
txFifo.avail());
|
||||
txFifo.pop();
|
||||
} else {
|
||||
// We'll get woken up when the packet ethTxDone() gets called
|
||||
txFifoTick = false;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -1180,34 +1294,133 @@ IGbE::tick()
|
|||
if (rxTick)
|
||||
rxStateMachine();
|
||||
|
||||
if (txTick) {
|
||||
if (txTick)
|
||||
txStateMachine();
|
||||
txWire();
|
||||
}
|
||||
|
||||
if (rxTick || txTick)
|
||||
if (txFifoTick)
|
||||
txWire();
|
||||
|
||||
|
||||
if (rxTick || txTick || txFifoTick)
|
||||
tickEvent.schedule(curTick + cycles(1));
|
||||
}
|
||||
|
||||
void
|
||||
IGbE::ethTxDone()
|
||||
{
|
||||
// restart the state machines if they are stopped
|
||||
// restart the tx state machines if they are stopped
|
||||
// fifo to send another packet
|
||||
// tx sm to put more data into the fifo
|
||||
txFifoTick = true;
|
||||
txTick = true;
|
||||
|
||||
restartClock();
|
||||
DPRINTF(Ethernet, "TxFIFO: Transmission complete\n");
|
||||
DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
|
||||
}
|
||||
|
||||
void
|
||||
IGbE::serialize(std::ostream &os)
|
||||
{
|
||||
panic("Need to implemenet\n");
|
||||
PciDev::serialize(os);
|
||||
|
||||
regs.serialize(os);
|
||||
SERIALIZE_SCALAR(eeOpBits);
|
||||
SERIALIZE_SCALAR(eeAddrBits);
|
||||
SERIALIZE_SCALAR(eeDataBits);
|
||||
SERIALIZE_SCALAR(eeOpcode);
|
||||
SERIALIZE_SCALAR(eeAddr);
|
||||
SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
|
||||
|
||||
rxFifo.serialize("rxfifo", os);
|
||||
txFifo.serialize("txfifo", os);
|
||||
|
||||
bool txPktExists = txPacket;
|
||||
SERIALIZE_SCALAR(txPktExists);
|
||||
if (txPktExists)
|
||||
txPacket->serialize("txpacket", os);
|
||||
|
||||
Tick rdtr_time = 0, radv_time = 0, tidv_time = 0, tadv_time = 0,
|
||||
inter_time = 0;
|
||||
|
||||
if (rdtrEvent.scheduled())
|
||||
rdtr_time = rdtrEvent.when();
|
||||
SERIALIZE_SCALAR(rdtr_time);
|
||||
|
||||
if (radvEvent.scheduled())
|
||||
radv_time = radvEvent.when();
|
||||
SERIALIZE_SCALAR(radv_time);
|
||||
|
||||
if (tidvEvent.scheduled())
|
||||
rdtr_time = tidvEvent.when();
|
||||
SERIALIZE_SCALAR(tidv_time);
|
||||
|
||||
if (tadvEvent.scheduled())
|
||||
rdtr_time = tadvEvent.when();
|
||||
SERIALIZE_SCALAR(tadv_time);
|
||||
|
||||
if (interEvent.scheduled())
|
||||
rdtr_time = interEvent.when();
|
||||
SERIALIZE_SCALAR(inter_time);
|
||||
|
||||
nameOut(os, csprintf("%s.TxDescCache", name()));
|
||||
txDescCache.serialize(os);
|
||||
|
||||
nameOut(os, csprintf("%s.RxDescCache", name()));
|
||||
rxDescCache.serialize(os);
|
||||
}
|
||||
|
||||
void
|
||||
IGbE::unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
panic("Need to implemenet\n");
|
||||
PciDev::unserialize(cp, section);
|
||||
|
||||
regs.unserialize(cp, section);
|
||||
UNSERIALIZE_SCALAR(eeOpBits);
|
||||
UNSERIALIZE_SCALAR(eeAddrBits);
|
||||
UNSERIALIZE_SCALAR(eeDataBits);
|
||||
UNSERIALIZE_SCALAR(eeOpcode);
|
||||
UNSERIALIZE_SCALAR(eeAddr);
|
||||
UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
|
||||
|
||||
rxFifo.unserialize("rxfifo", cp, section);
|
||||
txFifo.unserialize("txfifo", cp, section);
|
||||
|
||||
bool txPktExists;
|
||||
UNSERIALIZE_SCALAR(txPktExists);
|
||||
if (txPktExists) {
|
||||
txPacket = new EthPacketData(16384);
|
||||
txPacket->unserialize("txpacket", cp, section);
|
||||
}
|
||||
|
||||
rxTick = true;
|
||||
txTick = true;
|
||||
txFifoTick = true;
|
||||
|
||||
Tick rdtr_time, radv_time, tidv_time, tadv_time, inter_time;
|
||||
UNSERIALIZE_SCALAR(rdtr_time);
|
||||
UNSERIALIZE_SCALAR(radv_time);
|
||||
UNSERIALIZE_SCALAR(tidv_time);
|
||||
UNSERIALIZE_SCALAR(tadv_time);
|
||||
UNSERIALIZE_SCALAR(inter_time);
|
||||
|
||||
if (rdtr_time)
|
||||
rdtrEvent.schedule(rdtr_time);
|
||||
|
||||
if (radv_time)
|
||||
radvEvent.schedule(radv_time);
|
||||
|
||||
if (tidv_time)
|
||||
tidvEvent.schedule(tidv_time);
|
||||
|
||||
if (tadv_time)
|
||||
tadvEvent.schedule(tadv_time);
|
||||
|
||||
if (inter_time)
|
||||
interEvent.schedule(inter_time);
|
||||
|
||||
txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section));
|
||||
|
||||
rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -62,8 +62,10 @@ class IGbE : public PciDev
|
|||
uint8_t eeOpcode, eeAddr;
|
||||
uint16_t flash[iGbReg::EEPROM_SIZE];
|
||||
|
||||
// The drain event if we have one
|
||||
Event *drainEvent;
|
||||
|
||||
// cached parameters from params struct
|
||||
Tick tickRate;
|
||||
bool useFlowControl;
|
||||
|
||||
// packet fifos
|
||||
|
|
@ -76,24 +78,44 @@ class IGbE : public PciDev
|
|||
// Should to Rx/Tx State machine tick?
|
||||
bool rxTick;
|
||||
bool txTick;
|
||||
bool txFifoTick;
|
||||
|
||||
// Event and function to deal with RDTR timer expiring
|
||||
void rdtrProcess() { rxDescCache.writeback(0); postInterrupt(iGbReg::IT_RXT, true); }
|
||||
void rdtrProcess() {
|
||||
rxDescCache.writeback(0);
|
||||
DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n");
|
||||
postInterrupt(iGbReg::IT_RXT, true);
|
||||
}
|
||||
|
||||
//friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
|
||||
EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
|
||||
|
||||
// Event and function to deal with RADV timer expiring
|
||||
void radvProcess() { rxDescCache.writeback(0); postInterrupt(iGbReg::IT_RXT, true); }
|
||||
void radvProcess() {
|
||||
rxDescCache.writeback(0);
|
||||
DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n");
|
||||
postInterrupt(iGbReg::IT_RXT, true);
|
||||
}
|
||||
|
||||
//friend class EventWrapper<IGbE, &IGbE::radvProcess>;
|
||||
EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
|
||||
|
||||
// Event and function to deal with TADV timer expiring
|
||||
void tadvProcess() { postInterrupt(iGbReg::IT_TXDW, true); }
|
||||
void tadvProcess() {
|
||||
txDescCache.writeback(0);
|
||||
DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n");
|
||||
postInterrupt(iGbReg::IT_TXDW, true);
|
||||
}
|
||||
|
||||
//friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
|
||||
EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
|
||||
|
||||
// Event and function to deal with TIDV timer expiring
|
||||
void tidvProcess() { postInterrupt(iGbReg::IT_TXDW, true); };
|
||||
void tidvProcess() {
|
||||
txDescCache.writeback(0);
|
||||
DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n");
|
||||
postInterrupt(iGbReg::IT_TXDW, true);
|
||||
}
|
||||
//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
|
||||
EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
|
||||
|
||||
|
|
@ -131,8 +153,15 @@ class IGbE : public PciDev
|
|||
|
||||
Tick intClock() { return Clock::Int::ns * 1024; }
|
||||
|
||||
/** This function is used to restart the clock so it can handle things like
|
||||
* draining and resume in one place. */
|
||||
void restartClock();
|
||||
|
||||
/** Check if all the draining things that need to occur have occured and
|
||||
* handle the drain event if so.
|
||||
*/
|
||||
void checkDrain();
|
||||
|
||||
template<class T>
|
||||
class DescCache
|
||||
{
|
||||
|
|
@ -202,8 +231,10 @@ class IGbE : public PciDev
|
|||
*/
|
||||
void areaChanged()
|
||||
{
|
||||
if (usedCache.size() > 0 || unusedCache.size() > 0)
|
||||
if (usedCache.size() > 0 || curFetching || wbOut)
|
||||
panic("Descriptor Address, Length or Head changed. Bad\n");
|
||||
reset();
|
||||
|
||||
}
|
||||
|
||||
void writeback(Addr aMask)
|
||||
|
|
@ -229,7 +260,7 @@ class IGbE : public PciDev
|
|||
moreToWb = false;
|
||||
wbAlignment = aMask;
|
||||
|
||||
if (max_to_wb + curHead > descLen()) {
|
||||
if (max_to_wb + curHead >= descLen()) {
|
||||
max_to_wb = descLen() - curHead;
|
||||
moreToWb = true;
|
||||
// this is by definition aligned correctly
|
||||
|
|
@ -265,10 +296,14 @@ class IGbE : public PciDev
|
|||
*/
|
||||
void fetchDescriptors()
|
||||
{
|
||||
size_t max_to_fetch = descTail() - cachePnt;
|
||||
if (max_to_fetch < 0)
|
||||
size_t max_to_fetch;
|
||||
|
||||
if (descTail() >= cachePnt)
|
||||
max_to_fetch = descTail() - cachePnt;
|
||||
else
|
||||
max_to_fetch = descLen() - cachePnt;
|
||||
|
||||
|
||||
max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
|
||||
unusedCache.size()));
|
||||
|
||||
|
|
@ -311,8 +346,9 @@ class IGbE : public PciDev
|
|||
#endif
|
||||
|
||||
cachePnt += curFetching;
|
||||
if (cachePnt > descLen())
|
||||
cachePnt -= descLen();
|
||||
assert(cachePnt <= descLen());
|
||||
if (cachePnt == descLen())
|
||||
cachePnt = 0;
|
||||
|
||||
curFetching = 0;
|
||||
|
||||
|
|
@ -320,7 +356,7 @@ class IGbE : public PciDev
|
|||
oldCp, cachePnt);
|
||||
|
||||
enableSm();
|
||||
|
||||
igbe->checkDrain();
|
||||
}
|
||||
|
||||
EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
|
||||
|
|
@ -337,8 +373,8 @@ class IGbE : public PciDev
|
|||
curHead += wbOut;
|
||||
wbOut = 0;
|
||||
|
||||
if (curHead > descLen())
|
||||
curHead = 0;
|
||||
if (curHead >= descLen())
|
||||
curHead -= descLen();
|
||||
|
||||
// Update the head
|
||||
updateHead(curHead);
|
||||
|
|
@ -352,6 +388,7 @@ class IGbE : public PciDev
|
|||
writeback(wbAlignment);
|
||||
}
|
||||
intAfterWb();
|
||||
igbe->checkDrain();
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -390,6 +427,63 @@ class IGbE : public PciDev
|
|||
|
||||
usedCache.clear();
|
||||
unusedCache.clear();
|
||||
|
||||
cachePnt = 0;
|
||||
|
||||
}
|
||||
|
||||
virtual void serialize(std::ostream &os)
|
||||
{
|
||||
SERIALIZE_SCALAR(cachePnt);
|
||||
SERIALIZE_SCALAR(curFetching);
|
||||
SERIALIZE_SCALAR(wbOut);
|
||||
SERIALIZE_SCALAR(moreToWb);
|
||||
SERIALIZE_SCALAR(wbAlignment);
|
||||
|
||||
int usedCacheSize = usedCache.size();
|
||||
SERIALIZE_SCALAR(usedCacheSize);
|
||||
for(int x = 0; x < usedCacheSize; x++) {
|
||||
arrayParamOut(os, csprintf("usedCache_%d", x),
|
||||
(uint8_t*)usedCache[x],sizeof(T));
|
||||
}
|
||||
|
||||
int unusedCacheSize = unusedCache.size();
|
||||
SERIALIZE_SCALAR(unusedCacheSize);
|
||||
for(int x = 0; x < unusedCacheSize; x++) {
|
||||
arrayParamOut(os, csprintf("unusedCache_%d", x),
|
||||
(uint8_t*)unusedCache[x],sizeof(T));
|
||||
}
|
||||
}
|
||||
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
UNSERIALIZE_SCALAR(cachePnt);
|
||||
UNSERIALIZE_SCALAR(curFetching);
|
||||
UNSERIALIZE_SCALAR(wbOut);
|
||||
UNSERIALIZE_SCALAR(moreToWb);
|
||||
UNSERIALIZE_SCALAR(wbAlignment);
|
||||
|
||||
int usedCacheSize;
|
||||
UNSERIALIZE_SCALAR(usedCacheSize);
|
||||
T *temp;
|
||||
for(int x = 0; x < usedCacheSize; x++) {
|
||||
temp = new T;
|
||||
arrayParamIn(cp, section, csprintf("usedCache_%d", x),
|
||||
(uint8_t*)temp,sizeof(T));
|
||||
usedCache.push_back(temp);
|
||||
}
|
||||
|
||||
int unusedCacheSize;
|
||||
UNSERIALIZE_SCALAR(unusedCacheSize);
|
||||
for(int x = 0; x < unusedCacheSize; x++) {
|
||||
temp = new T;
|
||||
arrayParamIn(cp, section, csprintf("unusedCache_%d", x),
|
||||
(uint8_t*)temp,sizeof(T));
|
||||
unusedCache.push_back(temp);
|
||||
}
|
||||
}
|
||||
virtual bool hasOutstandingEvents() {
|
||||
return wbEvent.scheduled() || fetchEvent.scheduled();
|
||||
}
|
||||
|
||||
};
|
||||
|
|
@ -428,6 +522,10 @@ class IGbE : public PciDev
|
|||
|
||||
EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
|
||||
|
||||
virtual bool hasOutstandingEvents();
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
friend class RxDescCache;
|
||||
|
||||
|
|
@ -447,7 +545,6 @@ class IGbE : public PciDev
|
|||
bool pktDone;
|
||||
bool isTcp;
|
||||
bool pktWaiting;
|
||||
int hLen;
|
||||
|
||||
public:
|
||||
TxDescCache(IGbE *i, std::string n, int s);
|
||||
|
|
@ -475,6 +572,11 @@ class IGbE : public PciDev
|
|||
void pktComplete();
|
||||
EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
|
||||
|
||||
virtual bool hasOutstandingEvents();
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
};
|
||||
friend class TxDescCache;
|
||||
|
||||
|
|
@ -513,7 +615,8 @@ class IGbE : public PciDev
|
|||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
virtual unsigned int drain(Event *de);
|
||||
virtual void resume();
|
||||
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ struct TxDesc {
|
|||
|
||||
namespace TxdOp {
|
||||
const uint8_t TXD_CNXT = 0x0;
|
||||
const uint8_t TXD_DATA = 0x0;
|
||||
const uint8_t TXD_DATA = 0x1;
|
||||
|
||||
bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
|
||||
uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
|
||||
|
|
@ -220,6 +220,14 @@ struct Regs {
|
|||
bool operator==(T d) { return d == _data; }
|
||||
void operator()(T d) { _data = d; }
|
||||
Reg() { _data = 0; }
|
||||
void serialize(std::ostream &os)
|
||||
{
|
||||
SERIALIZE_SCALAR(_data);
|
||||
}
|
||||
void unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
UNSERIALIZE_SCALAR(_data);
|
||||
}
|
||||
};
|
||||
|
||||
struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register
|
||||
|
|
@ -595,6 +603,79 @@ struct Regs {
|
|||
ADD_FIELD32(smbclkout,30,1); // smb clock out
|
||||
};
|
||||
MANC manc;
|
||||
};
|
||||
|
||||
}; // iGbReg namespace
|
||||
void serialize(std::ostream &os)
|
||||
{
|
||||
paramOut(os, "ctrl", ctrl._data);
|
||||
paramOut(os, "sts", sts._data);
|
||||
paramOut(os, "eecd", eecd._data);
|
||||
paramOut(os, "eerd", eerd._data);
|
||||
paramOut(os, "ctrl_ext", ctrl_ext._data);
|
||||
paramOut(os, "mdic", mdic._data);
|
||||
paramOut(os, "icr", icr._data);
|
||||
SERIALIZE_SCALAR(imr);
|
||||
paramOut(os, "itr", itr._data);
|
||||
SERIALIZE_SCALAR(iam);
|
||||
paramOut(os, "rctl", rctl._data);
|
||||
paramOut(os, "fcttv", fcttv._data);
|
||||
paramOut(os, "tctl", tctl._data);
|
||||
paramOut(os, "pba", pba._data);
|
||||
paramOut(os, "fcrtl", fcrtl._data);
|
||||
paramOut(os, "fcrth", fcrth._data);
|
||||
paramOut(os, "rdba", rdba._data);
|
||||
paramOut(os, "rdlen", rdlen._data);
|
||||
paramOut(os, "rdh", rdh._data);
|
||||
paramOut(os, "rdt", rdt._data);
|
||||
paramOut(os, "rdtr", rdtr._data);
|
||||
paramOut(os, "rxdctl", rxdctl._data);
|
||||
paramOut(os, "radv", radv._data);
|
||||
paramOut(os, "rsrpd", rsrpd._data);
|
||||
paramOut(os, "tdba", tdba._data);
|
||||
paramOut(os, "tdlen", tdlen._data);
|
||||
paramOut(os, "tdh", tdh._data);
|
||||
paramOut(os, "tdt", tdt._data);
|
||||
paramOut(os, "tidv", tidv._data);
|
||||
paramOut(os, "txdctl", txdctl._data);
|
||||
paramOut(os, "tadv", tadv._data);
|
||||
paramOut(os, "rxcsum", rxcsum._data);
|
||||
paramOut(os, "manc", manc._data);
|
||||
}
|
||||
|
||||
void unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
paramIn(cp, section, "ctrl", ctrl._data);
|
||||
paramIn(cp, section, "sts", sts._data);
|
||||
paramIn(cp, section, "eecd", eecd._data);
|
||||
paramIn(cp, section, "eerd", eerd._data);
|
||||
paramIn(cp, section, "ctrl_ext", ctrl_ext._data);
|
||||
paramIn(cp, section, "mdic", mdic._data);
|
||||
paramIn(cp, section, "icr", icr._data);
|
||||
UNSERIALIZE_SCALAR(imr);
|
||||
paramIn(cp, section, "itr", itr._data);
|
||||
UNSERIALIZE_SCALAR(iam);
|
||||
paramIn(cp, section, "rctl", rctl._data);
|
||||
paramIn(cp, section, "fcttv", fcttv._data);
|
||||
paramIn(cp, section, "tctl", tctl._data);
|
||||
paramIn(cp, section, "pba", pba._data);
|
||||
paramIn(cp, section, "fcrtl", fcrtl._data);
|
||||
paramIn(cp, section, "fcrth", fcrth._data);
|
||||
paramIn(cp, section, "rdba", rdba._data);
|
||||
paramIn(cp, section, "rdlen", rdlen._data);
|
||||
paramIn(cp, section, "rdh", rdh._data);
|
||||
paramIn(cp, section, "rdt", rdt._data);
|
||||
paramIn(cp, section, "rdtr", rdtr._data);
|
||||
paramIn(cp, section, "rxdctl", rxdctl._data);
|
||||
paramIn(cp, section, "radv", radv._data);
|
||||
paramIn(cp, section, "rsrpd", rsrpd._data);
|
||||
paramIn(cp, section, "tdba", tdba._data);
|
||||
paramIn(cp, section, "tdlen", tdlen._data);
|
||||
paramIn(cp, section, "tdh", tdh._data);
|
||||
paramIn(cp, section, "tdt", tdt._data);
|
||||
paramIn(cp, section, "tidv", tidv._data);
|
||||
paramIn(cp, section, "txdctl", txdctl._data);
|
||||
paramIn(cp, section, "tadv", tadv._data);
|
||||
paramIn(cp, section, "rxcsum", rxcsum._data);
|
||||
paramIn(cp, section, "manc", manc._data);
|
||||
}
|
||||
};
|
||||
} // iGbReg namespace
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 104057 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179368 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 103746 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 65718 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179556 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_tick_rate 65601 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 10367 # Number of instructions simulated
|
||||
sim_insts 11001 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 10366 # Number of ticks simulated
|
||||
sim_ticks 11000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 10367 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 10367 # Number of instructions executed
|
||||
system.cpu.num_refs 2607 # Number of memory references
|
||||
system.cpu.numCycles 11001 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 11001 # Number of instructions executed
|
||||
system.cpu.num_refs 2760 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CASX FAIL: Passed
|
|||
CASX WORK: Passed
|
||||
LDTX: Passed
|
||||
LDTW: Passed
|
||||
STTW: Passed
|
||||
Done
|
||||
M5 Simulator System
|
||||
|
||||
|
|
@ -15,8 +16,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 6 2007 15:43:35
|
||||
M5 started Tue Mar 6 15:52:39 2007
|
||||
M5 compiled Mar 29 2007 15:29:35
|
||||
M5 started Thu Mar 29 15:39:35 2007
|
||||
M5 executing on zeep
|
||||
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
|
||||
Exiting @ tick 10366 because target called exit()
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 11000 because target called exit()
|
||||
|
|
|
|||
Loading…
Reference in a new issue