Make "test" set some condition codes.

It still needs to zero the overflow and carry flags to be correct.

--HG--
extra : convert_revision : 73cb3a55f7b4234389d9355f5ad45da6aaaa6c60
This commit is contained in:
Gabe Black 2007-07-17 15:35:34 -07:00
parent a6757095c3
commit c4004482a5

View file

@ -57,26 +57,26 @@ microcode = '''
def macroop TEST_M_R def macroop TEST_M_R
{ {
ld t1, ds, [scale, index, base], disp ld t1, ds, [scale, index, base], disp
and t0, t1, reg and t0, t1, reg, flags=(SF, ZF, PF)
}; };
def macroop TEST_P_R def macroop TEST_P_R
{ {
rdip t7 rdip t7
ld t1, ds, [scale, index, base], disp ld t1, ds, [scale, index, base], disp
and t0, t1, reg and t0, t1, reg, flags=(SF, ZF, PF)
}; };
def macroop TEST_R_R def macroop TEST_R_R
{ {
and t0, reg, regm and t0, reg, regm, flags=(SF, ZF, PF)
}; };
def macroop TEST_M_I def macroop TEST_M_I
{ {
ld t1, ds, [scale, index, base], disp ld t1, ds, [scale, index, base], disp
limm t2, imm limm t2, imm
and t0, t1, t2 and t0, t1, t2, flags=(SF, ZF, PF)
}; };
def macroop TEST_P_I def macroop TEST_P_I
@ -84,12 +84,12 @@ def macroop TEST_P_I
rdip t7 rdip t7
ld t1, ds, [scale, index, base], disp ld t1, ds, [scale, index, base], disp
limm t2, imm limm t2, imm
and t0, t1, t2 and t0, t1, t2, flags=(SF, ZF, PF)
}; };
def macroop TEST_R_I def macroop TEST_R_I
{ {
limm t1, imm limm t1, imm
and t0, reg, t1 and t0, reg, t1, flags=(SF, ZF, PF)
}; };
''' '''