Add the bus and connector objects to scons
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
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parent
4973a16b34
commit
c27c122afc
12 changed files with 58 additions and 38 deletions
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@ -88,11 +88,13 @@ base_sources = Split('''
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cpu/static_inst.cc
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cpu/sampler/sampler.cc
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mem/connector.cc
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mem/mem_object.cc
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mem/page_table.cc
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mem/physical.cc
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mem/port.cc
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mem/translating_port.cc
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mem/bus.cc
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python/pyconfig.cc
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python/embedded_py.cc
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@ -86,6 +86,15 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
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void
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SimpleCPU::init()
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{
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//Create Memory Ports (conect them up)
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Port *mem_dport = mem->getPort("");
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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Port *mem_iport = mem->getPort("");
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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BaseCPU::init();
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#if FULL_SYSTEM
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for (int i = 0; i < execContexts.size(); ++i) {
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@ -146,20 +155,11 @@ SimpleCPU::CpuPort::recvRetry()
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}
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SimpleCPU::SimpleCPU(Params *p)
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: BaseCPU(p), icachePort(this),
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: BaseCPU(p), mem(p->mem), icachePort(this),
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dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
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{
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_status = Idle;
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//Create Memory Ports (conect them up)
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Port *mem_dport = p->mem->getPort();
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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Port *mem_iport = p->mem->getPort();
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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#if FULL_SYSTEM
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cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
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#else
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@ -105,6 +105,7 @@ class SimpleCPU : public BaseCPU
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virtual Packet *recvRetry();
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};
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MemObject *mem;
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CpuPort icachePort;
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CpuPort dcachePort;
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@ -203,7 +203,7 @@ class PioDevice : public SimObject
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virtual ~PioDevice();
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virtual Port *getPort(std::string if_name)
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virtual Port *getPort(const std::string &if_name)
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{
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if (if_name == "pio")
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return pioPort;
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@ -223,7 +223,7 @@ class DmaDevice : public PioDevice
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DmaDevice(const std::string &name, Platform *p);
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virtual ~DmaDevice();
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virtual Port *getPort(std::string if_name)
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virtual Port *getPort(const std::string &if_name)
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{
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if (if_name == "pio")
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return pioPort;
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@ -137,7 +137,7 @@ class Bus : public MemObject
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public:
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/** A function used to return the port associated with this bus object. */
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virtual Port *getPort(const char *if_name)
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virtual Port *getPort(const std::string &if_name)
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{
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// if_name ignored? forced to be empty?
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int id = num_interfaces++;
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@ -145,7 +145,7 @@ class Bus : public MemObject
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return interfaces[id];
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}
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Bus(const std::string &n)
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: MemObject(n) {}
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: MemObject(n), num_interfaces(0) {}
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};
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@ -48,7 +48,7 @@ class MemObject : public SimObject
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public:
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/** Additional function to return the Port of a memory object. */
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virtual Port *getPort(const char *if_name = NULL) = 0;
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virtual Port *getPort(const std::string &if_name) = 0;
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};
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#endif //__MEM_MEM_OBJECT_HH__
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@ -69,8 +69,8 @@ PhysicalMemory::MemResponseEvent::description()
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return "Physical Memory Timing Access respnse event";
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}
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PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus)
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: MemObject(n), memPort(this), base_addr(0), pmem_addr(NULL)
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PhysicalMemory::PhysicalMemory(const string &n)
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: MemObject(n), base_addr(0), pmem_addr(NULL)
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{
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// Hardcoded to 128 MB for now.
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pmem_size = 1 << 27;
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@ -88,14 +88,6 @@ PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus)
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}
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page_ptr = 0;
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Port *peer_port;
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peer_port = bus->getPort();
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memPort.setPeer(peer_port);
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peer_port->setPeer(&memPort);
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}
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PhysicalMemory::~PhysicalMemory()
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@ -160,10 +152,13 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
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}
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Port *
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PhysicalMemory::getPort(const char *if_name)
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PhysicalMemory::getPort(const std::string &if_name)
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{
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if (if_name == NULL) {
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return new MemoryPort(this);
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if (if_name == "") {
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if (port != NULL)
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panic("PhysicalMemory::getPort: additional port requested to memory!");
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port = new MemoryPort(this);
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return port;
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} else {
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panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
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}
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@ -341,7 +336,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
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SimObjectParam<MemoryController *> mmu;
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#endif
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Param<Range<Addr> > range;
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SimObjectParam<MemObject*> bus;
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END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
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@ -351,8 +345,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
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#if FULL_SYSTEM
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INIT_PARAM(mmu, "Memory Controller"),
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#endif
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INIT_PARAM(range, "Device Address Range"),
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INIT_PARAM(bus, "bus object memory connects to")
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INIT_PARAM(range, "Device Address Range")
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END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
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@ -364,7 +357,7 @@ CREATE_SIM_OBJECT(PhysicalMemory)
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}
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#endif
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return new PhysicalMemory(getInstanceName(), bus);
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return new PhysicalMemory(getInstanceName());
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}
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REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)
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@ -69,9 +69,7 @@ class PhysicalMemory : public MemObject
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virtual int deviceBlockSize();
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};
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MemoryPort memPort;
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virtual Port * getPort(const char *if_name);
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virtual Port *getPort(const std::string &if_name);
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int numPorts;
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@ -96,6 +94,7 @@ class PhysicalMemory : public MemObject
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Addr base_addr;
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Addr pmem_size;
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uint8_t *pmem_addr;
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MemoryPort *port;
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int page_ptr;
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public:
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@ -103,13 +102,13 @@ class PhysicalMemory : public MemObject
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uint64_t size() { return pmem_size; }
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public:
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PhysicalMemory(const std::string &n, MemObject *bus);
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PhysicalMemory(const std::string &n);
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virtual ~PhysicalMemory();
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public:
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int deviceBlockSize();
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void getAddressRanges(AddrRangeList &rangeList, bool &owner);
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void virtual init() { memPort.sendStatusChange(Port::RangeChange); }
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void virtual init() { port->sendStatusChange(Port::RangeChange); }
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// fast back-door memory access for vtophys(), remote gdb, etc.
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// uint64_t phys_read_qword(Addr addr) const;
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@ -5,6 +5,5 @@ class PhysicalMemory(Memory):
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type = 'PhysicalMemory'
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range = Param.AddrRange("Device Address")
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file = Param.String('', "memory mapped file")
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bus = Param.MemObject("Bus to attach to")
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if build_env['FULL_SYSTEM']:
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mmu = Param.MemoryController(Parent.any, "Memory Controller")
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@ -355,6 +355,10 @@ main(int argc, char **argv)
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echoCommandLine(argc, argv, *outputStream);
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ParamContext::showAllContexts(*configStream);
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// Any objects that can't connect themselves until after construction should
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// do so now
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SimObject::connectAll();
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// Do a second pass to finish initializing the sim objects
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SimObject::initAll();
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@ -87,6 +87,11 @@ SimObject::SimObject(const string &_name)
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simObjectList.push_back(this);
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}
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void
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SimObject::connect()
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{
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}
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void
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SimObject::init()
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{
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@ -150,6 +155,21 @@ SimObject::regAllStats()
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Stats::registerResetCallback(&StatResetCB);
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}
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//
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// static function: call connect() on all SimObjects.
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//
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void
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SimObject::connectAll()
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{
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SimObjectList::iterator i = simObjectList.begin();
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SimObjectList::iterator end = simObjectList.end();
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for (; i != end; ++i) {
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SimObject *obj = *i;
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obj->connect();
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}
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}
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//
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// static function: call init() on all SimObjects.
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//
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@ -78,7 +78,9 @@ class SimObject : public Serializable, protected StartupCallback
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// initialization pass of all objects.
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// Gets invoked after construction, before unserialize.
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virtual void init();
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virtual void connect();
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static void initAll();
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static void connectAll();
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// register statistics for this object
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virtual void regStats();
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