Add the bus and connector objects to scons

change getPort parameter from char* to string
Add an extra phase between construction and init called connect

SConscript:
    Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    the connection to memory shouldn't be made until we know the memory
    object exists (e.g. after construction)
dev/io_device.hh:
    change to const string
mem/bus.hh:
    change getPort parameter from char* to string
    initialize num_interfaces
mem/mem_object.hh:
    change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
    change getPort parameter from char* to string
    get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
    get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Add an extra phase between construction and init called connect

--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9

SConscript

@@ -88,11 +88,13 @@ base_sources = Split('''
 	cpu/static_inst.cc
         cpu/sampler/sampler.cc
 
+        mem/connector.cc
         mem/mem_object.cc
         mem/page_table.cc
         mem/physical.cc
         mem/port.cc
         mem/translating_port.cc
+        mem/bus.cc
 
         python/pyconfig.cc
         python/embedded_py.cc

cpu/simple/cpu.cc

@@ -86,6 +86,15 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
 void
 SimpleCPU::init()
 {
+    //Create Memory Ports (conect them up)
+    Port *mem_dport = mem->getPort("");
+    dcachePort.setPeer(mem_dport);
+    mem_dport->setPeer(&dcachePort);
+
+    Port *mem_iport = mem->getPort("");
+    icachePort.setPeer(mem_iport);
+    mem_iport->setPeer(&icachePort);
+
     BaseCPU::init();
 #if FULL_SYSTEM
     for (int i = 0; i < execContexts.size(); ++i) {
@@ -146,20 +155,11 @@ SimpleCPU::CpuPort::recvRetry()
 }
 
 SimpleCPU::SimpleCPU(Params *p)
-    : BaseCPU(p), icachePort(this),
+    : BaseCPU(p), mem(p->mem), icachePort(this),
       dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
 {
     _status = Idle;
 
-    //Create Memory Ports (conect them up)
-    Port *mem_dport = p->mem->getPort();
-    dcachePort.setPeer(mem_dport);
-    mem_dport->setPeer(&dcachePort);
-
-    Port *mem_iport = p->mem->getPort();
-    icachePort.setPeer(mem_iport);
-    mem_iport->setPeer(&icachePort);
-
 #if FULL_SYSTEM
     cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 #else

cpu/simple/cpu.hh

@@ -105,6 +105,7 @@ class SimpleCPU : public BaseCPU
         virtual Packet *recvRetry();
     };
 
+    MemObject *mem;
     CpuPort icachePort;
     CpuPort dcachePort;
 

dev/io_device.hh

@@ -203,7 +203,7 @@ class PioDevice : public SimObject
 
     virtual ~PioDevice();
 
-    virtual Port *getPort(std::string if_name)
+    virtual Port *getPort(const std::string &if_name)
     {
         if (if_name == "pio")
             return pioPort;
@@ -223,7 +223,7 @@ class DmaDevice : public PioDevice
     DmaDevice(const std::string &name, Platform *p);
     virtual ~DmaDevice();
 
-    virtual Port *getPort(std::string if_name)
+    virtual Port *getPort(const std::string &if_name)
     {
         if (if_name == "pio")
             return pioPort;

mem/bus.hh

@@ -137,7 +137,7 @@ class Bus : public MemObject
   public:
 
     /** A function used to return the port associated with this bus object. */
-    virtual Port *getPort(const char *if_name)
+    virtual Port *getPort(const std::string &if_name)
     {
         // if_name ignored?  forced to be empty?
         int id = num_interfaces++;
@@ -145,7 +145,7 @@ class Bus : public MemObject
         return interfaces[id];
     }
     Bus(const std::string &n)
-        : MemObject(n) {}
+        : MemObject(n), num_interfaces(0) {}
 
 };
 

mem/mem_object.hh

@@ -48,7 +48,7 @@ class MemObject : public SimObject
 
   public:
     /** Additional function to return the Port of a memory object. */
-    virtual Port *getPort(const char *if_name = NULL) = 0;
+    virtual Port *getPort(const std::string &if_name) = 0;
 };
 
 #endif //__MEM_MEM_OBJECT_HH__

mem/physical.cc

@@ -69,8 +69,8 @@ PhysicalMemory::MemResponseEvent::description()
     return "Physical Memory Timing Access respnse event";
 }
 
-PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus)
+PhysicalMemory::PhysicalMemory(const string &n)
-    : MemObject(n), memPort(this), base_addr(0), pmem_addr(NULL)
+    : MemObject(n), base_addr(0), pmem_addr(NULL)
 {
     // Hardcoded to 128 MB for now.
     pmem_size = 1 << 27;
@@ -88,14 +88,6 @@ PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus)
     }
 
     page_ptr = 0;
-
-    Port *peer_port;
-    peer_port = bus->getPort();
-    memPort.setPeer(peer_port);
-    peer_port->setPeer(&memPort);
-
-
-
 }
 
 PhysicalMemory::~PhysicalMemory()
@@ -160,10 +152,13 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
 }
 
 Port *
-PhysicalMemory::getPort(const char *if_name)
+PhysicalMemory::getPort(const std::string &if_name)
 {
-    if (if_name == NULL) {
+    if (if_name == "") {
-        return new MemoryPort(this);
+        if (port != NULL)
+           panic("PhysicalMemory::getPort: additional port requested to memory!");
+        port = new MemoryPort(this);
+        return port;
     } else {
         panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
     }
@@ -341,7 +336,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
     SimObjectParam<MemoryController *> mmu;
 #endif
     Param<Range<Addr> > range;
-    SimObjectParam<MemObject*> bus;
 
 END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
 
@@ -351,8 +345,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
 #if FULL_SYSTEM
     INIT_PARAM(mmu, "Memory Controller"),
 #endif
-    INIT_PARAM(range, "Device Address Range"),
+    INIT_PARAM(range, "Device Address Range")
-    INIT_PARAM(bus, "bus object memory connects to")
 
 END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
 
@@ -364,7 +357,7 @@ CREATE_SIM_OBJECT(PhysicalMemory)
     }
 #endif
 
-    return new PhysicalMemory(getInstanceName(), bus);
+    return new PhysicalMemory(getInstanceName());
 }
 
 REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)

mem/physical.hh

@@ -69,9 +69,7 @@ class PhysicalMemory : public MemObject
         virtual int deviceBlockSize();
     };
 
-    MemoryPort memPort;
+    virtual Port *getPort(const std::string &if_name);
-
-    virtual Port * getPort(const char *if_name);
 
     int numPorts;
 
@@ -96,6 +94,7 @@ class PhysicalMemory : public MemObject
     Addr base_addr;
     Addr pmem_size;
     uint8_t *pmem_addr;
+    MemoryPort *port;
     int page_ptr;
 
   public:
@@ -103,13 +102,13 @@ class PhysicalMemory : public MemObject
     uint64_t size() { return pmem_size; }
 
   public:
-    PhysicalMemory(const std::string &n, MemObject *bus);
+    PhysicalMemory(const std::string &n);
     virtual ~PhysicalMemory();
 
   public:
     int deviceBlockSize();
     void getAddressRanges(AddrRangeList &rangeList, bool &owner);
-    void virtual init() { memPort.sendStatusChange(Port::RangeChange); }
+    void virtual init() { port->sendStatusChange(Port::RangeChange); }
 
     // fast back-door memory access for vtophys(), remote gdb, etc.
     // uint64_t phys_read_qword(Addr addr) const;

python/m5/objects/PhysicalMemory.py

@@ -5,6 +5,5 @@ class PhysicalMemory(Memory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
-    bus = Param.MemObject("Bus to attach to")
     if build_env['FULL_SYSTEM']:
         mmu = Param.MemoryController(Parent.any, "Memory Controller")

sim/main.cc

@@ -355,6 +355,10 @@ main(int argc, char **argv)
     echoCommandLine(argc, argv, *outputStream);
     ParamContext::showAllContexts(*configStream);
 
+    // Any objects that can't connect themselves until after construction should
+    // do so now
+    SimObject::connectAll();
+
     // Do a second pass to finish initializing the sim objects
     SimObject::initAll();
 

sim/sim_object.cc

@@ -87,6 +87,11 @@ SimObject::SimObject(const string &_name)
     simObjectList.push_back(this);
 }
 
+void
+SimObject::connect()
+{
+}
+
 void
 SimObject::init()
 {
@@ -150,6 +155,21 @@ SimObject::regAllStats()
     Stats::registerResetCallback(&StatResetCB);
 }
 
+//
+// static function: call connect() on all SimObjects.
+//
+void
+SimObject::connectAll()
+{
+    SimObjectList::iterator i = simObjectList.begin();
+    SimObjectList::iterator end = simObjectList.end();
+
+    for (; i != end; ++i) {
+        SimObject *obj = *i;
+        obj->connect();
+    }
+}
+
 //
 // static function: call init() on all SimObjects.
 //

sim/sim_object.hh

@@ -78,7 +78,9 @@ class SimObject : public Serializable, protected StartupCallback
     // initialization pass of all objects.
     // Gets invoked after construction, before unserialize.
     virtual void init();
+    virtual void connect();
     static void initAll();
+    static void connectAll();
 
     // register statistics for this object
     virtual void regStats();