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Another pass at the prefetcher. Now it works with both miss and access reference streams.

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Reworked how it is instattiated and how it communicates with other cache objects.

SConscript:
    Compile all the prefetcher files
objects/BaseCache.mpy:
    Add parameters for prefetcher

--HG--
extra : convert_revision : 2faa81c17673420ffae72a50a27e310d4c0f4135
This commit is contained in:
Ron Dreslinski 2005-04-01 19:26:44 -05:00
parent 13608a9b85
commit c21bf8e7ae
2 changed files with 11 additions and 3 deletions
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5
SConscript
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@ -164,7 +164,10 @@ base_sources = Split('''
mem/cache/miss/miss_queue.cc mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc mem/cache/miss/mshr_queue.cc
mem/cache/miss/prefetcher.cc mem/cache/prefetch/base_prefetcher.cc
mem/cache/prefetch/prefetcher.cc
mem/cache/prefetch/stride_prefetcher.cc
mem/cache/prefetch/tagged_prefetcher.cc
mem/cache/tags/base_tags.cc mem/cache/tags/base_tags.cc
mem/cache/tags/cache_tags.cc mem/cache/tags/cache_tags.cc
mem/cache/tags/fa_lru.cc mem/cache/tags/fa_lru.cc

9
objects/BaseCache.mpy
View file

@ -36,7 +36,12 @@ simobj BaseCache(BaseMem):
two_queue = Param.Bool(False, two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement") "whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers") write_buffers = Param.Int(8, "number of write buffers")
use_prefetcher = Param.Bool(False, prefetch_miss = Param.Bool(False,
"wheter you are using the hardware prefetcher") "wheter you are using the hardware prefetcher from Miss stream")
prefetch_access = Param.Bool(False,
"wheter you are using the hardware prefetcher from Access stream")
prefetcher_size = Param.Int(100, prefetcher_size = Param.Int(100,
"Number of entries in the harware prefetch queue") "Number of entries in the harware prefetch queue")
prefetch_past_page = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")