Removing of old code and adding in new comments.
src/cpu/base_dyn_inst.cc: Clean up old functions, comments. src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_params.hh: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/rename_impl.hh: src/cpu/ozone/lsq_unit.hh: src/cpu/ozone/lsq_unit_impl.hh: Remove old commented code. src/cpu/o3/fetch.hh: Remove old commented code, add in comments. src/cpu/o3/inst_queue_impl.hh: Move comment to better place. src/cpu/o3/lsq_unit.hh: Remove old commented code, add in new comments. src/cpu/o3/lsq_unit_impl.hh: Remove old commented code, rename variable. --HG-- extra : convert_revision : 8e79af9b4d3b3bdd0f55e4747c6ab64c9ad2f571
This commit is contained in:
parent
4b732e43a6
commit
c14c78fa3e
16 changed files with 60 additions and 185 deletions
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@ -137,8 +137,7 @@ BaseDynInst<Impl>::initVars()
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// Also make this a parameter, or perhaps get it from xc or cpu.
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asid = 0;
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// Initialize the fault to be unimplemented opcode.
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// fault = new UnimplementedOpcodeFault;
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// Initialize the fault to be NoFault.
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fault = NoFault;
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++instcount;
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@ -346,67 +345,6 @@ BaseDynInst<Impl>::dump(std::string &outstring)
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outstring = s.str();
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}
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#if 0
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template <class Impl>
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Fault
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BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
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{
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Fault fault;
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// check alignments, even speculative this test should always pass
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if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
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for (int i = 0; i < nbytes; i++)
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((char *) p)[i] = 0;
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// I added the following because according to the comment above,
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// we should never get here. The comment lies
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#if 0
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panic("unaligned access. Cycle = %n", curTick);
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#endif
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return NoFault;
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}
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MemReqPtr req = new MemReq(addr, thread, nbytes);
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switch(cmd) {
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case Read:
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fault = spec_mem->read(req, (uint8_t *)p);
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break;
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case Write:
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fault = spec_mem->write(req, (uint8_t *)p);
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if (fault != NoFault)
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break;
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specMemWrite = true;
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storeSize = nbytes;
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switch(nbytes) {
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case sizeof(uint8_t):
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*(uint8_t)&storeData = (uint8_t *)p;
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break;
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case sizeof(uint16_t):
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*(uint16_t)&storeData = (uint16_t *)p;
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break;
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case sizeof(uint32_t):
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*(uint32_t)&storeData = (uint32_t *)p;
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break;
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case sizeof(uint64_t):
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*(uint64_t)&storeData = (uint64_t *)p;
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break;
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}
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break;
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default:
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fault = genMachineCheckFault();
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break;
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}
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trace_mem(fault, cmd, addr, p, nbytes);
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return fault;
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}
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#endif
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template <class Impl>
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void
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BaseDynInst<Impl>::markSrcRegReady()
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@ -58,7 +58,6 @@ SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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#else
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SimObjectVectorParam<Process *> workload;
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//SimObjectParam<PageTable *> page_table;
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#endif // FULL_SYSTEM
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SimObjectParam<MemObject *> mem;
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@ -165,7 +164,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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INIT_PARAM(dtb, "Data translation buffer"),
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#else
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INIT_PARAM(workload, "Processes to run"),
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// INIT_PARAM(page_table, "Page table"),
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#endif // FULL_SYSTEM
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INIT_PARAM(mem, "Memory"),
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@ -309,7 +307,6 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
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params->dtb = dtb;
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#else
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params->workload = workload;
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// params->pTable = page_table;
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#endif // FULL_SYSTEM
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params->mem = mem;
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@ -58,9 +58,6 @@ class AlphaSimpleParams : public BaseFullCPU::Params
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Process *process;
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#endif // FULL_SYSTEM
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//Page Table
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// PageTable *pTable;
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MemObject *mem;
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BaseCPU *checker;
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@ -490,11 +490,6 @@ class FullO3CPU : public BaseFullCPU
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/** Pointers to all of the threads in the CPU. */
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std::vector<Thread *> thread;
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#if 0
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/** Page table pointer. */
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PageTable *pTable;
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#endif
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/** Pointer to the icache interface. */
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MemInterface *icacheInterface;
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/** Pointer to the dcache interface. */
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@ -69,29 +69,41 @@ class DefaultFetch
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typedef TheISA::MachInst MachInst;
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typedef TheISA::ExtMachInst ExtMachInst;
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/** IcachePort class for DefaultFetch. Handles doing the
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* communication with the cache/memory.
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*/
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class IcachePort : public Port
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{
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protected:
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/** Pointer to fetch. */
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DefaultFetch<Impl> *fetch;
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public:
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/** Default constructor. */
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IcachePort(DefaultFetch<Impl> *_fetch)
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: Port(_fetch->name() + "-iport"), fetch(_fetch)
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{ }
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protected:
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/** Atomic version of receive. Panics. */
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virtual Tick recvAtomic(PacketPtr pkt);
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/** Functional version of receive. Panics. */
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virtual void recvFunctional(PacketPtr pkt);
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/** Receives status change. Other than range changing, panics. */
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virtual void recvStatusChange(Status status);
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/** Returns the address ranges of this device. */
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop)
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{ resp.clear(); snoop.clear(); }
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/** Timing version of receive. Handles setting fetch to the
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* proper status to start fetching. */
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virtual bool recvTiming(PacketPtr pkt);
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/** Handles doing a retry of a failed fetch. */
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virtual void recvRetry();
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};
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@ -163,9 +175,6 @@ class DefaultFetch
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/** Sets pointer to time buffer used to communicate to the next stage. */
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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/** Sets pointer to page table. */
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// void setPageTable(PageTable *pt_ptr);
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/** Initialize stage. */
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void initStage();
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@ -268,6 +277,7 @@ class DefaultFetch
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}
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private:
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/** Handles retrying the fetch access. */
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void recvRetry();
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/** Returns the appropriate thread to fetch, given the fetch policy. */
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@ -406,11 +416,6 @@ class DefaultFetch
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/** Records if fetch is switched out. */
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bool switchedOut;
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#if !FULL_SYSTEM
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/** Page table pointer. */
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// PageTable *pTable;
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#endif
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// @todo: Consider making these vectors and tracking on a per thread basis.
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/** Stat for total number of cycles stalled due to an icache miss. */
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Stats::Scalar<> icacheStallCycles;
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@ -322,18 +322,6 @@ DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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toDecode = fetchQueue->getWire(0);
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}
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#if 0
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template<class Impl>
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void
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DefaultFetch<Impl>::setPageTable(PageTable *pt_ptr)
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{
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DPRINTF(Fetch, "Setting the page table pointer.\n");
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#if !FULL_SYSTEM
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pTable = pt_ptr;
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#endif
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}
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#endif
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template<class Impl>
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void
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DefaultFetch<Impl>::initStage()
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@ -381,8 +369,6 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
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fetchStatus[tid] = IcacheAccessComplete;
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}
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// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
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// Reset the mem req to NULL.
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delete pkt->req;
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delete pkt;
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@ -594,8 +580,6 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
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if (fetchStatus[tid] == IcacheWaitResponse) {
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DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
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tid);
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// Should I delete this here or when it comes back from the cache?
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// delete memReq[tid];
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memReq[tid] = NULL;
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}
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@ -155,9 +155,6 @@ class DefaultIEW
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/** Returns if IEW is switched out. */
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bool isSwitchedOut() { return switchedOut; }
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/** Sets page table pointer within LSQ. */
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// void setPageTable(PageTable *pt_ptr);
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/** Squashes instructions in IEW for a specific thread. */
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void squash(unsigned tid);
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@ -370,15 +370,6 @@ DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
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scoreboard = sb_ptr;
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}
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#if 0
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template<class Impl>
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void
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DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
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{
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ldstQueue.setPageTable(pt_ptr);
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}
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#endif
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template <class Impl>
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void
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DefaultIEW<Impl>::switchOut()
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@ -1182,9 +1173,8 @@ DefaultIEW<Impl>::executeInsts()
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fetchRedirect[tid] = false;
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}
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#if 0
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printAvailableInsts();
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#endif
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// Uncomment this if you want to see all available instructions.
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// printAvailableInsts();
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// Execute/writeback any instructions that are available.
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int insts_to_execute = fromIssue->size;
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@ -1349,8 +1339,8 @@ DefaultIEW<Impl>::writebackInsts()
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DynInstPtr inst = toCommit->insts[inst_num];
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int tid = inst->threadNumber;
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DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
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inst->readPC());
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DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
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inst->seqNum, inst->readPC());
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iewInstsToCommit[tid]++;
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@ -1240,11 +1240,11 @@ template <class Impl>
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int
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InstructionQueue<Impl>::countInsts()
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{
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#if 0
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//ksewell:This works but definitely could use a cleaner write
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//with a more intuitive way of counting. Right now it's
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//just brute force ....
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#if 0
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// Change the #if if you want to use this method.
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int total_insts = 0;
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for (int i = 0; i < numThreads; ++i) {
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@ -36,10 +36,8 @@
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#include "config/full_system.hh"
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#include "cpu/inst_seq.hh"
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//#include "cpu/o3/cpu_policy.hh"
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#include "cpu/o3/lsq_unit.hh"
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#include "mem/port.hh"
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//#include "mem/page_table.hh"
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#include "sim/sim_object.hh"
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template <class Impl>
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@ -70,8 +68,6 @@ class LSQ {
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void setCPU(FullCPU *cpu_ptr);
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/** Sets the IEW stage pointer. */
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void setIEW(IEW *iew_ptr);
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/** Sets the page table pointer. */
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// void setPageTable(PageTable *pt_ptr);
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/** Switches out the LSQ. */
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void switchOut();
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/** Takes over execution from another CPU's thread. */
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@ -281,9 +277,6 @@ class LSQ {
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/** The IEW stage pointer. */
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IEW *iewStage;
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/** The pointer to the page table. */
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// PageTable *pTable;
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/** List of Active Threads in System. */
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std::list<unsigned> *activeThreads;
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@ -136,17 +136,6 @@ LSQ<Impl>::setIEW(IEW *iew_ptr)
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}
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}
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#if 0
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template<class Impl>
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void
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LSQ<Impl>::setPageTable(PageTable *pt_ptr)
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{
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for (int tid=0; tid < numThreads; tid++) {
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thread[tid].setPageTable(pt_ptr);
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}
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}
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#endif
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template <class Impl>
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void
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LSQ<Impl>::switchOut()
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@ -42,9 +42,6 @@
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#include "cpu/inst_seq.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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//#include "mem/page_table.hh"
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//#include "sim/debug.hh"
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//#include "sim/sim_object.hh"
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/**
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* Class that implements the actual LQ and SQ for each specific
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@ -87,9 +84,6 @@ class LSQUnit {
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void setIEW(IEW *iew_ptr)
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{ iewStage = iew_ptr; }
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/** Sets the page table pointer. */
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// void setPageTable(PageTable *pt_ptr);
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/** Switches out LSQ unit. */
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void switchOut();
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@ -211,8 +205,10 @@ class LSQUnit {
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!isStoreBlocked; }
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private:
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/** Writes back the instruction, sending it to IEW. */
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void writeback(DynInstPtr &inst, PacketPtr pkt);
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/** Handles completing the send of a store to memory. */
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void storePostSend(Packet *pkt);
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/** Completes the store at the specified index. */
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@ -241,55 +237,75 @@ class LSQUnit {
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/** Pointer to the IEW stage. */
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IEW *iewStage;
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/** Pointer to memory object. */
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MemObject *mem;
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/** DcachePort class for this LSQ Unit. Handles doing the
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* communication with the cache/memory.
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* @todo: Needs to be moved to the LSQ level and have some sort
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* of arbitration.
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*/
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class DcachePort : public Port
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{
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protected:
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/** Pointer to CPU. */
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FullCPU *cpu;
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/** Pointer to LSQ. */
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LSQUnit *lsq;
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public:
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/** Default constructor. */
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DcachePort(FullCPU *_cpu, LSQUnit *_lsq)
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: Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
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{ }
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protected:
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/** Atomic version of receive. Panics. */
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virtual Tick recvAtomic(PacketPtr pkt);
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/** Functional version of receive. Panics. */
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virtual void recvFunctional(PacketPtr pkt);
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/** Receives status change. Other than range changing, panics. */
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virtual void recvStatusChange(Status status);
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/** Returns the address ranges of this device. */
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop)
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{ resp.clear(); snoop.clear(); }
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/** Timing version of receive. Handles writing back and
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* completing the load or store that has returned from
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* memory. */
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virtual bool recvTiming(PacketPtr pkt);
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/** Handles doing a retry of the previous send. */
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virtual void recvRetry();
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};
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/** Pointer to the D-cache. */
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DcachePort *dcachePort;
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/** Derived class to hold any sender state the LSQ needs. */
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class LSQSenderState : public Packet::SenderState
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{
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public:
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/** Default constructor. */
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LSQSenderState()
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: noWB(false)
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{ }
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// protected:
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/** Instruction who initiated the access to memory. */
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DynInstPtr inst;
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/** Whether or not it is a load. */
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bool isLoad;
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/** The LQ/SQ index of the instruction. */
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int idx;
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/** Whether or not the instruction will need to writeback. */
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bool noWB;
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};
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/** Pointer to the page table. */
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// PageTable *pTable;
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/** Writeback event, specifically for when stores forward data to loads. */
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class WritebackEvent : public Event {
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public:
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/** Constructs a writeback event. */
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@ -302,8 +318,10 @@ class LSQUnit {
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const char *description();
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private:
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/** Instruction whose results are being written back. */
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DynInstPtr inst;
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/** The packet that would have been sent to memory. */
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PacketPtr pkt;
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/** The pointer to the LSQ unit that issued the store. */
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@ -404,8 +422,10 @@ class LSQUnit {
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/** The index of the above store. */
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int stallingLoadIdx;
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PacketPtr sendingPkt;
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/** The packet that needs to be retried. */
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PacketPtr retryPkt;
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/** Whehter or not a store is blocked due to the memory system. */
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bool isStoreBlocked;
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/** Whether or not a load is blocked due to the memory system. */
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@ -66,7 +66,7 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
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LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
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DynInstPtr inst = state->inst;
|
||||
DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
|
||||
// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
|
||||
DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
|
||||
|
||||
//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
|
||||
|
||||
|
@ -209,16 +209,6 @@ LSQUnit<Impl>::clearSQ()
|
|||
storeQueue.clear();
|
||||
}
|
||||
|
||||
#if 0
|
||||
template<class Impl>
|
||||
void
|
||||
LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
|
||||
{
|
||||
DPRINTF(LSQUnit, "Setting the page table pointer.\n");
|
||||
pTable = pt_ptr;
|
||||
}
|
||||
#endif
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
LSQUnit<Impl>::switchOut()
|
||||
|
@ -628,8 +618,8 @@ LSQUnit<Impl>::writebackStores()
|
|||
// Need to handle becoming blocked on a store.
|
||||
isStoreBlocked = true;
|
||||
|
||||
assert(sendingPkt == NULL);
|
||||
sendingPkt = data_pkt;
|
||||
assert(retryPkt == NULL);
|
||||
retryPkt = data_pkt;
|
||||
} else {
|
||||
storePostSend(data_pkt);
|
||||
}
|
||||
|
@ -858,11 +848,11 @@ template <class Impl>
|
|||
void
|
||||
LSQUnit<Impl>::recvRetry()
|
||||
{
|
||||
assert(sendingPkt != NULL);
|
||||
|
||||
if (isStoreBlocked) {
|
||||
if (dcachePort->sendTiming(sendingPkt)) {
|
||||
storePostSend(sendingPkt);
|
||||
assert(retryPkt != NULL);
|
||||
|
||||
if (dcachePort->sendTiming(retryPkt)) {
|
||||
storePostSend(retryPkt);
|
||||
sendingPkt = NULL;
|
||||
isStoreBlocked = false;
|
||||
} else {
|
||||
|
|
|
@ -327,18 +327,9 @@ DefaultRename<Impl>::squash(unsigned tid)
|
|||
if (renameStatus[tid] == Blocked ||
|
||||
renameStatus[tid] == Unblocking ||
|
||||
renameStatus[tid] == SerializeStall) {
|
||||
#if 0
|
||||
// In syscall emulation, we can have both a block and a squash due
|
||||
// to a syscall in the same cycle. This would cause both signals to
|
||||
// be high. This shouldn't happen in full system.
|
||||
if (toDecode->renameBlock[tid]) {
|
||||
toDecode->renameBlock[tid] = 0;
|
||||
} else {
|
||||
toDecode->renameUnblock[tid] = 1;
|
||||
}
|
||||
#else
|
||||
|
||||
toDecode->renameUnblock[tid] = 1;
|
||||
#endif
|
||||
|
||||
serializeInst[tid] = NULL;
|
||||
}
|
||||
|
||||
|
|
|
@ -114,9 +114,6 @@ class OzoneLSQ {
|
|||
void setBE(BackEnd *be_ptr)
|
||||
{ be = be_ptr; }
|
||||
|
||||
/** Sets the page table pointer. */
|
||||
void setPageTable(PageTable *pt_ptr);
|
||||
|
||||
/** Ticks the LSQ unit, which in this case only resets the number of
|
||||
* used cache ports.
|
||||
* @todo: Move the number of used ports up to the LSQ level so it can
|
||||
|
|
|
@ -123,14 +123,6 @@ OzoneLSQ<Impl>::clearSQ()
|
|||
storeQueue.clear();
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
OzoneLSQ<Impl>::setPageTable(PageTable *pt_ptr)
|
||||
{
|
||||
DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
|
||||
pTable = pt_ptr;
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
OzoneLSQ<Impl>::resizeLQ(unsigned size)
|
||||
|
|
Loading…
Reference in a new issue