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arm: Squash after returning from exceptions in v7

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Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
This commit is contained in:
Mitch Hayenga 2016-02-29 19:13:13 -06:00
parent aa674268e9
commit c0d19391d4
3 changed files with 8 additions and 5 deletions
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6
src/arch/arm/isa/insts/data.isa
View file

@ -273,10 +273,12 @@ let {{
'''
buildImmDataInst(mnem + 's', code, flagType,
suffix = "ImmPclr", buildCc = False,
instFlags = ["IsSerializeAfter","IsNonSpeculative"])
instFlags = ["IsSerializeAfter","IsNonSpeculative",
"IsSquashAfter"])
buildRegDataInst(mnem + 's', code, flagType,
suffix = "RegPclr", buildCc = False,
instFlags = ["IsSerializeAfter","IsNonSpeculative"])
instFlags = ["IsSerializeAfter","IsNonSpeculative",
"IsSquashAfter"])
buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")

4
src/arch/arm/isa/insts/macromem.isa
View file

@ -124,7 +124,7 @@ let {{
'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest},
['IsMicroop','IsNonSpeculative',
'IsSerializeAfter'])
'IsSerializeAfter', 'IsSquashAfter'])
microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
@ -668,7 +668,7 @@ let {{
{'code': microRetUopCode % 'URb',
'predicate_test': predicateTest},
['IsMicroop', 'IsNonSpeculative',
'IsSerializeAfter'])
'IsSerializeAfter', 'IsSquashAfter'])
setPCCPSRDecl = '''
CPSR cpsrOrCondCodes = URc;

3
src/arch/arm/isa/insts/misc.isa
View file

@ -130,7 +130,8 @@ let {{
eretIop = InstObjParams("eret", "Eret", "PredOp",
{ "code": eretCode,
"predicate_test": predicateTest },
["IsNonSpeculative", "IsSerializeAfter"])
["IsNonSpeculative", "IsSerializeAfter",
"IsSquashAfter"])
header_output += BasicDeclare.subst(eretIop)
decoder_output += BasicConstructor.subst(eretIop)
exec_output += PredOpExecute.subst(eretIop)