ruby: converts sparse memory stats to gem5 style

src/mem/ruby/slicc_interface/AbstractController.hh

@@ -71,7 +71,6 @@ class AbstractController : public ClockedObject, public Consumer
     virtual DataBlock& getDataBlock(const Address& addr) = 0;
 
     virtual void print(std::ostream & out) const = 0;
-    virtual void printStats(std::ostream & out) const = 0;
     virtual void wakeup() = 0;
     virtual void clearStats() = 0;
     virtual void regStats() = 0;

src/mem/ruby/system/DirectoryMemory.cc

@@ -192,10 +192,10 @@ DirectoryMemory::print(ostream& out) const
 }
 
 void
-DirectoryMemory::printStats(ostream& out) const
+DirectoryMemory::regStats()
 {
     if (m_use_map) {
-        m_sparseMemory->printStats(out);
+        m_sparseMemory->regStats(name());
     }
 }
 

src/mem/ruby/system/DirectoryMemory.hh

@@ -63,7 +63,7 @@ class DirectoryMemory : public SimObject
     void invalidateBlock(PhysAddress address);
 
     void print(std::ostream& out) const;
-    void printStats(std::ostream& out) const;
+    void regStats();
 
     void recordRequestType(DirectoryRequestType requestType);
 

src/mem/ruby/system/SparseMemory.cc

@@ -57,15 +57,6 @@ SparseMemory::SparseMemory(int number_of_levels)
             m_number_of_bits_per_level[level] = even_level_bits;
     }
     m_map_head = new SparseMapType;
-
-    m_total_adds = 0;
-    m_total_removes = 0;
-    m_adds_per_level = new uint64_t[m_number_of_levels];
-    m_removes_per_level = new uint64_t[m_number_of_levels];
-    for (int level = 0; level < m_number_of_levels; level++) {
-        m_adds_per_level[level] = 0;
-        m_removes_per_level[level] = 0;
-    }
 }
 
 SparseMemory::~SparseMemory()
@@ -73,8 +64,6 @@ SparseMemory::~SparseMemory()
     recursivelyRemoveTables(m_map_head, 0);
     delete m_map_head;
     delete [] m_number_of_bits_per_level;
-    delete [] m_adds_per_level;
-    delete [] m_removes_per_level;
 }
 
 // Recursively search table hierarchy for the lowest level table.
@@ -409,21 +398,20 @@ SparseMemory::recordBlocks(int cntrl_id, CacheRecorder* tr) const
 }
 
 void
-SparseMemory::print(ostream& out) const
+SparseMemory::regStats(const string &name)
 {
-}
+    m_total_adds.name(name + ".total_adds");
 
-void
-SparseMemory::printStats(ostream& out) const
-{
-    out << "total_adds: " << m_total_adds << " [";
-    for (int level = 0; level < m_number_of_levels; level++) {
-        out << m_adds_per_level[level] << " ";
-    }
-    out << "]" << endl;
-    out << "total_removes: " << m_total_removes << " [";
-    for (int level = 0; level < m_number_of_levels; level++) {
-        out << m_removes_per_level[level] << " ";
-    }
-    out << "]" << endl;
+    m_adds_per_level
+        .init(m_number_of_levels)
+        .name(name + ".adds_per_level")
+        .flags(Stats::pdf | Stats::total)
+        ;
+
+    m_total_removes.name(name + ".total_removes");
+    m_removes_per_level
+        .init(m_number_of_levels)
+        .name(name + ".removes_per_level")
+        .flags(Stats::pdf | Stats::total)
+        ;
 }

src/mem/ruby/system/SparseMemory.hh

@@ -31,8 +31,10 @@
 #define __MEM_RUBY_SYSTEM_SPARSEMEMORY_HH__
 
 #include <iostream>
+#include <string>
 
 #include "base/hashmap.hh"
+#include "base/statistics.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
@@ -67,14 +69,9 @@ class SparseMemory
     void recordBlocks(int cntrl_id, CacheRecorder *) const;
 
     AbstractEntry* lookup(const Address& address);
-
-    // Print cache contents
-    void print(std::ostream& out) const;
-    void printStats(std::ostream& out) const;
+    void regStats(const std::string &name);
 
   private:
-    // Private Methods
-
     // Private copy constructor and assignment operator
     SparseMemory(const SparseMemory& obj);
     SparseMemory& operator=(const SparseMemory& obj);
@@ -92,10 +89,10 @@ class SparseMemory
     int m_number_of_levels;
     int* m_number_of_bits_per_level;
 
-    uint64_t m_total_adds;
-    uint64_t m_total_removes;
-    uint64_t* m_adds_per_level;
-    uint64_t* m_removes_per_level;
+    Stats::Scalar m_total_adds;
+    Stats::Vector m_adds_per_level;
+    Stats::Scalar m_total_removes;
+    Stats::Vector m_removes_per_level;
 };
 
 #endif // __MEM_RUBY_SYSTEM_SPARSEMEMORY_HH__

src/mem/ruby/system/System.cc

@@ -145,15 +145,6 @@ RubySystem::printStats(ostream& out)
 
     m_profiler_ptr->printStats(out);
     m_network_ptr->printStats(out);
-
-    for (uint32_t i = 0;i < g_abs_controls.size(); ++i) {
-        for (map<uint32_t, AbstractController *>::iterator it =
-                g_abs_controls[i].begin();
-             it != g_abs_controls[i].end(); ++it) {
-
-            ((*it).second)->printStats(out);
-        }
-    }
 }
 
 void

src/mem/slicc/symbols/StateMachine.py

@@ -257,7 +257,6 @@ class $c_ident : public AbstractController
 
     void print(std::ostream& out) const;
     void wakeup();
-    void printStats(std::ostream& out) const;
     void clearStats();
     void regStats();
     void collateStats();
@@ -847,22 +846,6 @@ $c_ident::print(ostream& out) const
     out << "[$c_ident " << m_version << "]";
 }
 
-void
-$c_ident::printStats(ostream& out) const
-{
-''')
-        #
-        # Cache and Memory Controllers have specific profilers associated with
-        # them.  Print out these stats before dumping state transition stats.
-        #
-        for param in self.config_parameters:
-            if param.type_ast.type.ident == "DirectoryMemory":
-                assert(param.pointer)
-                code('    m_${{param.ident}}_ptr->printStats(out);')
-
-        code('''
-}
-
 void $c_ident::clearStats()
 {
     for (int state = 0; state < ${ident}_State_NUM; state++) {