minor mods for mimicking NS83820 functionality
dev/ide_ctrl.cc: generalize these #defs dev/ide_ctrl.hh: put these in pcireg.h dev/ns_gige.cc: do i need io_enable? and assert will fail if i actually need to implement it, which may give clue as to wehtehr i need to implmeent the mem_enable and bm_enable stuff. dev/ns_gige.hh: implement this in case it's needed dev/pcireg.h: put these defs in pcireg instead --HG-- extra : convert_revision : 5e3581b5da17410f943907139bd479f15d2231e8
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@ -342,12 +342,12 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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// (like updating the PIO ranges)
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switch (offset) {
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case PCI_COMMAND:
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if (config.data[offset] & IOSE)
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if (config.data[offset] & PCI_CMD_IOSE)
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io_enabled = true;
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else
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io_enabled = false;
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if (config.data[offset] & BME)
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if (config.data[offset] & PCI_CMD_BME)
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bm_enabled = true;
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else
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bm_enabled = false;
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@ -74,10 +74,6 @@
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#define UDMACTL (5)
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#define UDMATIM (6)
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// PCI Command bit fields
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#define BME 0x04 // Bus master function enable
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#define IOSE 0x01 // I/O space enable
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typedef enum RegType {
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COMMAND_BLOCK = 0,
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CONTROL_BLOCK,
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@ -98,7 +98,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6])
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: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t),
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: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), io_enable(false),
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txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
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txXferLen(0), rxXferLen(0), txPktXmitted(0), txState(txIdle), CTDD(false),
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txFifoCnt(0), txFifoAvail(MAX_TX_FIFO_SIZE), txHalt(false),
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@ -242,6 +242,28 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
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// Need to catch writes to BARs to update the PIO interface
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switch (offset) {
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//seems to work fine without all these, but i ut in the IO to
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//double check, an assertion will fail if we need to properly
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// imlpement it
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case PCI_COMMAND:
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if (config.data[offset] & PCI_CMD_IOSE)
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io_enable = true;
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else
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io_enable = false;
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#if 0
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if (config.data[offset] & PCI_CMD_BME)
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bm_enabled = true;
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else
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bm_enabled = false;
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break;
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if (config.data[offset] & PCI_CMD_MSE)
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mem_enable = true;
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else
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mem_enable = false;
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break;
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#endif
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case PCI0_BASE_ADDR0:
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if (BARAddrs[0] != 0) {
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@ -272,6 +294,8 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
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Fault
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NSGigE::read(MemReqPtr &req, uint8_t *data)
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{
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assert(io_enable);
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//The mask is to give you only the offset into the device register file
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Addr daddr = req->paddr & 0xfff;
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DPRINTF(EthernetPIO, "read da=%#x pa=%#x va=%#x size=%d\n",
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@ -474,6 +498,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
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Fault
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NSGigE::write(MemReqPtr &req, const uint8_t *data)
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{
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assert(io_enable);
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Addr daddr = req->paddr & 0xfff;
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DPRINTF(EthernetPIO, "write da=%#x pa=%#x va=%#x size=%d\n",
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daddr, req->paddr, req->vaddr, req->size);
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@ -2085,6 +2111,8 @@ NSGigE::serialize(ostream &os)
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SERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
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SERIALIZE_SCALAR(io_enable);
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/*
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* Serialize the data Fifos
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*/
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@ -2242,6 +2270,8 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion)
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UNSERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
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UNSERIALIZE_SCALAR(io_enable);
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/*
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* unserialize the data fifos
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*/
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@ -158,6 +158,13 @@ class NSGigE : public PciDev
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dp_regs regs;
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dp_rom rom;
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/** pci settings */
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bool io_enable;
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#if 0
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bool mem_enable;
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bool bm_enable;
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#endif
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/*** BASIC STRUCTURES FOR TX/RX ***/
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/* Data FIFOs */
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pktbuf_t txFifo;
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@ -114,6 +114,11 @@ union PCIConfig {
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#define PCI_HEADER_TYPE 0x0E // Header Type ro
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#define PCI_BIST 0x0F // Built in self test rw
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// some pci command reg bitfields
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#define PCI_CMD_BME 0x04 // Bus master function enable
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#define PCI_CMD_MSE 0x02 // Memory Space Access enable
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#define PCI_CMD_IOSE 0x01 // I/O space enable
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// Type 0 PCI offsets
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#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
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