minor mods for mimicking NS83820 functionality
dev/ide_ctrl.cc: generalize these #defs dev/ide_ctrl.hh: put these in pcireg.h dev/ns_gige.cc: do i need io_enable? and assert will fail if i actually need to implement it, which may give clue as to wehtehr i need to implmeent the mem_enable and bm_enable stuff. dev/ns_gige.hh: implement this in case it's needed dev/pcireg.h: put these defs in pcireg instead --HG-- extra : convert_revision : 5e3581b5da17410f943907139bd479f15d2231e8
This commit is contained in:
parent
f0f96233e8
commit
bfcb088281
5 changed files with 45 additions and 7 deletions
|
@ -342,12 +342,12 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
|
||||||
// (like updating the PIO ranges)
|
// (like updating the PIO ranges)
|
||||||
switch (offset) {
|
switch (offset) {
|
||||||
case PCI_COMMAND:
|
case PCI_COMMAND:
|
||||||
if (config.data[offset] & IOSE)
|
if (config.data[offset] & PCI_CMD_IOSE)
|
||||||
io_enabled = true;
|
io_enabled = true;
|
||||||
else
|
else
|
||||||
io_enabled = false;
|
io_enabled = false;
|
||||||
|
|
||||||
if (config.data[offset] & BME)
|
if (config.data[offset] & PCI_CMD_BME)
|
||||||
bm_enabled = true;
|
bm_enabled = true;
|
||||||
else
|
else
|
||||||
bm_enabled = false;
|
bm_enabled = false;
|
||||||
|
|
|
@ -74,10 +74,6 @@
|
||||||
#define UDMACTL (5)
|
#define UDMACTL (5)
|
||||||
#define UDMATIM (6)
|
#define UDMATIM (6)
|
||||||
|
|
||||||
// PCI Command bit fields
|
|
||||||
#define BME 0x04 // Bus master function enable
|
|
||||||
#define IOSE 0x01 // I/O space enable
|
|
||||||
|
|
||||||
typedef enum RegType {
|
typedef enum RegType {
|
||||||
COMMAND_BLOCK = 0,
|
COMMAND_BLOCK = 0,
|
||||||
CONTROL_BLOCK,
|
CONTROL_BLOCK,
|
||||||
|
|
|
@ -98,7 +98,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
|
||||||
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
|
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
|
||||||
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
|
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
|
||||||
uint32_t func, bool rx_filter, const int eaddr[6])
|
uint32_t func, bool rx_filter, const int eaddr[6])
|
||||||
: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t),
|
: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), io_enable(false),
|
||||||
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
|
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
|
||||||
txXferLen(0), rxXferLen(0), txPktXmitted(0), txState(txIdle), CTDD(false),
|
txXferLen(0), rxXferLen(0), txPktXmitted(0), txState(txIdle), CTDD(false),
|
||||||
txFifoCnt(0), txFifoAvail(MAX_TX_FIFO_SIZE), txHalt(false),
|
txFifoCnt(0), txFifoAvail(MAX_TX_FIFO_SIZE), txHalt(false),
|
||||||
|
@ -242,6 +242,28 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
|
||||||
|
|
||||||
// Need to catch writes to BARs to update the PIO interface
|
// Need to catch writes to BARs to update the PIO interface
|
||||||
switch (offset) {
|
switch (offset) {
|
||||||
|
//seems to work fine without all these, but i ut in the IO to
|
||||||
|
//double check, an assertion will fail if we need to properly
|
||||||
|
// imlpement it
|
||||||
|
case PCI_COMMAND:
|
||||||
|
if (config.data[offset] & PCI_CMD_IOSE)
|
||||||
|
io_enable = true;
|
||||||
|
else
|
||||||
|
io_enable = false;
|
||||||
|
#if 0
|
||||||
|
if (config.data[offset] & PCI_CMD_BME)
|
||||||
|
bm_enabled = true;
|
||||||
|
else
|
||||||
|
bm_enabled = false;
|
||||||
|
break;
|
||||||
|
|
||||||
|
if (config.data[offset] & PCI_CMD_MSE)
|
||||||
|
mem_enable = true;
|
||||||
|
else
|
||||||
|
mem_enable = false;
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
|
||||||
case PCI0_BASE_ADDR0:
|
case PCI0_BASE_ADDR0:
|
||||||
if (BARAddrs[0] != 0) {
|
if (BARAddrs[0] != 0) {
|
||||||
|
|
||||||
|
@ -272,6 +294,8 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
|
||||||
Fault
|
Fault
|
||||||
NSGigE::read(MemReqPtr &req, uint8_t *data)
|
NSGigE::read(MemReqPtr &req, uint8_t *data)
|
||||||
{
|
{
|
||||||
|
assert(io_enable);
|
||||||
|
|
||||||
//The mask is to give you only the offset into the device register file
|
//The mask is to give you only the offset into the device register file
|
||||||
Addr daddr = req->paddr & 0xfff;
|
Addr daddr = req->paddr & 0xfff;
|
||||||
DPRINTF(EthernetPIO, "read da=%#x pa=%#x va=%#x size=%d\n",
|
DPRINTF(EthernetPIO, "read da=%#x pa=%#x va=%#x size=%d\n",
|
||||||
|
@ -474,6 +498,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
|
||||||
Fault
|
Fault
|
||||||
NSGigE::write(MemReqPtr &req, const uint8_t *data)
|
NSGigE::write(MemReqPtr &req, const uint8_t *data)
|
||||||
{
|
{
|
||||||
|
assert(io_enable);
|
||||||
|
|
||||||
Addr daddr = req->paddr & 0xfff;
|
Addr daddr = req->paddr & 0xfff;
|
||||||
DPRINTF(EthernetPIO, "write da=%#x pa=%#x va=%#x size=%d\n",
|
DPRINTF(EthernetPIO, "write da=%#x pa=%#x va=%#x size=%d\n",
|
||||||
daddr, req->paddr, req->vaddr, req->size);
|
daddr, req->paddr, req->vaddr, req->size);
|
||||||
|
@ -2085,6 +2111,8 @@ NSGigE::serialize(ostream &os)
|
||||||
|
|
||||||
SERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
|
SERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
|
||||||
|
|
||||||
|
SERIALIZE_SCALAR(io_enable);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Serialize the data Fifos
|
* Serialize the data Fifos
|
||||||
*/
|
*/
|
||||||
|
@ -2242,6 +2270,8 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
|
||||||
UNSERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
|
UNSERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
|
||||||
|
|
||||||
|
UNSERIALIZE_SCALAR(io_enable);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* unserialize the data fifos
|
* unserialize the data fifos
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -158,6 +158,13 @@ class NSGigE : public PciDev
|
||||||
dp_regs regs;
|
dp_regs regs;
|
||||||
dp_rom rom;
|
dp_rom rom;
|
||||||
|
|
||||||
|
/** pci settings */
|
||||||
|
bool io_enable;
|
||||||
|
#if 0
|
||||||
|
bool mem_enable;
|
||||||
|
bool bm_enable;
|
||||||
|
#endif
|
||||||
|
|
||||||
/*** BASIC STRUCTURES FOR TX/RX ***/
|
/*** BASIC STRUCTURES FOR TX/RX ***/
|
||||||
/* Data FIFOs */
|
/* Data FIFOs */
|
||||||
pktbuf_t txFifo;
|
pktbuf_t txFifo;
|
||||||
|
|
|
@ -114,6 +114,11 @@ union PCIConfig {
|
||||||
#define PCI_HEADER_TYPE 0x0E // Header Type ro
|
#define PCI_HEADER_TYPE 0x0E // Header Type ro
|
||||||
#define PCI_BIST 0x0F // Built in self test rw
|
#define PCI_BIST 0x0F // Built in self test rw
|
||||||
|
|
||||||
|
// some pci command reg bitfields
|
||||||
|
#define PCI_CMD_BME 0x04 // Bus master function enable
|
||||||
|
#define PCI_CMD_MSE 0x02 // Memory Space Access enable
|
||||||
|
#define PCI_CMD_IOSE 0x01 // I/O space enable
|
||||||
|
|
||||||
// Type 0 PCI offsets
|
// Type 0 PCI offsets
|
||||||
#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
|
#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
|
||||||
#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
|
#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
|
||||||
|
|
Loading…
Reference in a new issue