X86: Separate the effective seg base and the "hidden" seg base.
--HG-- extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4
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@ -121,11 +121,11 @@ def operands {{
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# The TOP register should needs to be more protected so that later
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# The TOP register should needs to be more protected so that later
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# instructions don't map their indexes with an old value.
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# instructions don't map their indexes with an old value.
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'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61),
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'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61),
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
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'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 71),
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'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 71),
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'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 72),
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'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 72),
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'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
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'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
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'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
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'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
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'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
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'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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}};
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}};
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@ -103,6 +103,7 @@ archPrctlFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
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//Each of these valid options should actually check addr.
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//Each of these valid options should actually check addr.
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case SetFS:
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case SetFS:
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tc->setMiscRegNoEffect(MISCREG_FS_BASE, addr);
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tc->setMiscRegNoEffect(MISCREG_FS_BASE, addr);
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tc->setMiscRegNoEffect(MISCREG_FS_EFF_BASE, addr);
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return 0;
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return 0;
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case GetFS:
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case GetFS:
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fsBase = tc->readMiscRegNoEffect(MISCREG_FS_BASE);
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fsBase = tc->readMiscRegNoEffect(MISCREG_FS_BASE);
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@ -110,6 +111,7 @@ archPrctlFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
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return 0;
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return 0;
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case SetGS:
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case SetGS:
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tc->setMiscRegNoEffect(MISCREG_GS_BASE, addr);
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tc->setMiscRegNoEffect(MISCREG_GS_BASE, addr);
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tc->setMiscRegNoEffect(MISCREG_GS_EFF_BASE, addr);
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return 0;
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return 0;
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case GetGS:
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case GetGS:
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gsBase = tc->readMiscRegNoEffect(MISCREG_GS_BASE);
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gsBase = tc->readMiscRegNoEffect(MISCREG_GS_BASE);
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@ -186,6 +186,25 @@ void MiscRegFile::setReg(int miscReg,
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break;
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break;
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case MISCREG_CR8:
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case MISCREG_CR8:
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break;
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break;
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case MISCREG_CS_ATTR:
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{
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SegAttr toggled = regVal[miscReg] ^ val;
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SegAttr newCSAttr = val;
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if (toggled.longMode) {
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SegAttr newCSAttr = val;
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if (newCSAttr.longMode) {
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regVal[MISCREG_ES_EFF_BASE] = 0;
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regVal[MISCREG_CS_EFF_BASE] = 0;
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regVal[MISCREG_SS_EFF_BASE] = 0;
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regVal[MISCREG_DS_EFF_BASE] = 0;
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} else {
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regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
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regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
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regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
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regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
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}
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}
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}
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}
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}
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setRegNoEffect(miscReg, newVal);
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setRegNoEffect(miscReg, newVal);
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}
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}
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@ -270,8 +270,20 @@ namespace X86ISA
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MISCREG_GS_BASE,
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MISCREG_GS_BASE,
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MISCREG_INT_BASE,
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MISCREG_INT_BASE,
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// The effective segment base, ie what is actually added to an
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// address. In 64 bit mode this can be different from the above,
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// namely 0.
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MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
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MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
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MISCREG_CS_EFF_BASE,
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MISCREG_SS_EFF_BASE,
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MISCREG_DS_EFF_BASE,
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MISCREG_FS_EFF_BASE,
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MISCREG_GS_EFF_BASE,
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MISCREG_INT_EFF_BASE,
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// Hidden segment limit field
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// Hidden segment limit field
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MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
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MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NumSegments,
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MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
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MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
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MISCREG_CS_LIMIT,
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MISCREG_CS_LIMIT,
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MISCREG_SS_LIMIT,
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MISCREG_SS_LIMIT,
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@ -406,6 +418,12 @@ namespace X86ISA
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return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
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return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
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}
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}
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static inline MiscRegIndex
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MISCREG_SEG_EFF_BASE(int index)
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{
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return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
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}
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static inline MiscRegIndex
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static inline MiscRegIndex
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MISCREG_SEG_LIMIT(int index)
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MISCREG_SEG_LIMIT(int index)
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{
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{
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@ -160,6 +160,7 @@ X86LiveProcess::startup()
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//Initialize the segment registers.
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//Initialize the segment registers.
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for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
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for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
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tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
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tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
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tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
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}
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}
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@ -118,6 +118,7 @@ void initCPU(ThreadContext *tc, int cpuId)
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for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
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for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
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tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
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tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
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tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
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tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
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tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
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tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
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}
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}
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@ -130,7 +131,10 @@ void initCPU(ThreadContext *tc, int cpuId)
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codeAttr.defaultSize = 0;
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codeAttr.defaultSize = 0;
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tc->setMiscReg(MISCREG_CS, 0xf000);
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tc->setMiscReg(MISCREG_CS, 0xf000);
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tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000ULL);
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tc->setMiscReg(MISCREG_CS_BASE,
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0x00000000ffff0000ULL);
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tc->setMiscReg(MISCREG_CS_EFF_BASE,
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0x00000000ffff0000ULL);
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// This has the base value pre-added.
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// This has the base value pre-added.
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tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
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tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
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tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
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tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
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