From d9172c8f462511cde474040581063180be18540a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 5 Oct 2006 16:26:16 -0400
Subject: [PATCH 01/38] Partial reimplementation of the bus. The "clock" and
 "width" parameters have been added, and the HasData flag has been partially
 added to packets.

--HG--
extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39
---
 src/mem/bus.cc               | 41 +++++++++++++++++++++++++++++++++---
 src/mem/bus.hh               | 16 ++++++++++++--
 src/mem/packet.hh            | 23 ++++++++++++--------
 src/python/m5/objects/Bus.py |  2 ++
 4 files changed, 68 insertions(+), 14 deletions(-)

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index cf9e54e62..e3b395afc 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -78,6 +78,16 @@ Bus::recvTiming(Packet *pkt)
             pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
 
     short dest = pkt->getDest();
+    //if (pkt->isRequest() && curTick < tickAddrLastUsed ||
+    //        (pkt->isResponse() || pkt->hasData()) && curTick < tickDataLastUsed) {
+        //We're going to need resources that have already been committed
+        //Send this guy to the back of the line
+        //We don't need to worry about scheduling an event to deal with when the
+        //bus is freed because that's handled when tick*LastUsed is incremented.
+    //    retryList.push_back(interfaces[pkt->getSrc()]);
+    //    return false;
+    //}
+
     if (dest == Packet::Broadcast) {
         if ( timingSnoopPhase1(pkt) )
         {
@@ -95,8 +105,29 @@ Bus::recvTiming(Packet *pkt)
         assert(dest != pkt->getSrc()); // catch infinite loops
         port = interfaces[dest];
     }
+
+
     if (port->sendTiming(pkt))  {
-        // packet was successfully sent, just return true.
+        // Packet was successfully sent.
+        // Figure out what resources were used, and then return true.
+        //if (pkt->isRequest()) {
+            // The address bus will be used for one cycle
+        //    while (tickAddrLastUsed <= curTick)
+        //        tickAddrLastUsed += clock;
+        //}
+        //if (pkt->isResponse() || pkt->hasData()) {
+            // Use up the data bus for at least one bus cycle
+        //    while (tickDataLastUsed <= curTick)
+        //        tickDataLastUsed += clock;
+            // Use up the data bus for however many cycles remain
+        //    if (pkt->hasData()) {
+        //        int dataSize = pkt->getSize();
+        //        for (int transmitted = width; transmitted < dataSize;
+        //                transmitted += width) {
+        //            tickDataLastUsed += clock;
+        //        }
+        //    }
+        //}
         return true;
     }
 
@@ -380,16 +411,20 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
 
     Param<int> bus_id;
+    Param<int> clock;
+    Param<int> width;
 
 END_DECLARE_SIM_OBJECT_PARAMS(Bus)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
-    INIT_PARAM(bus_id, "a globally unique bus id")
+    INIT_PARAM(bus_id, "a globally unique bus id"),
+    INIT_PARAM(clock, "bus clock speed"),
+    INIT_PARAM(width, "width of the bus (bits)")
 END_INIT_SIM_OBJECT_PARAMS(Bus)
 
 CREATE_SIM_OBJECT(Bus)
 {
-    return new Bus(getInstanceName(), bus_id);
+    return new Bus(getInstanceName(), bus_id, clock, width);
 }
 
 REGISTER_SIM_OBJECT("Bus", Bus)
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 941389296..9dd666304 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -51,6 +51,14 @@ class Bus : public MemObject
 {
     /** a globally unique id for this bus. */
     int busId;
+    /** the clock speed for the bus */
+    int clock;
+    /** the width of the bus in bits */
+    int width;
+    /** the last tick the address bus was used */
+    Tick tickAddrLastUsed;
+    /** the last tick the data bus was used */
+    Tick tickDataLastUsed;
 
     static const int defaultId = -1;
 
@@ -199,8 +207,12 @@ class Bus : public MemObject
 
     virtual void init();
 
-    Bus(const std::string &n, int bus_id)
-        : MemObject(n), busId(bus_id), defaultPort(NULL)  {}
+    Bus(const std::string &n, int bus_id, int _clock, int _width)
+        : MemObject(n), busId(bus_id), clock(_clock), width(_width),
+        tickAddrLastUsed(0), tickDataLastUsed(0), defaultPort(NULL)
+    {
+        assert(width);
+    }
 
 };
 
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index c7d28010c..b14343b47 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -174,7 +174,8 @@ class Packet
         IsResponse 	= 1 << 5,
         NeedsResponse	= 1 << 6,
         IsSWPrefetch    = 1 << 7,
-        IsHWPrefetch    = 1 << 8
+        IsHWPrefetch    = 1 << 8,
+        HasData		= 1 << 9
     };
 
   public:
@@ -183,21 +184,24 @@ class Packet
     {
         InvalidCmd      = 0,
         ReadReq		= IsRead  | IsRequest | NeedsResponse,
-        WriteReq	= IsWrite | IsRequest | NeedsResponse,
-        WriteReqNoAck	= IsWrite | IsRequest,
-        ReadResp	= IsRead  | IsResponse | NeedsResponse,
+        WriteReq	= IsWrite | IsRequest | NeedsResponse,// | HasData,
+        WriteReqNoAck	= IsWrite | IsRequest,// | HasData,
+        ReadResp	= IsRead  | IsResponse | NeedsResponse,// | HasData,
         WriteResp	= IsWrite | IsResponse | NeedsResponse,
-        Writeback       = IsWrite | IsRequest,
+        Writeback       = IsWrite | IsRequest,// | HasData,
         SoftPFReq       = IsRead  | IsRequest | IsSWPrefetch | NeedsResponse,
         HardPFReq       = IsRead  | IsRequest | IsHWPrefetch | NeedsResponse,
-        SoftPFResp      = IsRead  | IsResponse | IsSWPrefetch | NeedsResponse,
-        HardPFResp      = IsRead  | IsResponse | IsHWPrefetch | NeedsResponse,
+        SoftPFResp      = IsRead  | IsResponse | IsSWPrefetch
+                                | NeedsResponse,// | HasData,
+        HardPFResp      = IsRead  | IsResponse | IsHWPrefetch
+                                | NeedsResponse,// | HasData,
         InvalidateReq   = IsInvalidate | IsRequest,
-        WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
+        WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,// | HasData,
         UpgradeReq      = IsInvalidate | IsRequest | NeedsResponse,
         UpgradeResp     = IsInvalidate | IsResponse | NeedsResponse,
         ReadExReq       = IsRead | IsInvalidate | IsRequest | NeedsResponse,
-        ReadExResp      = IsRead | IsInvalidate | IsResponse | NeedsResponse
+        ReadExResp      = IsRead | IsInvalidate | IsResponse
+                                | NeedsResponse,// | HasData
     };
 
     /** Return the string name of the cmd field (for debugging and
@@ -219,6 +223,7 @@ class Packet
     bool isResponse()	 { return (cmd & IsResponse) != 0; }
     bool needsResponse() { return (cmd & NeedsResponse) != 0; }
     bool isInvalidate()  { return (cmd & IsInvalidate) != 0; }
+    bool hasData()	 { return (cmd & HasData) != 0; }
 
     bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; }
     bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; }
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index f6828a0d5..b7c55990c 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -6,3 +6,5 @@ class Bus(MemObject):
     port = VectorPort("vector port for connecting devices")
     default = Port("Default port for requests that aren't handeled by a device.")
     bus_id = Param.Int(0, "blah")
+    clock = Param.Clock("1GHz", "bus clock speed")
+    width = Param.Int(64, "bus width (bits)")

From c2f954ac692e664ba105f94c64c8c408cf1b4380 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 04:29:40 -0400
Subject: [PATCH 02/38] Allocate new thread stacks and shared mem region via
 Process page table for Tru64 thread library emulation.

--HG--
extra : convert_revision : dbd307536e260e24ef79130d2aa88d84e33f03d4
---
 src/kern/tru64/tru64.hh | 39 ++++++++++++++++++++++++---------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 87ac88007..18671c364 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -588,16 +588,26 @@ class Tru64 : public OperatingSystem
 
         argp.copyIn(tc->getMemPort());
 
+        int stack_size =
+            gtoh(argp->rsize) + gtoh(argp->ysize) + gtoh(argp->gsize);
+
         // if the user chose an address, just let them have it.  Otherwise
         // pick one for them.
-        if (htog(argp->address) == 0) {
-            argp->address = htog(process->next_thread_stack_base);
-            int stack_size = (htog(argp->rsize) + htog(argp->ysize) +
-                    htog(argp->gsize));
+        Addr stack_base = gtoh(argp->address);
+
+        if (stack_base == 0) {
+            stack_base = process->next_thread_stack_base;
             process->next_thread_stack_base -= stack_size;
-            argp.copyOut(tc->getMemPort());
         }
 
+        stack_base = roundDown(stack_base, VMPageSize);
+
+        // map memory
+        process->pTable->allocate(stack_base, roundUp(stack_size, VMPageSize));
+
+        argp->address = gtoh(stack_base);
+        argp.copyOut(tc->getMemPort());
+
         return 0;
     }
 
@@ -633,7 +643,7 @@ class Tru64 : public OperatingSystem
             abort();
         }
 
-        const Addr base_addr = 0x12000; // was 0x3f0000000LL;
+        Addr base_addr = 0x12000; // was 0x3f0000000LL;
         Addr cur_addr = base_addr; // next addresses to use
         // first comes the config_info struct
         Addr config_addr = cur_addr;
@@ -659,8 +669,6 @@ class Tru64 : public OperatingSystem
         config->nxm_slot_state = htog(slot_state_addr);
         config->nxm_rad[0] = htog(rad_state_addr);
 
-        config.copyOut(tc->getMemPort());
-
         // initialize the slot_state array and copy it out
         TypedBufferArg<Tru64::nxm_slot_state_t> slot_state(slot_state_addr,
                                                            slot_state_size);
@@ -672,8 +680,6 @@ class Tru64 : public OperatingSystem
                 (i == 0) ? Tru64::NXM_SLOT_BOUND : Tru64::NXM_SLOT_AVAIL;
         }
 
-        slot_state.copyOut(tc->getMemPort());
-
         // same for the per-RAD "shared" struct.  Note that we need to
         // allocate extra bytes for the per-VP array which is embedded at
         // the end.
@@ -706,17 +712,20 @@ class Tru64 : public OperatingSystem
             }
         }
 
-        rad_state.copyOut(tc->getMemPort());
-
         //
         // copy pointer to shared config area out to user
         //
         *configptr_ptr = htog(config_addr);
-        configptr_ptr.copyOut(tc->getMemPort());
 
         // Register this as a valid address range with the process
-        process->nxm_start = base_addr;
-        process->nxm_end = cur_addr;
+        base_addr = roundDown(base_addr, VMPageSize);
+        int size = cur_addr - base_addr;
+        process->pTable->allocate(base_addr, roundUp(size, VMPageSize));
+
+        config.copyOut(tc->getMemPort());
+        slot_state.copyOut(tc->getMemPort());
+        rad_state.copyOut(tc->getMemPort());
+        configptr_ptr.copyOut(tc->getMemPort());
 
         return 0;
     }

From be36c808f77cfcb001aacb8cb32f45fb5909e00e Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 10:43:31 -0700
Subject: [PATCH 03/38] Rename some vars for clarity.

--HG--
extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
---
 src/cpu/simple/atomic.cc | 41 ++++++++++++++++++++--------------
 src/cpu/simple/timing.cc | 48 ++++++++++++++++++++--------------------
 2 files changed, 48 insertions(+), 41 deletions(-)

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 88698bfee..1b67af81b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -253,29 +253,32 @@ template <class T>
 Fault
 AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
-    data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+    // use the CPU's statically allocated read request and packet objects
+    Request *req = data_read_req;
+    Packet  *pkt = data_read_pkt;
+
+    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
     if (traceData) {
         traceData->setAddr(addr);
     }
 
     // translate to physical address
-    Fault fault = thread->translateDataReadReq(data_read_req);
+    Fault fault = thread->translateDataReadReq(req);
 
     // Now do the access.
     if (fault == NoFault) {
-        data_read_pkt->reinitFromRequest();
+        pkt->reinitFromRequest();
 
-        dcache_latency = dcachePort.sendAtomic(data_read_pkt);
+        dcache_latency = dcachePort.sendAtomic(pkt);
         dcache_access = true;
 
-        assert(data_read_pkt->result == Packet::Success);
-        data = data_read_pkt->get<T>();
-
+        assert(pkt->result == Packet::Success);
+        data = pkt->get<T>();
     }
 
     // This will need a new way to tell if it has a dcache attached.
-    if (data_read_req->getFlags() & UNCACHEABLE)
+    if (req->getFlags() & UNCACHEABLE)
         recordEvent("Uncached Read");
 
     return fault;
@@ -328,33 +331,37 @@ template <class T>
 Fault
 AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
-    data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+    // use the CPU's statically allocated write request and packet objects
+    Request *req = data_write_req;
+    Packet  *pkt = data_write_pkt;
+
+    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
     if (traceData) {
         traceData->setAddr(addr);
     }
 
     // translate to physical address
-    Fault fault = thread->translateDataWriteReq(data_write_req);
+    Fault fault = thread->translateDataWriteReq(req);
 
     // Now do the access.
     if (fault == NoFault) {
         data = htog(data);
-        data_write_pkt->reinitFromRequest();
-        data_write_pkt->dataStatic(&data);
+        pkt->reinitFromRequest();
+        pkt->dataStatic(&data);
 
-        dcache_latency = dcachePort.sendAtomic(data_write_pkt);
+        dcache_latency = dcachePort.sendAtomic(pkt);
         dcache_access = true;
 
-        assert(data_write_pkt->result == Packet::Success);
+        assert(pkt->result == Packet::Success);
 
-        if (res && data_write_req->getFlags() & LOCKED) {
-            *res = data_write_req->getScResult();
+        if (res && req->getFlags() & LOCKED) {
+            *res = req->getScResult();
         }
     }
 
     // This will need a new way to tell if it's hooked up to a cache or not.
-    if (data_write_req->getFlags() & UNCACHEABLE)
+    if (req->getFlags() & UNCACHEABLE)
         recordEvent("Uncached Write");
 
     // If the write needs to have a fault on the access, consider calling
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 03ee27e04..dfe599bc5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -227,35 +227,35 @@ template <class T>
 Fault
 TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
-    // need to fill in CPU & thread IDs here
-    Request *data_read_req = new Request();
-    data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
-    data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+    Request *req =
+        new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
+                    /* CPU ID */ 0, /* thread ID */ 0);
 
     if (traceData) {
-        traceData->setAddr(data_read_req->getVaddr());
+        traceData->setAddr(req->getVaddr());
     }
 
    // translate to physical address
-    Fault fault = thread->translateDataReadReq(data_read_req);
+    Fault fault = thread->translateDataReadReq(req);
 
     // Now do the access.
     if (fault == NoFault) {
-        Packet *data_read_pkt =
-            new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
-        data_read_pkt->dataDynamic<T>(new T);
+        Packet *pkt =
+            new Packet(req, Packet::ReadReq, Packet::Broadcast);
+        pkt->dataDynamic<T>(new T);
 
-        if (!dcachePort.sendTiming(data_read_pkt)) {
+        if (!dcachePort.sendTiming(pkt)) {
             _status = DcacheRetry;
-            dcache_pkt = data_read_pkt;
+            dcache_pkt = pkt;
         } else {
             _status = DcacheWaitResponse;
+            // memory system takes ownership of packet
             dcache_pkt = NULL;
         }
     }
 
     // This will need a new way to tell if it has a dcache attached.
-    if (data_read_req->getFlags() & UNCACHEABLE)
+    if (req->getFlags() & UNCACHEABLE)
         recordEvent("Uncached Read");
 
     return fault;
@@ -308,31 +308,31 @@ template <class T>
 Fault
 TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
-    // need to fill in CPU & thread IDs here
-    Request *data_write_req = new Request();
-    data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
-    data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+    Request *req =
+        new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
+                    /* CPU ID */ 0, /* thread ID */ 0);
 
     // translate to physical address
-    Fault fault = thread->translateDataWriteReq(data_write_req);
+    Fault fault = thread->translateDataWriteReq(req);
+
     // Now do the access.
     if (fault == NoFault) {
-        Packet *data_write_pkt =
-            new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
-        data_write_pkt->allocate();
-        data_write_pkt->set(data);
+        assert(dcache_pkt == NULL);
+        dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+        dcache_pkt->allocate();
+        dcache_pkt->set(data);
 
-        if (!dcachePort.sendTiming(data_write_pkt)) {
+        if (!dcachePort.sendTiming(dcache_pkt)) {
             _status = DcacheRetry;
-            dcache_pkt = data_write_pkt;
         } else {
             _status = DcacheWaitResponse;
+            // memory system takes ownership of packet
             dcache_pkt = NULL;
         }
     }
 
     // This will need a new way to tell if it's hooked up to a cache or not.
-    if (data_write_req->getFlags() & UNCACHEABLE)
+    if (req->getFlags() & UNCACHEABLE)
         recordEvent("Uncached Write");
 
     // If the write needs to have a fault on the access, consider calling

From d3fba5aa30adfb006b99895e869ed175213d0134 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 10:53:24 -0700
Subject: [PATCH 04/38] Implement Alpha LL/SC support for SimpleCPU (Atomic &
 Timing) and PhysicalMemory.  *No* support for caches or O3CPU. Note that
 properly setting cpu_id on all CPUs is now required for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
---
 src/arch/SConscript                         |  1 +
 src/arch/alpha/locked_mem.hh                | 97 +++++++++++++++++++++
 src/arch/mips/locked_mem.hh                 | 62 +++++++++++++
 src/arch/sparc/locked_mem.hh                | 62 +++++++++++++
 src/base/traceflags.py                      |  1 +
 src/cpu/base.hh                             |  2 +-
 src/cpu/simple/atomic.cc                    | 49 +++++++----
 src/cpu/simple/timing.cc                    | 64 +++++++++-----
 src/cpu/simple/timing.hh                    |  2 +
 src/mem/physical.cc                         | 95 ++++++++++++++++++--
 src/mem/physical.hh                         | 62 +++++++++++++
 src/mem/request.hh                          |  6 +-
 src/python/m5/objects/BaseCPU.py            |  3 +-
 tests/configs/simple-atomic.py              |  2 +-
 tests/configs/simple-timing.py              |  2 +-
 tests/configs/tsunami-simple-atomic-dual.py |  2 +-
 tests/configs/tsunami-simple-atomic.py      |  2 +-
 tests/configs/tsunami-simple-timing-dual.py |  2 +-
 tests/configs/tsunami-simple-timing.py      |  2 +-
 19 files changed, 465 insertions(+), 53 deletions(-)
 create mode 100644 src/arch/alpha/locked_mem.hh
 create mode 100644 src/arch/mips/locked_mem.hh
 create mode 100644 src/arch/sparc/locked_mem.hh

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 59cea6211..dda1dea53 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -50,6 +50,7 @@ isa_switch_hdrs = Split('''
 	arguments.hh
 	faults.hh
 	isa_traits.hh
+        locked_mem.hh
 	process.hh
 	regfile.hh
 	stacktrace.hh
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
new file mode 100644
index 000000000..368ea2895
--- /dev/null
+++ b/src/arch/alpha/locked_mem.hh
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
+#define __ARCH_ALPHA_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "arch/isa_traits.hh"
+#include "base/misc.hh"
+#include "mem/request.hh"
+
+
+namespace AlphaISA
+{
+template <class XC>
+inline void
+handleLockedRead(XC *xc, Request *req)
+{
+    xc->setMiscReg(Lock_Addr_DepTag, req->getPaddr() & ~0xf);
+    xc->setMiscReg(Lock_Flag_DepTag, true);
+}
+
+
+template <class XC>
+inline bool
+handleLockedWrite(XC *xc, Request *req)
+{
+    if (req->isUncacheable()) {
+        // Funky Turbolaser mailbox access...don't update
+        // result register (see stq_c in decoder.isa)
+        req->setScResult(2);
+    } else {
+        // standard store conditional
+        bool lock_flag = xc->readMiscReg(Lock_Flag_DepTag);
+        Addr lock_addr = xc->readMiscReg(Lock_Addr_DepTag);
+        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
+            // Lock flag not set or addr mismatch in CPU;
+            // don't even bother sending to memory system
+            req->setScResult(0);
+            xc->setMiscReg(Lock_Flag_DepTag, false);
+            // the rest of this code is not architectural;
+            // it's just a debugging aid to help detect
+            // livelock by warning on long sequences of failed
+            // store conditionals
+            int stCondFailures = xc->readStCondFailures();
+            stCondFailures++;
+            xc->setStCondFailures(stCondFailures);
+            if (stCondFailures % 100000 == 0) {
+                warn("cpu %d: %d consecutive "
+                     "store conditional failures\n",
+                     xc->readCpuId(), stCondFailures);
+            }
+
+            // store conditional failed already, so don't issue it to mem
+            return false;
+        }
+    }
+
+    return true;
+}
+
+
+} // namespace AlphaISA
+
+#endif
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
new file mode 100644
index 000000000..363cf1e90
--- /dev/null
+++ b/src/arch/mips/locked_mem.hh
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
+#define __ARCH_MIPS_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "mem/request.hh"
+
+
+namespace MipsISA
+{
+template <class XC>
+inline void
+handleLockedRead(XC *xc, Request *req)
+{
+}
+
+
+template <class XC>
+inline bool
+handleLockedWrite(XC *xc, Request *req)
+{
+    return true;
+}
+
+
+} // namespace MipsISA
+
+#endif
diff --git a/src/arch/sparc/locked_mem.hh b/src/arch/sparc/locked_mem.hh
new file mode 100644
index 000000000..291b2f422
--- /dev/null
+++ b/src/arch/sparc/locked_mem.hh
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_SPARC_LOCKED_MEM_HH__
+#define __ARCH_SPARC_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "mem/request.hh"
+
+
+namespace SparcISA
+{
+template <class XC>
+inline void
+handleLockedRead(XC *xc, Request *req)
+{
+}
+
+
+template <class XC>
+inline bool
+handleLockedWrite(XC *xc, Request *req)
+{
+    return true;
+}
+
+
+} // namespace SparcISA
+
+#endif
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 8e8153b68..274407be5 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -112,6 +112,7 @@ baseFlags = [
     'IdeDisk',
     'InstExec',
     'Interrupt',
+    'LLSC',
     'LSQ',
     'LSQUnit',
     'Loader',
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index e02527371..75e0d86af 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -140,8 +140,8 @@ class BaseCPU : public MemObject
         bool functionTrace;
         Tick functionTraceStart;
         System *system;
-#if FULL_SYSTEM
         int cpu_id;
+#if FULL_SYSTEM
         Tick profile;
 #endif
         Tick progress_interval;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 1b67af81b..0ca700634 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -28,6 +28,7 @@
  * Authors: Steve Reinhardt
  */
 
+#include "arch/locked_mem.hh"
 #include "arch/utility.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/atomic.hh"
@@ -133,20 +134,19 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
 {
     _status = Idle;
 
-    // @todo fix me and get the real cpu id & thread number!!!
     ifetch_req = new Request();
-    ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
+    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
     ifetch_pkt->dataStatic(&inst);
 
     data_read_req = new Request();
-    data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
+    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
     data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
                                Packet::Broadcast);
     data_read_pkt->dataStatic(&dataReg);
 
     data_write_req = new Request();
-    data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
+    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
     data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
                                 Packet::Broadcast);
 }
@@ -275,6 +275,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
         assert(pkt->result == Packet::Success);
         data = pkt->get<T>();
+
+        if (req->isLocked()) {
+            TheISA::handleLockedRead(thread, req);
+        }
     }
 
     // This will need a new way to tell if it has a dcache attached.
@@ -346,17 +350,32 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 
     // Now do the access.
     if (fault == NoFault) {
-        data = htog(data);
-        pkt->reinitFromRequest();
-        pkt->dataStatic(&data);
+        bool do_access = true;  // flag to suppress cache access
 
-        dcache_latency = dcachePort.sendAtomic(pkt);
-        dcache_access = true;
+        if (req->isLocked()) {
+            do_access = TheISA::handleLockedWrite(thread, req);
+        }
 
-        assert(pkt->result == Packet::Success);
+        if (do_access) {
+            data = htog(data);
+            pkt->reinitFromRequest();
+            pkt->dataStatic(&data);
 
-        if (res && req->getFlags() & LOCKED) {
-            *res = req->getScResult();
+            dcache_latency = dcachePort.sendAtomic(pkt);
+            dcache_access = true;
+
+            assert(pkt->result == Packet::Success);
+        }
+
+        if (req->isLocked()) {
+            uint64_t scResult = req->getScResult();
+            if (scResult != 0) {
+                // clear failure counter
+                thread->setStCondFailures(0);
+            }
+            if (res) {
+                *res = req->getScResult();
+            }
         }
     }
 
@@ -474,11 +493,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     Param<Tick> progress_interval;
     SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
+    Param<int> cpu_id;
 
 #if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
-    Param<int> cpu_id;
     Param<Tick> profile;
 #else
     SimObjectParam<Process *> workload;
@@ -507,11 +526,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     INIT_PARAM(progress_interval, "Progress interval"),
     INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
+    INIT_PARAM(cpu_id, "processor ID"),
 
 #if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(profile, ""),
 #else
     INIT_PARAM(workload, "processes to run"),
@@ -545,11 +564,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
     params->simulate_stalls = simulate_stalls;
     params->mem = mem;
     params->system = system;
+    params->cpu_id = cpu_id;
 
 #if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
-    params->cpu_id = cpu_id;
     params->profile = profile;
 #else
     params->process = workload;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index dfe599bc5..cd43bb5fc 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -28,6 +28,7 @@
  * Authors: Steve Reinhardt
  */
 
+#include "arch/locked_mem.hh"
 #include "arch/utility.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/timing.hh"
@@ -94,7 +95,8 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
 }
 
 TimingSimpleCPU::TimingSimpleCPU(Params *p)
-    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
+    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
+      cpu_id(p->cpu_id)
 {
     _status = Idle;
     ifetch_pkt = dcache_pkt = NULL;
@@ -229,7 +231,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    /* CPU ID */ 0, /* thread ID */ 0);
+                    cpu_id, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -310,7 +312,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    /* CPU ID */ 0, /* thread ID */ 0);
+                    cpu_id, /* thread ID */ 0);
 
     // translate to physical address
     Fault fault = thread->translateDataWriteReq(req);
@@ -322,12 +324,20 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         dcache_pkt->allocate();
         dcache_pkt->set(data);
 
-        if (!dcachePort.sendTiming(dcache_pkt)) {
-            _status = DcacheRetry;
-        } else {
-            _status = DcacheWaitResponse;
-            // memory system takes ownership of packet
-            dcache_pkt = NULL;
+        bool do_access = true;  // flag to suppress cache access
+
+        if (req->isLocked()) {
+            do_access = TheISA::handleLockedWrite(thread, req);
+        }
+
+        if (do_access) {
+            if (!dcachePort.sendTiming(dcache_pkt)) {
+                _status = DcacheRetry;
+            } else {
+                _status = DcacheWaitResponse;
+                // memory system takes ownership of packet
+                dcache_pkt = NULL;
+            }
         }
     }
 
@@ -392,9 +402,8 @@ TimingSimpleCPU::fetch()
 {
     checkForInterrupts();
 
-    // need to fill in CPU & thread IDs here
     Request *ifetch_req = new Request();
-    ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
+    ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
     Fault fault = setupFetchRequest(ifetch_req);
 
     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
@@ -453,12 +462,20 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
     if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
         // load or store: just send to dcache
         Fault fault = curStaticInst->initiateAcc(this, traceData);
-        if (fault == NoFault) {
-            // successfully initiated access: instruction will
-            // complete in dcache response callback
-            assert(_status == DcacheWaitResponse);
+        if (_status != Running) {
+            // instruction will complete in dcache response callback
+            assert(_status == DcacheWaitResponse || _status == DcacheRetry);
+            assert(fault == NoFault);
         } else {
-            // fault: complete now to invoke fault handler
+            if (fault == NoFault) {
+                // early fail on store conditional: complete now
+                assert(dcache_pkt != NULL);
+                fault = curStaticInst->completeAcc(dcache_pkt, this,
+                                                   traceData);
+                delete dcache_pkt->req;
+                delete dcache_pkt;
+                dcache_pkt = NULL;
+            }
             postExecute();
             advanceInst(fault);
         }
@@ -479,8 +496,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    // These next few lines could be replaced with something faster
-    // who knows what though
+    // delay processing of returned data until next CPU clock edge
     Tick time = pkt->req->getTime();
     while (time < curTick)
         time += lat;
@@ -527,6 +543,10 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 
+    if (pkt->isRead() && pkt->req->isLocked()) {
+        TheISA::handleLockedRead(thread, pkt->req);
+    }
+
     delete pkt->req;
     delete pkt;
 
@@ -546,6 +566,7 @@ TimingSimpleCPU::completeDrain()
 bool
 TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
 {
+    // delay processing of returned data until next CPU clock edge
     Tick time = pkt->req->getTime();
     while (time < curTick)
         time += lat;
@@ -574,6 +595,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
     Packet *tmp = cpu->dcache_pkt;
     if (sendTiming(tmp)) {
         cpu->_status = DcacheWaitResponse;
+        // memory system takes ownership of packet
         cpu->dcache_pkt = NULL;
     }
 }
@@ -592,11 +614,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     Param<Tick> progress_interval;
     SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
+    Param<int> cpu_id;
 
 #if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
-    Param<int> cpu_id;
     Param<Tick> profile;
 #else
     SimObjectParam<Process *> workload;
@@ -625,11 +647,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     INIT_PARAM(progress_interval, "Progress interval"),
     INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
+    INIT_PARAM(cpu_id, "processor ID"),
 
 #if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(profile, ""),
 #else
     INIT_PARAM(workload, "processes to run"),
@@ -661,11 +683,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
     params->functionTraceStart = function_trace_start;
     params->mem = mem;
     params->system = system;
+    params->cpu_id = cpu_id;
 
 #if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
-    params->cpu_id = cpu_id;
     params->profile = profile;
 #else
     params->process = workload;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index d03fa4bc0..b65eebd99 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -166,6 +166,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     Packet *ifetch_pkt;
     Packet *dcache_pkt;
 
+    int cpu_id;
+
   public:
 
     virtual Port *getPort(const std::string &if_name, int idx = -1);
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 8fea733ec..23b1d5ffc 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -110,6 +110,88 @@ PhysicalMemory::calculateLatency(Packet *pkt)
     return lat;
 }
 
+
+
+// Add load-locked to tracking list.  Should only be called if the
+// operation is a load and the LOCKED flag is set.
+void
+PhysicalMemory::trackLoadLocked(Request *req)
+{
+    Addr paddr = LockedAddr::mask(req->getPaddr());
+
+    // first we check if we already have a locked addr for this
+    // xc.  Since each xc only gets one, we just update the
+    // existing record with the new address.
+    list<LockedAddr>::iterator i;
+
+    for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
+        if (i->matchesContext(req)) {
+            DPRINTF(LLSC, "Modifying lock record: cpu %d thread %d addr %#x\n",
+                    req->getCpuNum(), req->getThreadNum(), paddr);
+            i->addr = paddr;
+            return;
+        }
+    }
+
+    // no record for this xc: need to allocate a new one
+    DPRINTF(LLSC, "Adding lock record: cpu %d thread %d addr %#x\n",
+            req->getCpuNum(), req->getThreadNum(), paddr);
+    lockedAddrList.push_front(LockedAddr(req));
+}
+
+
+// Called on *writes* only... both regular stores and
+// store-conditional operations.  Check for conventional stores which
+// conflict with locked addresses, and for success/failure of store
+// conditionals.
+bool
+PhysicalMemory::checkLockedAddrList(Request *req)
+{
+    Addr paddr = LockedAddr::mask(req->getPaddr());
+    bool isLocked = req->isLocked();
+
+    // Initialize return value.  Non-conditional stores always
+    // succeed.  Assume conditional stores will fail until proven
+    // otherwise.
+    bool success = !isLocked;
+
+    // Iterate over list.  Note that there could be multiple matching
+    // records, as more than one context could have done a load locked
+    // to this location.
+    list<LockedAddr>::iterator i = lockedAddrList.begin();
+
+    while (i != lockedAddrList.end()) {
+
+        if (i->addr == paddr) {
+            // we have a matching address
+
+            if (isLocked && i->matchesContext(req)) {
+                // it's a store conditional, and as far as the memory
+                // system can tell, the requesting context's lock is
+                // still valid.
+                DPRINTF(LLSC, "StCond success: cpu %d thread %d addr %#x\n",
+                        req->getCpuNum(), req->getThreadNum(), paddr);
+                success = true;
+            }
+
+            // Get rid of our record of this lock and advance to next
+            DPRINTF(LLSC, "Erasing lock record: cpu %d thread %d addr %#x\n",
+                    i->cpuNum, i->threadNum, paddr);
+            i = lockedAddrList.erase(i);
+        }
+        else {
+            // no match: advance to next record
+            ++i;
+        }
+    }
+
+    if (isLocked) {
+        req->setScResult(success ? 1 : 0);
+    }
+
+    return success;
+}
+
 void
 PhysicalMemory::doFunctionalAccess(Packet *pkt)
 {
@@ -117,18 +199,17 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
 
     switch (pkt->cmd) {
       case Packet::ReadReq:
+        if (pkt->req->isLocked()) {
+            trackLoadLocked(pkt->req);
+        }
         memcpy(pkt->getPtr<uint8_t>(),
                pmemAddr + pkt->getAddr() - params()->addrRange.start,
                pkt->getSize());
         break;
       case Packet::WriteReq:
-        memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
-               pkt->getPtr<uint8_t>(),
-               pkt->getSize());
-        // temporary hack: will need to add real LL/SC implementation
-        // for cacheless systems later.
-        if (pkt->req->getFlags() & LOCKED) {
-            pkt->req->setScResult(1);
+        if (writeOK(pkt->req)) {
+            memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
+                   pkt->getPtr<uint8_t>(), pkt->getSize());
         }
         break;
       default:
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 02308b2ef..97bea2ec4 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -78,6 +78,68 @@ class PhysicalMemory : public MemObject
     const PhysicalMemory &operator=(const PhysicalMemory &specmem);
 
   protected:
+
+    class LockedAddr {
+      public:
+        // on alpha, minimum LL/SC granularity is 16 bytes, so lower
+        // bits need to masked off.
+        static const Addr Addr_Mask = 0xf;
+
+        static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
+
+        Addr addr; 	// locked address
+        int cpuNum;	// locking CPU
+        int threadNum;	// locking thread ID within CPU
+
+        // check for matching execution context
+        bool matchesContext(Request *req)
+        {
+            return (cpuNum == req->getCpuNum() &&
+                    threadNum == req->getThreadNum());
+        }
+
+        LockedAddr(Request *req)
+            : addr(mask(req->getPaddr())),
+              cpuNum(req->getCpuNum()),
+              threadNum(req->getThreadNum())
+        {
+        }
+    };
+
+    std::list<LockedAddr> lockedAddrList;
+
+    // helper function for checkLockedAddrs(): we really want to
+    // inline a quick check for an empty locked addr list (hopefully
+    // the common case), and do the full list search (if necessary) in
+    // this out-of-line function
+    bool checkLockedAddrList(Request *req);
+
+    // Record the address of a load-locked operation so that we can
+    // clear the execution context's lock flag if a matching store is
+    // performed
+    void trackLoadLocked(Request *req);
+
+    // Compare a store address with any locked addresses so we can
+    // clear the lock flag appropriately.  Return value set to 'false'
+    // if store operation should be suppressed (because it was a
+    // conditional store and the address was no longer locked by the
+    // requesting execution context), 'true' otherwise.  Note that
+    // this method must be called on *all* stores since even
+    // non-conditional stores must clear any matching lock addresses.
+    bool writeOK(Request *req) {
+        if (lockedAddrList.empty()) {
+            // no locked addrs: nothing to check, store_conditional fails
+            bool isLocked = req->isLocked();
+            if (isLocked) {
+                req->setScResult(0);
+            }
+            return !isLocked; // only do write if not an sc
+        } else {
+            // iterate over list...
+            return checkLockedAddrList(req);
+        }
+    }
+
     uint8_t *pmemAddr;
     MemoryPort *port;
     int pagePtr;
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 6acd7526c..e54984fcd 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -232,9 +232,11 @@ class Request
     Addr getPC() { assert(validPC); return pc; }
 
     /** Accessor Function to Check Cacheability. */
-    bool isUncacheable() { return getFlags() & UNCACHEABLE; }
+    bool isUncacheable() { return (getFlags() & UNCACHEABLE) != 0; }
 
-    bool isInstRead() { return getFlags() & INST_READ; }
+    bool isInstRead() { return (getFlags() & INST_READ) != 0; }
+
+    bool isLocked() { return (getFlags() & LOCKED) != 0; }
 
     friend class Packet;
 };
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 0b887cceb..b6dc08e46 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -11,10 +11,11 @@ class BaseCPU(SimObject):
     mem = Param.MemObject("memory")
 
     system = Param.System(Parent.any, "system object")
+    cpu_id = Param.Int("CPU identifier")
+
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
-        cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
 
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 2bf67f3b1..d35ac4ae0 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -29,7 +29,7 @@
 import m5
 from m5.objects import *
 
-system = System(cpu = AtomicSimpleCPU(),
+system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 7bb76db0e..60190b47c 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -36,7 +36,7 @@ class MyCache(BaseCache):
     mshrs = 10
     tgts_per_mshr = 5
 
-cpu = TimingSimpleCPU()
+cpu = TimingSimpleCPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
 cpu.mem = cpu.dcache
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index e3945f7dc..f798213db 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -34,7 +34,7 @@ import FSConfig
 AlphaConsole.cpu = Parent.cpu[0]
 IntrControl.cpu = Parent.cpu[0]
 
-cpus = [ AtomicSimpleCPU() for i in xrange(2) ]
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpus
 for c in cpus:
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index ca1dd5c77..623d285e4 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -31,7 +31,7 @@ from m5.objects import *
 m5.AddToPath('../configs/common')
 import FSConfig
 
-cpu = AtomicSimpleCPU()
+cpu = AtomicSimpleCPU(cpu_id=0)
 system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 967d6a2d2..bf94214fd 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -34,7 +34,7 @@ import FSConfig
 AlphaConsole.cpu = Parent.cpu[0]
 IntrControl.cpu = Parent.cpu[0]
 
-cpus = [ TimingSimpleCPU() for i in xrange(2) ]
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpus
 for c in cpus:
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index b3fc9d105..2edf5ac32 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -31,7 +31,7 @@ from m5.objects import *
 m5.AddToPath('../configs/common')
 import FSConfig
 
-cpu = TimingSimpleCPU()
+cpu = TimingSimpleCPU(cpu_id=0)
 system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)

From 34b697cd04e7d645f8bf95d5c1a2dfeb623181f1 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 8 Oct 2006 14:04:49 -0400
Subject: [PATCH 05/38] Add in HasData, and move the define of NUM_MEM_CMDS to
 a more visible location.

--HG--
extra : convert_revision : 4379efe892ca0a39363ee04009e1bbb8c8f77afa
---
 src/mem/packet.hh | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index b14343b47..e7047b0cd 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -58,10 +58,6 @@ typedef std::list<PacketPtr> PacketList;
 #define NO_ALLOCATE 1 << 5
 #define SNOOP_COMMIT 1 << 6
 
-//For statistics we need max number of commands, hard code it at
-//20 for now.  @todo fix later
-#define NUM_MEM_CMDS 1 << 9
-
 /**
  * A Packet is used to encapsulate a transfer between two objects in
  * the memory system (e.g., the L1 and L2 cache).  (In contrast, a
@@ -164,6 +160,8 @@ class Packet
 
   private:
     /** List of command attributes. */
+    // If you add a new CommandAttribute, make sure to increase NUM_MEM_CMDS
+    // as well.
     enum CommandAttribute
     {
         IsRead		= 1 << 0,
@@ -178,30 +176,34 @@ class Packet
         HasData		= 1 << 9
     };
 
+//For statistics we need max number of commands, hard code it at
+//20 for now.  @todo fix later
+#define NUM_MEM_CMDS 1 << 10
+
   public:
     /** List of all commands associated with a packet. */
     enum Command
     {
         InvalidCmd      = 0,
         ReadReq		= IsRead  | IsRequest | NeedsResponse,
-        WriteReq	= IsWrite | IsRequest | NeedsResponse,// | HasData,
-        WriteReqNoAck	= IsWrite | IsRequest,// | HasData,
-        ReadResp	= IsRead  | IsResponse | NeedsResponse,// | HasData,
+        WriteReq	= IsWrite | IsRequest | NeedsResponse | HasData,
+        WriteReqNoAck	= IsWrite | IsRequest | HasData,
+        ReadResp	= IsRead  | IsResponse | NeedsResponse | HasData,
         WriteResp	= IsWrite | IsResponse | NeedsResponse,
-        Writeback       = IsWrite | IsRequest,// | HasData,
+        Writeback       = IsWrite | IsRequest | HasData,
         SoftPFReq       = IsRead  | IsRequest | IsSWPrefetch | NeedsResponse,
         HardPFReq       = IsRead  | IsRequest | IsHWPrefetch | NeedsResponse,
         SoftPFResp      = IsRead  | IsResponse | IsSWPrefetch
-                                | NeedsResponse,// | HasData,
+                                | NeedsResponse | HasData,
         HardPFResp      = IsRead  | IsResponse | IsHWPrefetch
-                                | NeedsResponse,// | HasData,
+                                | NeedsResponse | HasData,
         InvalidateReq   = IsInvalidate | IsRequest,
-        WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,// | HasData,
+        WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest | HasData,
         UpgradeReq      = IsInvalidate | IsRequest | NeedsResponse,
         UpgradeResp     = IsInvalidate | IsResponse | NeedsResponse,
         ReadExReq       = IsRead | IsInvalidate | IsRequest | NeedsResponse,
         ReadExResp      = IsRead | IsInvalidate | IsResponse
-                                | NeedsResponse,// | HasData
+                                | NeedsResponse | HasData
     };
 
     /** Return the string name of the cmd field (for debugging and

From 00481d1f192c832d654379c2296d5b6020c12b1a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 8 Oct 2006 14:08:58 -0400
Subject: [PATCH 06/38] A possible implementation of a multiplexed bus.

--HG--
extra : convert_revision : 3c560eda12ffd8ca539c91024baf2770b963ede8
---
 src/mem/bus.cc | 164 +++++++++++++++++++++++++++++++------------------
 src/mem/bus.hh |  53 ++++++++++++++--
 2 files changed, 152 insertions(+), 65 deletions(-)

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index e3b395afc..fff3dfed6 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -67,6 +67,44 @@ Bus::init()
         (*intIter)->sendStatusChange(Port::RangeChange);
 }
 
+Bus::BusFreeEvent::BusFreeEvent(Bus *_bus) : Event(&mainEventQueue), bus(_bus)
+{}
+
+void Bus::BusFreeEvent::process()
+{
+    bus->recvRetry(0);
+}
+
+const char * Bus::BusFreeEvent::description()
+{
+    return "bus became available";
+}
+
+void
+Bus::occupyBus(int numCycles)
+{
+    //Move up when the bus will next be free
+    //We avoid the use of divide by adding repeatedly
+    //This should be faster if the value is updated frequently, but should
+    //be may be slower otherwise.
+
+    //Bring tickNextIdle up to the present tick
+    //There is some potential ambiguity where a cycle starts, which might make
+    //a difference when devices are acting right around a cycle boundary. Using
+    //a < allows things which happen exactly on a cycle boundary to take up only
+    //the following cycle. Anthing that happens later will have to "wait" for the
+    //end of that cycle, and then start using the bus after that.
+    while (tickNextIdle < curTick)
+        tickNextIdle += clock;
+    //Advance it numCycles bus cycles.
+    //XXX Should this use the repeating add trick as well?
+    tickNextIdle += (numCycles * clock);
+    if (!busIdle.scheduled()) {
+        busIdle.schedule(tickNextIdle);
+    } else {
+        busIdle.reschedule(tickNextIdle);
+    }
+}
 
 /** Function called by the port when the bus is receiving a Timing
  * transaction.*/
@@ -77,83 +115,89 @@ Bus::recvTiming(Packet *pkt)
     DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
             pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
 
-    short dest = pkt->getDest();
-    //if (pkt->isRequest() && curTick < tickAddrLastUsed ||
-    //        (pkt->isResponse() || pkt->hasData()) && curTick < tickDataLastUsed) {
-        //We're going to need resources that have already been committed
-        //Send this guy to the back of the line
-        //We don't need to worry about scheduling an event to deal with when the
-        //bus is freed because that's handled when tick*LastUsed is incremented.
-    //    retryList.push_back(interfaces[pkt->getSrc()]);
-    //    return false;
-    //}
+    Port *pktPort = interfaces[pkt->getSrc()];
 
-    if (dest == Packet::Broadcast) {
-        if ( timingSnoopPhase1(pkt) )
-        {
-            timingSnoopPhase2(pkt);
-            port = findPort(pkt->getAddr(), pkt->getSrc());
-        }
-        else
-        {
-            //Snoop didn't succeed
-            retryList.push_back(interfaces[pkt->getSrc()]);
-            return false;
-        }
-    } else {
-        assert(dest >= 0 && dest < interfaces.size());
-        assert(dest != pkt->getSrc()); // catch infinite loops
-        port = interfaces[dest];
+    // If the bus is busy, or other devices are in line ahead of the current one,
+    // put this device on the retry list.
+    if (tickNextIdle > curTick || (retryList.size() && pktPort != retryingPort)) {
+        addToRetryList(pktPort);
+        return false;
     }
 
+    // If the bus is blocked, make the device wait.
+    if (!(port = findDestPort(pkt, pkt->getSrc()))) {
+        addToRetryList(pktPort);
+        return false;
+    }
+
+    // The packet will be sent. Figure out how long it occupies the bus.
+    int numCycles = 0;
+    // Requests need one cycle to send an address
+    if (pkt->isRequest())
+        numCycles++;
+    else if (pkt->isResponse() || pkt->hasData()) {
+        // If a packet has data, it needs ceil(size/width) cycles to send it
+        // We're using the "adding instead of dividing" trick again here
+        if (pkt->hasData()) {
+            int dataSize = pkt->getSize();
+            for (int transmitted = 0; transmitted < dataSize;
+                    transmitted += width) {
+                numCycles++;
+            }
+        } else {
+            // If the packet didn't have data, it must have been a response.
+            // Those use the bus for one cycle to send their data.
+            numCycles++;
+        }
+    }
+
+    occupyBus(numCycles);
 
     if (port->sendTiming(pkt))  {
-        // Packet was successfully sent.
-        // Figure out what resources were used, and then return true.
-        //if (pkt->isRequest()) {
-            // The address bus will be used for one cycle
-        //    while (tickAddrLastUsed <= curTick)
-        //        tickAddrLastUsed += clock;
-        //}
-        //if (pkt->isResponse() || pkt->hasData()) {
-            // Use up the data bus for at least one bus cycle
-        //    while (tickDataLastUsed <= curTick)
-        //        tickDataLastUsed += clock;
-            // Use up the data bus for however many cycles remain
-        //    if (pkt->hasData()) {
-        //        int dataSize = pkt->getSize();
-        //        for (int transmitted = width; transmitted < dataSize;
-        //                transmitted += width) {
-        //            tickDataLastUsed += clock;
-        //        }
-        //    }
-        //}
+        // Packet was successfully sent. Return true.
         return true;
     }
 
-    // packet not successfully sent
-    retryList.push_back(interfaces[pkt->getSrc()]);
+    // Packet not successfully sent. Leave or put it on the retry list.
+    addToRetryList(pktPort);
     return false;
 }
 
 void
 Bus::recvRetry(int id)
 {
-    // Go through all the elements on the list calling sendRetry on each
-    // This is not very efficient at all but it works. Ultimately we should end
-    // up with something that is more intelligent.
-    int initialSize = retryList.size();
-    int i;
-    Port *p;
-
-    for (i = 0; i < initialSize; i++) {
-        assert(retryList.size() > 0);
-        p = retryList.front();
-        retryList.pop_front();
-        p->sendRetry();
+    //If there's anything waiting...
+    if (retryList.size()) {
+        retryingPort = retryList.front();
+        retryingPort->sendRetry();
+        //If the retryingPort pointer isn't null, either sendTiming wasn't
+        //called, or it was and the packet was successfully sent.
+        if (retryingPort) {
+            retryList.pop_front();
+            retryingPort = 0;
+        }
     }
 }
 
+Port *
+Bus::findDestPort(PacketPtr pkt, int id)
+{
+    Port * port = NULL;
+    short dest = pkt->getDest();
+
+    if (dest == Packet::Broadcast) {
+        if (timingSnoopPhase1(pkt)) {
+            timingSnoopPhase2(pkt);
+            port = findPort(pkt->getAddr(), pkt->getSrc());
+        }
+        //else, port stays NULL
+    } else {
+        assert(dest >= 0 && dest < interfaces.size());
+        assert(dest != pkt->getSrc()); // catch infinite loops
+        port = interfaces[dest];
+    }
+    return port;
+}
 
 Port *
 Bus::findPort(Addr addr, int id)
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 9dd666304..96f1152a6 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -46,6 +46,7 @@
 #include "mem/packet.hh"
 #include "mem/port.hh"
 #include "mem/request.hh"
+#include "sim/eventq.hh"
 
 class Bus : public MemObject
 {
@@ -55,10 +56,8 @@ class Bus : public MemObject
     int clock;
     /** the width of the bus in bits */
     int width;
-    /** the last tick the address bus was used */
-    Tick tickAddrLastUsed;
-    /** the last tick the data bus was used */
-    Tick tickDataLastUsed;
+    /** the next tick at which the bus will be idle */
+    Tick tickNextIdle;
 
     static const int defaultId = -1;
 
@@ -101,6 +100,15 @@ class Bus : public MemObject
      */
     Port *findPort(Addr addr, int id);
 
+    /** Finds the port a packet should be sent to. If the bus is blocked, no port
+     * is returned.
+     * @param pkt Packet to find a destination port for.
+     * @param id Id of the port this packet was received from
+     *           (to prevent loops)
+     */
+
+    Port *findDestPort(PacketPtr pkt, int id);
+
     /** Find all ports with a matching snoop range, except src port.  Keep in mind
      * that the ranges shouldn't overlap or you will get a double snoop to the same
      * interface.and the cache will assert out.
@@ -189,6 +197,22 @@ class Bus : public MemObject
 
     };
 
+    class BusFreeEvent : public Event
+    {
+        Bus * bus;
+
+      public:
+        BusFreeEvent(Bus * _bus);
+        void process();
+        const char *description();
+    };
+
+    BusFreeEvent busIdle;
+
+    void occupyBus(int numCycles);
+
+    Port * retryingPort;
+
     /** An array of pointers to the peer port interfaces
         connected to this bus.*/
     std::vector<Port*> interfaces;
@@ -197,6 +221,23 @@ class Bus : public MemObject
      * original send failed for whatever reason.*/
     std::list<Port*> retryList;
 
+    void addToRetryList(Port * port)
+    {
+        if (!retryingPort) {
+            // The device wasn't retrying a packet, or wasn't at an appropriate
+            // time.
+            retryList.push_back(port);
+        } else {
+            // The device was retrying a packet. It didn't work, so we'll leave
+            // it at the head of the retry list.
+            retryingPort = 0;
+
+            // We shouldn't be receiving a packet from one port when a different
+            // one is retrying.
+            assert(port == retryingPort);
+        }
+    }
+
     /** Port that handles requests that don't match any of the interfaces.*/
     Port *defaultPort;
 
@@ -209,9 +250,11 @@ class Bus : public MemObject
 
     Bus(const std::string &n, int bus_id, int _clock, int _width)
         : MemObject(n), busId(bus_id), clock(_clock), width(_width),
-        tickAddrLastUsed(0), tickDataLastUsed(0), defaultPort(NULL)
+        tickNextIdle(0), busIdle(this), retryingPort(0), defaultPort(NULL)
     {
+        //Both the width and clock period must be positive
         assert(width);
+        assert(clock);
     }
 
 };

From 911381321b294fa5a8d2dd77eaabc7473ffe5e6f Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 17:07:23 -0400
Subject: [PATCH 07/38] Update ref stats: ll/sc, cpu_id, new kernel (?)

--HG--
extra : convert_revision : 060cb7319c4474429917a6347a9a47f390208ec8
---
 .../ref/alpha/linux/o3-timing/m5stats.txt     |   8 +-
 .../00.hello/ref/alpha/linux/o3-timing/stdout |   4 +-
 .../ref/alpha/linux/simple-atomic/config.ini  |   1 +
 .../ref/alpha/linux/simple-atomic/config.out  |   1 +
 .../ref/alpha/linux/simple-atomic/m5stats.txt |   8 +-
 .../ref/alpha/linux/simple-atomic/stdout      |   4 +-
 .../ref/alpha/linux/simple-timing/config.ini  |   1 +
 .../ref/alpha/linux/simple-timing/config.out  |   1 +
 .../ref/alpha/linux/simple-timing/m5stats.txt |   8 +-
 .../ref/alpha/linux/simple-timing/stdout      |   4 +-
 .../ref/alpha/tru64/o3-timing/m5stats.txt     |   8 +-
 .../00.hello/ref/alpha/tru64/o3-timing/stdout |   4 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   1 +
 .../ref/alpha/tru64/simple-atomic/config.out  |   1 +
 .../ref/alpha/tru64/simple-atomic/m5stats.txt |   8 +-
 .../ref/alpha/tru64/simple-atomic/stdout      |   4 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   1 +
 .../ref/alpha/tru64/simple-timing/config.out  |   1 +
 .../ref/alpha/tru64/simple-timing/m5stats.txt |   8 +-
 .../ref/alpha/tru64/simple-timing/stdout      |   4 +-
 .../ref/mips/linux/simple-atomic/config.ini   |   9 +
 .../ref/mips/linux/simple-atomic/config.out   |  12 +
 .../ref/mips/linux/simple-atomic/m5stats.txt  |   8 +-
 .../ref/mips/linux/simple-atomic/stdout       |   4 +-
 .../ref/mips/linux/simple-timing/config.ini   |   9 +
 .../ref/mips/linux/simple-timing/config.out   |  12 +
 .../ref/mips/linux/simple-timing/m5stats.txt  |   8 +-
 .../ref/mips/linux/simple-timing/stdout       |   4 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   9 +
 .../ref/sparc/linux/simple-atomic/config.out  |  12 +
 .../ref/sparc/linux/simple-atomic/m5stats.txt |   8 +-
 .../ref/sparc/linux/simple-atomic/stdout      |   4 +-
 .../ref/alpha/linux/o3-timing/m5stats.txt     |  44 +-
 .../ref/alpha/linux/o3-timing/stdout          |   4 +-
 .../tsunami-simple-atomic-dual/config.ini     |   4 +-
 .../tsunami-simple-atomic-dual/config.out     |   4 +-
 .../console.system.sim_console                |  54 +--
 .../tsunami-simple-atomic-dual/m5stats.txt    | 407 +++++++++--------
 .../linux/tsunami-simple-atomic-dual/stderr   |   8 +-
 .../linux/tsunami-simple-atomic-dual/stdout   |   6 +-
 .../linux/tsunami-simple-atomic/config.ini    |   2 +-
 .../linux/tsunami-simple-atomic/config.out    |   2 +-
 .../console.system.sim_console                |  54 +--
 .../linux/tsunami-simple-atomic/m5stats.txt   | 140 +++---
 .../alpha/linux/tsunami-simple-atomic/stderr  |   4 +-
 .../alpha/linux/tsunami-simple-atomic/stdout  |   6 +-
 .../tsunami-simple-timing-dual/config.ini     |   4 +-
 .../tsunami-simple-timing-dual/config.out     |   4 +-
 .../console.system.sim_console                |  54 +--
 .../tsunami-simple-timing-dual/m5stats.txt    | 409 +++++++++---------
 .../linux/tsunami-simple-timing-dual/stderr   |   8 +-
 .../linux/tsunami-simple-timing-dual/stdout   |   6 +-
 .../linux/tsunami-simple-timing/config.ini    |   2 +-
 .../linux/tsunami-simple-timing/config.out    |   2 +-
 .../console.system.sim_console                |  54 +--
 .../linux/tsunami-simple-timing/m5stats.txt   | 146 +++----
 .../alpha/linux/tsunami-simple-timing/stderr  |   4 +-
 .../alpha/linux/tsunami-simple-timing/stdout  |   6 +-
 .../ref/alpha/eio/simple-atomic/config.ini    |   1 +
 .../ref/alpha/eio/simple-atomic/config.out    |   1 +
 .../ref/alpha/eio/simple-atomic/m5stats.txt   |   6 +-
 .../ref/alpha/eio/simple-atomic/stdout        |   4 +-
 .../ref/alpha/eio/simple-timing/config.ini    |   1 +
 .../ref/alpha/eio/simple-timing/config.out    |   1 +
 .../ref/alpha/eio/simple-timing/m5stats.txt   |  10 +-
 .../ref/alpha/eio/simple-timing/stdout        |   4 +-
 66 files changed, 864 insertions(+), 781 deletions(-)

diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index c2c9affca..b8dbf28af 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    420                       # Nu
 global.BPredUnit.condPredicted                   1302                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         2254                       # Number of BP lookups
 global.BPredUnit.usedRAS                          291                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  47059                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 160380                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                                  57322                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   1748                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 160364                       # Number of bytes of host memory used
+host_seconds                                     3.22                       # Real time elapsed on the host
+host_tick_rate                                   2135                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 12                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               259                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  2049                       # Number of loads inserted to the mem dependence unit.
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 14ef519e9..718827a30 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:34 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:45 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
 Exiting @ tick 6868 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index f7e73950d..7340cc079 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=AtomicSimpleCPU
 children=workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
index 198d7df5e..73f91ff61 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
@@ -44,6 +44,7 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
index e3cd05fb0..875e55644 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  74000                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 148088                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                                  73591                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 172802                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 148116                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                                 170614                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
index e26480539..59f571aaf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 11:12:49
-M5 started Sat Oct  7 11:13:02 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:50 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
 Exiting @ tick 5641 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index cefcf7f11..7b517abc8 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
index 1ed18ff71..5c4c7fb14 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
@@ -83,6 +83,7 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.cpu.dcache
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 97d39456e..757bbb920 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 286207                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159648                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                                 413300                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  98835                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159632                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                 144603                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index a9c37a14d..be8eccb38 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:38 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:50 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
 Exiting @ tick 8316 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index 53d94a43f..41348bbfb 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    222                       # Nu
 global.BPredUnit.condPredicted                    441                       # Number of conditional branches predicted
 global.BPredUnit.lookups                          888                       # Number of BP lookups
 global.BPredUnit.usedRAS                          160                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  45832                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159900                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                  55090                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26386                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159884                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                  31792                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                  9                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                   675                       # Number of loads inserted to the mem dependence unit.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index fa94f7eb9..c51631489 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:40 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:52 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Exiting @ tick 2886 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 34f5c0b32..f248945b1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=AtomicSimpleCPU
 children=workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out
index a474765ae..58ae0d9df 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out
@@ -44,6 +44,7 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
index b120e12b9..e3f845135 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 548861                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147820                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                                 504404                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  60702                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147692                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                                  60102                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2578                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index 0c9b00960..2ee4e0a08 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 11:12:49
-M5 started Sat Oct  7 11:13:09 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:54 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
 Exiting @ tick 2577 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 0d7d34e64..5616cf909 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
index 9b44f8ddd..c76e14e2c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
@@ -83,6 +83,7 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.cpu.dcache
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index 916f9dad8..39ef8ead8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 196989                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159172                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                                 279840                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  69262                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159156                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                                 100319                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2578                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index d152dc89c..27e317357 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:45 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:54 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
 Exiting @ tick 3777 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 2c82b8c1a..fa3ccdf1c 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=AtomicSimpleCPU
 children=workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
@@ -64,6 +65,7 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 mem=system.physmem
+progress_interval=0
 simulate_stalls=false
 system=system
 width=1
@@ -74,11 +76,17 @@ icache_port=system.membus.port[1]
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+egid=100
 env=
+euid=100
 executable=tests/test-progs/hello/bin/mips/linux/hello
+gid=100
 input=cin
 output=cout
+pid=100
+ppid=99
 system=system
+uid=100
 
 [system.membus]
 type=Bus
@@ -94,6 +102,7 @@ port=system.membus.port[0]
 
 [trace]
 bufsize=0
+cycle=0
 dump_on_exit=false
 file=cout
 flags=
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
index 8678c0d97..6ab9c098e 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
@@ -28,6 +28,12 @@ input=cin
 output=cout
 env=
 system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -35,8 +41,10 @@ max_insts_any_thread=0
 max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
+progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
@@ -48,6 +56,7 @@ simulate_stalls=false
 [trace]
 flags=
 start=0
+cycle=0
 bufsize=0
 file=cout
 dump_on_exit=false
@@ -91,3 +100,6 @@ trace_system=client
 [debug]
 break_cycles=
 
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index b70a6ee17..f358a8e52 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  90956                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147380                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                                  90353                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   2733                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147536                       # Number of bytes of host memory used
+host_seconds                                     2.07                       # Real time elapsed on the host
+host_tick_rate                                   2732                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index f5b9c8fd7..4056e38ec 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  5 2006 15:37:09
-M5 started Tue Sep  5 15:46:32 2006
+M5 compiled Oct  8 2006 14:15:37
+M5 started Sun Oct  8 14:15:41 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
 Exiting @ tick 5656 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 040735f2c..af7a1c895 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
@@ -64,6 +65,7 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 mem=system.cpu.dcache
+progress_interval=0
 system=system
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -197,11 +199,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+egid=100
 env=
+euid=100
 executable=tests/test-progs/hello/bin/mips/linux/hello
+gid=100
 input=cin
 output=cout
+pid=100
+ppid=99
 system=system
+uid=100
 
 [system.membus]
 type=Bus
@@ -217,6 +225,7 @@ port=system.membus.port[0]
 
 [trace]
 bufsize=0
+cycle=0
 dump_on_exit=false
 file=cout
 flags=
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
index a7270a97e..ead34bf39 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
@@ -67,6 +67,12 @@ input=cin
 output=cout
 env=
 system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -74,8 +80,10 @@ max_insts_any_thread=0
 max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
+progress_interval=0
 mem=system.cpu.dcache
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
@@ -169,6 +177,7 @@ hit_latency=1
 [trace]
 flags=
 start=0
+cycle=0
 bufsize=0
 file=cout
 dump_on_exit=false
@@ -212,3 +221,6 @@ trace_system=client
 [debug]
 break_cycles=
 
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index bc5ad3cca..ef08c56cd 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 273933                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159012                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                                 403699                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 116093                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 158992                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                                 174583                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 954193ee0..97b24e1ad 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:52:26
-M5 started Sat Oct  7 12:52:42 2006
+M5 compiled Oct  8 2006 14:15:37
+M5 started Sun Oct  8 14:15:43 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Exiting @ tick 8579 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 082415a7f..21028fa63 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=AtomicSimpleCPU
 children=workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
@@ -64,6 +65,7 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 mem=system.physmem
+progress_interval=0
 simulate_stalls=false
 system=system
 width=1
@@ -74,11 +76,17 @@ icache_port=system.membus.port[1]
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+egid=100
 env=
+euid=100
 executable=tests/test-progs/hello/bin/sparc/linux/hello
+gid=100
 input=cin
 output=cout
+pid=100
+ppid=99
 system=system
+uid=100
 
 [system.membus]
 type=Bus
@@ -94,6 +102,7 @@ port=system.membus.port[0]
 
 [trace]
 bufsize=0
+cycle=0
 dump_on_exit=false
 file=cout
 flags=
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out
index 45412a511..f5be4e3bd 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out
@@ -28,6 +28,12 @@ input=cin
 output=cout
 env=
 system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -35,8 +41,10 @@ max_insts_any_thread=0
 max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
+progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
@@ -48,6 +56,7 @@ simulate_stalls=false
 [trace]
 flags=
 start=0
+cycle=0
 bufsize=0
 file=cout
 dump_on_exit=false
@@ -91,3 +100,6 @@ trace_system=client
 [debug]
 break_cycles=
 
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
index 9bfb2fec9..e87e77b8f 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  61348                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147288                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                                  60991                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   2175                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147292                       # Number of bytes of host memory used
+host_seconds                                     2.06                       # Real time elapsed on the host
+host_tick_rate                                   2174                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        4483                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
index 38eb82c8b..c9df3a17c 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  5 2006 15:39:50
-M5 started Tue Sep  5 15:49:24 2006
+M5 compiled Oct  8 2006 14:19:59
+M5 started Sun Oct  8 14:20:03 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
 Exiting @ tick 4482 because target called exit()
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
index a249947ca..15172b43c 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   1081                       # Nu
 global.BPredUnit.condPredicted                   2449                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         4173                       # Number of BP lookups
 global.BPredUnit.usedRAS                          551                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  50082                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 161260                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
-host_tick_rate                                  37535                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  40630                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 161244                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
+host_tick_rate                                  30458                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 41                       # Number of conflicting loads.
 memdepunit.memDep.conflictingLoads                 39                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               194                       # Number of conflicting stores.
@@ -115,7 +115,7 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.088670                       # m
 system.cpu.dcache.WriteReq_mshr_miss_rate_0     0.088670                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses            144                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses_0          144                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets            1                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  11.670554                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
@@ -476,20 +476,20 @@ system.cpu.ipc_1                             0.666272                       # IP
 system.cpu.ipc_total                         1.332425                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    8158                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
-                          (null)            2      0.02%            # Type of FU issued
-                          IntAlu         5514     67.59%            # Type of FU issued
-                         IntMult            1      0.01%            # Type of FU issued
-                          IntDiv            0      0.00%            # Type of FU issued
-                        FloatAdd            2      0.02%            # Type of FU issued
-                        FloatCmp            0      0.00%            # Type of FU issued
-                        FloatCvt            0      0.00%            # Type of FU issued
-                       FloatMult            0      0.00%            # Type of FU issued
-                        FloatDiv            0      0.00%            # Type of FU issued
-                       FloatSqrt            0      0.00%            # Type of FU issued
-                         MemRead         1662     20.37%            # Type of FU issued
-                        MemWrite          977     11.98%            # Type of FU issued
-                       IprAccess            0      0.00%            # Type of FU issued
-                    InstPrefetch            0      0.00%            # Type of FU issued
+(null)                                              2      0.02%            # Type of FU issued
+IntAlu                                           5514     67.59%            # Type of FU issued
+IntMult                                             1      0.01%            # Type of FU issued
+IntDiv                                              0      0.00%            # Type of FU issued
+FloatAdd                                            2      0.02%            # Type of FU issued
+FloatCmp                                            0      0.00%            # Type of FU issued
+FloatCvt                                            0      0.00%            # Type of FU issued
+FloatMult                                           0      0.00%            # Type of FU issued
+FloatDiv                                            0      0.00%            # Type of FU issued
+FloatSqrt                                           0      0.00%            # Type of FU issued
+MemRead                                          1662     20.37%            # Type of FU issued
+MemWrite                                          977     11.98%            # Type of FU issued
+IprAccess                                           0      0.00%            # Type of FU issued
+InstPrefetch                                        0      0.00%            # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.end_dist
 system.cpu.iq.ISSUE:FU_type_1                    8090                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_1.start_dist
@@ -610,7 +610,7 @@ system.cpu.l2cache.demand_avg_miss_latency_0     2.059561
 system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0>                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency_0            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0>                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_1     no value                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      9                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits_0                    9                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits_1                    0                       # number of demand (read+write) hits
@@ -619,7 +619,7 @@ system.cpu.l2cache.demand_miss_latency_0         1971                       # nu
 system.cpu.l2cache.demand_miss_latency_1            0                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.990683                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate_0        0.990683                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_1        no value                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_1    <err: div-0>                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  957                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses_0                957                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses_1                  0                       # number of demand (read+write) misses
@@ -631,7 +631,7 @@ system.cpu.l2cache.demand_mshr_miss_latency_0          957
 system.cpu.l2cache.demand_mshr_miss_latency_1            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.990683                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate_0     0.990683                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_1     no value                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             957                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses_0           957                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses_1             0                       # number of demand (read+write) MSHR misses
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
index be25795fb..6b640d359 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:47 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:56 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
 Exiting @ tick 8441 because target called exit()
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 3d719c501..401611d58 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -75,7 +75,7 @@ side_b=system.membus.port[0]
 type=AtomicSimpleCPU
 children=dtb itb
 clock=1
-cpu_id=-1
+cpu_id=0
 defer_registration=false
 dtb=system.cpu0.dtb
 function_trace=false
@@ -106,7 +106,7 @@ size=48
 type=AtomicSimpleCPU
 children=dtb itb
 clock=1
-cpu_id=-1
+cpu_id=1
 defer_registration=false
 dtb=system.cpu1.dtb
 function_trace=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
index b8290213e..1d4d50845 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
@@ -90,9 +90,9 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 itb=system.cpu0.itb
 dtb=system.cpu0.dtb
-cpu_id=-1
 profile=0
 clock=1
 defer_registration=false
@@ -118,9 +118,9 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=1
 itb=system.cpu1.itb
 dtb=system.cpu1.dtb
-cpu_id=-1
 profile=0
 clock=1
 defer_registration=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
index 4a397ddbf..57a610390 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 2 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -16,29 +16,27 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
 
unix_boot_mem ends at FFFFFC0000078000 
 
k_argc = 0 
-
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
-
CallbackFixup 0 18000, t7=FFFFFC0000700000
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
 
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
-
Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
 
memcluster 0, usage 1, start        0, end      392
 
memcluster 1, usage 0, start      392, end    16384
-
freeing pages 1030:16384
-
reserving pages 1030:1031
+
freeing pages 1069:16384
+
reserving pages 1069:1070
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
-
PID hash table entries: 1024 (order 10: 16384 bytes)
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
 
Using epoch = 1900
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
-
Mount-cache hash table entries: 512 (order: 0, 8192 bytes)
-
per-CPU timeslice cutoff: 374.49 usecs.
-
task migration cache decay timeout: 0 msecs.
+
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
 
Slave CPU 1 console command START
 SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
@@ -53,16 +51,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
Initializing Cryptographic API
 
rtc: Standard PC (1900) epoch (1900) detected
 
Real Time Clock Driver v1.12
-
Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
 
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
 
loop: loaded (max 8 devices)
-
Using anticipatory io scheduler
 
nbd: registered device at major 43
 
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
ns83820: irq bound to CPU 1
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
-
eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
 
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
 
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
@@ -75,24 +80,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
 
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
 
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
 
 hdb: unknown partition table
-
scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
-
  Vendor: Linux     Model: scsi_m5       Li  Rev: 0004
-
  Type:   Direct-Access                      ANSI SCSI revision: 03
-
SCSI device sda: 16384 512-byte hdwr sectors (8 MB)
-
SCSI device sda: drive cache: write back
-
 sda: unknown partition table
-
Attached scsi disk sda at scsi0, channel 0, id 0, lun 0
 
mice: PS/2 mouse device common for all mice
 
NET: Registered protocol family 2
-
IP: routing cache hash table of 1024 buckets, 16Kbytes
-
TCP: Hash tables configured (established 8192 bind 8192)
-
ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
 
ip_tables: (C) 2000-2002 Netfilter core team
 
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
 
Initializing IPsec netlink socket
 
NET: Registered protocol family 1
 
NET: Registered protocol family 17
@@ -101,7 +105,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
-
Freeing unused kernel memory: 480k freed
+
Freeing unused kernel memory: 224k freed
 

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
 mounting filesystems...
 loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index 376929ebb..537721d92 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,232 +1,225 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1361363                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194440                       # Number of bytes of host memory used
-host_seconds                                    45.04                       # Real time elapsed on the host
-host_tick_rate                               78691874                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1292093                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197872                       # Number of bytes of host memory used
+host_seconds                                    51.53                       # Real time elapsed on the host
+host_tick_rate                               72118724                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    61314617                       # Number of instructions simulated
-sim_seconds                                  1.772124                       # Number of seconds simulated
-sim_ticks                                  3544247159                       # Number of ticks simulated
-system.cpu0.dtb.accesses                      1850344                       # DTB accesses
-system.cpu0.dtb.acv                               301                       # DTB access violations
-system.cpu0.dtb.hits                         12691711                       # DTB hits
-system.cpu0.dtb.misses                           8349                       # DTB misses
-system.cpu0.dtb.read_accesses                  509385                       # DTB read accesses
-system.cpu0.dtb.read_acv                          184                       # DTB read access violations
-system.cpu0.dtb.read_hits                     7018751                       # DTB read hits
-system.cpu0.dtb.read_misses                      6579                       # DTB read misses
-system.cpu0.dtb.write_accesses                1340959                       # DTB write accesses
-system.cpu0.dtb.write_acv                         117                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5672960                       # DTB write hits
-system.cpu0.dtb.write_misses                     1770                       # DTB write misses
-system.cpu0.idle_fraction                    0.984893                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      1981604                       # ITB accesses
-system.cpu0.itb.acv                               161                       # ITB acv
-system.cpu0.itb.hits                          1978255                       # ITB hits
-system.cpu0.itb.misses                           3349                       # ITB misses
-system.cpu0.kern.callpal                       176688                       # number of callpals executed
+sim_insts                                    66579941                       # Number of instructions simulated
+sim_seconds                                  1.858108                       # Number of seconds simulated
+sim_ticks                                  3716216351                       # Number of ticks simulated
+system.cpu0.dtb.accesses                       604194                       # DTB accesses
+system.cpu0.dtb.acv                               337                       # DTB access violations
+system.cpu0.dtb.hits                         12597930                       # DTB hits
+system.cpu0.dtb.misses                           7857                       # DTB misses
+system.cpu0.dtb.read_accesses                  426113                       # DTB read accesses
+system.cpu0.dtb.read_acv                          210                       # DTB read access violations
+system.cpu0.dtb.read_hits                     7793080                       # DTB read hits
+system.cpu0.dtb.read_misses                      7107                       # DTB read misses
+system.cpu0.dtb.write_accesses                 178081                       # DTB write accesses
+system.cpu0.dtb.write_acv                         127                       # DTB write access violations
+system.cpu0.dtb.write_hits                    4804850                       # DTB write hits
+system.cpu0.dtb.write_misses                      750                       # DTB write misses
+system.cpu0.idle_fraction                    0.986701                       # Percentage of idle cycles
+system.cpu0.itb.accesses                      1567177                       # ITB accesses
+system.cpu0.itb.acv                               184                       # ITB acv
+system.cpu0.itb.hits                          1563535                       # ITB hits
+system.cpu0.itb.misses                           3642                       # ITB misses
+system.cpu0.kern.callpal                       140535                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir                    97      0.05%      0.06% # number of callpals executed
-system.cpu0.kern.callpal_wrmces                     1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal_wrfen                      1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal_swpctx                  1117      0.63%      0.69% # number of callpals executed
-system.cpu0.kern.callpal_tbi                       44      0.02%      0.71% # number of callpals executed
-system.cpu0.kern.callpal_wrent                      7      0.00%      0.72% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                166811     94.41%     95.13% # number of callpals executed
-system.cpu0.kern.callpal_rdps                    4911      2.78%     97.91% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.91% # number of callpals executed
-system.cpu0.kern.callpal_wrusp                      3      0.00%     97.91% # number of callpals executed
-system.cpu0.kern.callpal_rdusp                      9      0.01%     97.91% # number of callpals executed
-system.cpu0.kern.callpal_whami                      2      0.00%     97.92% # number of callpals executed
-system.cpu0.kern.callpal_rti                     3236      1.83%     99.75% # number of callpals executed
-system.cpu0.kern.callpal_callsys                  325      0.18%     99.93% # number of callpals executed
-system.cpu0.kern.callpal_imb                      121      0.07%    100.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir                   567      0.40%      0.40% # number of callpals executed
+system.cpu0.kern.callpal_wrmces                     1      0.00%      0.40% # number of callpals executed
+system.cpu0.kern.callpal_wrfen                      1      0.00%      0.41% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.41% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  2926      2.08%      2.49% # number of callpals executed
+system.cpu0.kern.callpal_tbi                       49      0.03%      2.52% # number of callpals executed
+system.cpu0.kern.callpal_wrent                      7      0.00%      2.53% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                126411     89.95%     92.48% # number of callpals executed
+system.cpu0.kern.callpal_rdps                    5784      4.12%     96.59% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.59% # number of callpals executed
+system.cpu0.kern.callpal_wrusp                      2      0.00%     96.60% # number of callpals executed
+system.cpu0.kern.callpal_rdusp                      9      0.01%     96.60% # number of callpals executed
+system.cpu0.kern.callpal_whami                      2      0.00%     96.60% # number of callpals executed
+system.cpu0.kern.callpal_rti                     4273      3.04%     99.64% # number of callpals executed
+system.cpu0.kern.callpal_callsys                  366      0.26%     99.90% # number of callpals executed
+system.cpu0.kern.callpal_imb                      134      0.10%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    190918                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    155157                       # number of hwrei instructions executed
 system.cpu0.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu0.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu0.kern.inst.quiesce                    1922                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count                     172116                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    72060     41.87%     41.87% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21                     251      0.15%     42.01% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22                    5518      3.21%     45.22% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30                       7      0.00%     45.22% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                   94280     54.78%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      153515                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     72019     46.91%     46.91% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21                      251      0.16%     47.08% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22                     5518      3.59%     50.67% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30                        7      0.00%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    75720     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks                 3543835079                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0               3521923327     99.38%     99.38% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21                   39982      0.00%     99.38% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22                 1005040      0.03%     99.41% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30                    1756      0.00%     99.41% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31                20864974      0.59%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used                    0.891928                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_0                  0.999431                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6712                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     133285                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    53228     39.94%     39.94% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21                     245      0.18%     40.12% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22                    1895      1.42%     41.54% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30                     460      0.35%     41.89% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31                   77457     58.11%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      107676                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     52768     49.01%     49.01% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21                      245      0.23%     49.23% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22                     1895      1.76%     50.99% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30                      460      0.43%     51.42% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    52308     48.58%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks                 3716215936                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0               3683825506     99.13%     99.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21                   40474      0.00%     99.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22                  162970      0.00%     99.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                  103364      0.00%     99.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31                32083622      0.86%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used                    0.807863                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_0                  0.991358                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.803140                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel                1277                      
-system.cpu0.kern.mode_good_user                  1129                      
-system.cpu0.kern.mode_good_idle                   148                      
-system.cpu0.kern.mode_switch_kernel              2253                       # number of protection mode switches
-system.cpu0.kern.mode_switch_user                1129                       # number of protection mode switches
-system.cpu0.kern.mode_switch_idle                2074                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good            0.468109                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.566800                       # fraction of useful protection mode switches
+system.cpu0.kern.ipl_used_31                 0.675317                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel                1221                      
+system.cpu0.kern.mode_good_user                  1222                      
+system.cpu0.kern.mode_good_idle                     0                      
+system.cpu0.kern.mode_switch_kernel              6758                       # number of protection mode switches
+system.cpu0.kern.mode_switch_user                1222                       # number of protection mode switches
+system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
+system.cpu0.kern.mode_switch_good            0.306140                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.180675                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_idle       0.071360                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel           28710240      0.81%      0.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user              2184201      0.06%      0.87% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_idle           3512891779     99.13%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    1118                       # number of times the context was actually changed
-system.cpu0.kern.syscall                          192                       # number of syscalls executed
-system.cpu0.kern.syscall_fork                       7      3.65%      3.65% # number of syscalls executed
-system.cpu0.kern.syscall_read                      13      6.77%     10.42% # number of syscalls executed
-system.cpu0.kern.syscall_write                      4      2.08%     12.50% # number of syscalls executed
-system.cpu0.kern.syscall_close                     28     14.58%     27.08% # number of syscalls executed
-system.cpu0.kern.syscall_chdir                      1      0.52%     27.60% # number of syscalls executed
-system.cpu0.kern.syscall_obreak                     7      3.65%     31.25% # number of syscalls executed
-system.cpu0.kern.syscall_lseek                      6      3.12%     34.37% # number of syscalls executed
-system.cpu0.kern.syscall_getpid                     4      2.08%     36.46% # number of syscalls executed
-system.cpu0.kern.syscall_setuid                     1      0.52%     36.98% # number of syscalls executed
-system.cpu0.kern.syscall_getuid                     3      1.56%     38.54% # number of syscalls executed
-system.cpu0.kern.syscall_access                     7      3.65%     42.19% # number of syscalls executed
-system.cpu0.kern.syscall_dup                        2      1.04%     43.23% # number of syscalls executed
-system.cpu0.kern.syscall_open                      34     17.71%     60.94% # number of syscalls executed
-system.cpu0.kern.syscall_getgid                     3      1.56%     62.50% # number of syscalls executed
-system.cpu0.kern.syscall_sigprocmask                8      4.17%     66.67% # number of syscalls executed
-system.cpu0.kern.syscall_ioctl                      9      4.69%     71.35% # number of syscalls executed
-system.cpu0.kern.syscall_readlink                   1      0.52%     71.87% # number of syscalls executed
-system.cpu0.kern.syscall_execve                     5      2.60%     74.48% # number of syscalls executed
-system.cpu0.kern.syscall_mmap                      22     11.46%     85.94% # number of syscalls executed
-system.cpu0.kern.syscall_munmap                     2      1.04%     86.98% # number of syscalls executed
-system.cpu0.kern.syscall_mprotect                   6      3.12%     90.10% # number of syscalls executed
-system.cpu0.kern.syscall_gethostname                1      0.52%     90.62% # number of syscalls executed
-system.cpu0.kern.syscall_dup2                       2      1.04%     91.67% # number of syscalls executed
-system.cpu0.kern.syscall_fcntl                      8      4.17%     95.83% # number of syscalls executed
-system.cpu0.kern.syscall_socket                     2      1.04%     96.87% # number of syscalls executed
-system.cpu0.kern.syscall_connect                    2      1.04%     97.92% # number of syscalls executed
-system.cpu0.kern.syscall_setgid                     1      0.52%     98.44% # number of syscalls executed
-system.cpu0.kern.syscall_getrlimit                  1      0.52%     98.96% # number of syscalls executed
-system.cpu0.kern.syscall_setsid                     2      1.04%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.015107                       # Percentage of non-idle cycles
-system.cpu0.numCycles                        53543489                       # number of cpu cycles simulated
-system.cpu0.num_insts                        53539979                       # Number of instructions executed
-system.cpu0.num_refs                         12727196                       # Number of memory references
-system.cpu1.dtb.accesses                       460215                       # DTB accesses
-system.cpu1.dtb.acv                                72                       # DTB access violations
-system.cpu1.dtb.hits                          2012555                       # DTB hits
-system.cpu1.dtb.misses                           4236                       # DTB misses
-system.cpu1.dtb.read_accesses                  319867                       # DTB read accesses
-system.cpu1.dtb.read_acv                           26                       # DTB read access violations
-system.cpu1.dtb.read_hits                     1276251                       # DTB read hits
-system.cpu1.dtb.read_misses                      3800                       # DTB read misses
-system.cpu1.dtb.write_accesses                 140348                       # DTB write accesses
-system.cpu1.dtb.write_acv                          46                       # DTB write access violations
-system.cpu1.dtb.write_hits                     736304                       # DTB write hits
-system.cpu1.dtb.write_misses                      436                       # DTB write misses
-system.cpu1.idle_fraction                    0.997806                       # Percentage of idle cycles
-system.cpu1.itb.accesses                      1302484                       # ITB accesses
-system.cpu1.itb.acv                                23                       # ITB acv
-system.cpu1.itb.hits                          1300768                       # ITB hits
-system.cpu1.itb.misses                           1716                       # ITB misses
-system.cpu1.kern.callpal                        27118                       # number of callpals executed
+system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel         3714429703     99.95%     99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user              1786231      0.05%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    2927                       # number of times the context was actually changed
+system.cpu0.kern.syscall                          217                       # number of syscalls executed
+system.cpu0.kern.syscall_fork                       8      3.69%      3.69% # number of syscalls executed
+system.cpu0.kern.syscall_read                      19      8.76%     12.44% # number of syscalls executed
+system.cpu0.kern.syscall_write                      3      1.38%     13.82% # number of syscalls executed
+system.cpu0.kern.syscall_close                     31     14.29%     28.11% # number of syscalls executed
+system.cpu0.kern.syscall_chdir                      1      0.46%     28.57% # number of syscalls executed
+system.cpu0.kern.syscall_obreak                     6      2.76%     31.34% # number of syscalls executed
+system.cpu0.kern.syscall_lseek                     10      4.61%     35.94% # number of syscalls executed
+system.cpu0.kern.syscall_getpid                     6      2.76%     38.71% # number of syscalls executed
+system.cpu0.kern.syscall_setuid                     2      0.92%     39.63% # number of syscalls executed
+system.cpu0.kern.syscall_getuid                     4      1.84%     41.47% # number of syscalls executed
+system.cpu0.kern.syscall_access                     6      2.76%     44.24% # number of syscalls executed
+system.cpu0.kern.syscall_dup                        2      0.92%     45.16% # number of syscalls executed
+system.cpu0.kern.syscall_open                      33     15.21%     60.37% # number of syscalls executed
+system.cpu0.kern.syscall_getgid                     4      1.84%     62.21% # number of syscalls executed
+system.cpu0.kern.syscall_sigprocmask               10      4.61%     66.82% # number of syscalls executed
+system.cpu0.kern.syscall_ioctl                      9      4.15%     70.97% # number of syscalls executed
+system.cpu0.kern.syscall_execve                     6      2.76%     73.73% # number of syscalls executed
+system.cpu0.kern.syscall_mmap                      25     11.52%     85.25% # number of syscalls executed
+system.cpu0.kern.syscall_munmap                     3      1.38%     86.64% # number of syscalls executed
+system.cpu0.kern.syscall_mprotect                   7      3.23%     89.86% # number of syscalls executed
+system.cpu0.kern.syscall_gethostname                1      0.46%     90.32% # number of syscalls executed
+system.cpu0.kern.syscall_dup2                       3      1.38%     91.71% # number of syscalls executed
+system.cpu0.kern.syscall_fcntl                      8      3.69%     95.39% # number of syscalls executed
+system.cpu0.kern.syscall_socket                     2      0.92%     96.31% # number of syscalls executed
+system.cpu0.kern.syscall_connect                    2      0.92%     97.24% # number of syscalls executed
+system.cpu0.kern.syscall_setgid                     2      0.92%     98.16% # number of syscalls executed
+system.cpu0.kern.syscall_getrlimit                  2      0.92%     99.08% # number of syscalls executed
+system.cpu0.kern.syscall_setsid                     2      0.92%    100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction                0.013299                       # Percentage of non-idle cycles
+system.cpu0.numCycles                        49421041                       # number of cpu cycles simulated
+system.cpu0.num_insts                        49417215                       # Number of instructions executed
+system.cpu0.num_refs                         12829669                       # Number of memory references
+system.cpu1.dtb.accesses                       701326                       # DTB accesses
+system.cpu1.dtb.acv                                30                       # DTB access violations
+system.cpu1.dtb.hits                          5286923                       # DTB hits
+system.cpu1.dtb.misses                           3658                       # DTB misses
+system.cpu1.dtb.read_accesses                  474933                       # DTB read accesses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_hits                     3100008                       # DTB read hits
+system.cpu1.dtb.read_misses                      3260                       # DTB read misses
+system.cpu1.dtb.write_accesses                 226393                       # DTB write accesses
+system.cpu1.dtb.write_acv                          30                       # DTB write access violations
+system.cpu1.dtb.write_hits                    2186915                       # DTB write hits
+system.cpu1.dtb.write_misses                      398                       # DTB write misses
+system.cpu1.idle_fraction                    0.995381                       # Percentage of idle cycles
+system.cpu1.itb.accesses                      1714255                       # ITB accesses
+system.cpu1.itb.acv                                 0                       # ITB acv
+system.cpu1.itb.hits                          1712856                       # ITB hits
+system.cpu1.itb.misses                           1399                       # ITB misses
+system.cpu1.kern.callpal                        81795                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir                     7      0.03%      0.03% # number of callpals executed
-system.cpu1.kern.callpal_wrmces                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal_wrfen                      1      0.00%      0.04% # number of callpals executed
-system.cpu1.kern.callpal_swpctx                   515      1.90%      1.94% # number of callpals executed
-system.cpu1.kern.callpal_tbi                       10      0.04%      1.97% # number of callpals executed
-system.cpu1.kern.callpal_wrent                      7      0.03%      2.00% # number of callpals executed
-system.cpu1.kern.callpal_swpipl                 23496     86.64%     88.64% # number of callpals executed
-system.cpu1.kern.callpal_rdps                     251      0.93%     89.57% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp                      1      0.00%     89.57% # number of callpals executed
-system.cpu1.kern.callpal_wrusp                      4      0.01%     89.59% # number of callpals executed
-system.cpu1.kern.callpal_rdusp                      1      0.00%     89.59% # number of callpals executed
-system.cpu1.kern.callpal_whami                      3      0.01%     89.60% # number of callpals executed
-system.cpu1.kern.callpal_rti                     2552      9.41%     99.01% # number of callpals executed
-system.cpu1.kern.callpal_callsys                  208      0.77%     99.78% # number of callpals executed
-system.cpu1.kern.callpal_imb                       59      0.22%    100.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir                   460      0.56%      0.56% # number of callpals executed
+system.cpu1.kern.callpal_wrmces                     1      0.00%      0.56% # number of callpals executed
+system.cpu1.kern.callpal_wrfen                      1      0.00%      0.57% # number of callpals executed
+system.cpu1.kern.callpal_swpctx                  2245      2.74%      3.31% # number of callpals executed
+system.cpu1.kern.callpal_tbi                        4      0.00%      3.32% # number of callpals executed
+system.cpu1.kern.callpal_wrent                      7      0.01%      3.32% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 71908     87.91%     91.24% # number of callpals executed
+system.cpu1.kern.callpal_rdps                    3034      3.71%     94.95% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.95% # number of callpals executed
+system.cpu1.kern.callpal_wrusp                      5      0.01%     94.95% # number of callpals executed
+system.cpu1.kern.callpal_whami                      3      0.00%     94.96% # number of callpals executed
+system.cpu1.kern.callpal_rti                     3913      4.78%     99.74% # number of callpals executed
+system.cpu1.kern.callpal_callsys                  165      0.20%     99.94% # number of callpals executed
+system.cpu1.kern.callpal_imb                       46      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     35069                       # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei                     89345                       # number of hwrei instructions executed
 system.cpu1.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu1.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu1.kern.inst.quiesce                    1947                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count                      27951                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0                    10084     36.08%     36.08% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22                    5485     19.62%     55.70% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30                      97      0.35%     56.05% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31                   12285     43.95%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good                       27484                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0                     10061     36.61%     36.61% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22                     5485     19.96%     56.56% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30                       97      0.35%     56.92% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31                    11841     43.08%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks                 3544246744                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0               3521927913     99.37%     99.37% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22                 1037048      0.03%     99.40% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30                   25211      0.00%     99.40% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31                21256572      0.60%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used                    0.983292                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_0                  0.997719                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2592                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count                      78283                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                    30809     39.36%     39.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22                    1894      2.42%     41.78% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30                     567      0.72%     42.50% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31                   45013     57.50%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       61674                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                     29890     48.46%     48.46% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22                     1894      3.07%     51.54% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30                      567      0.92%     52.45% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                    29323     47.55%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks                 3715795413                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0               3690163762     99.31%     99.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22                  162884      0.00%     99.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30                  130370      0.00%     99.32% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31                25338397      0.68%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used                    0.787834                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0                  0.970171                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31                 0.963858                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel                 636                      
-system.cpu1.kern.mode_good_user                   637                      
-system.cpu1.kern.mode_good_idle                     0                      
-system.cpu1.kern.mode_switch_kernel              3063                       # number of protection mode switches
-system.cpu1.kern.mode_switch_user                 637                       # number of protection mode switches
-system.cpu1.kern.mode_switch_idle                   0                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good            0.344054                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel     0.207640                       # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31                 0.651434                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel                1028                      
+system.cpu1.kern.mode_good_user                   535                      
+system.cpu1.kern.mode_good_idle                   493                      
+system.cpu1.kern.mode_switch_kernel              2307                       # number of protection mode switches
+system.cpu1.kern.mode_switch_user                 535                       # number of protection mode switches
+system.cpu1.kern.mode_switch_idle                2948                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good            0.355095                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel     0.445600                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel         3542834137     99.96%     99.96% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user              1412605      0.04%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     516                       # number of times the context was actually changed
-system.cpu1.kern.syscall                          137                       # number of syscalls executed
-system.cpu1.kern.syscall_fork                       1      0.73%      0.73% # number of syscalls executed
-system.cpu1.kern.syscall_read                      17     12.41%     13.14% # number of syscalls executed
-system.cpu1.kern.syscall_close                     15     10.95%     24.09% # number of syscalls executed
-system.cpu1.kern.syscall_chmod                      1      0.73%     24.82% # number of syscalls executed
-system.cpu1.kern.syscall_obreak                     8      5.84%     30.66% # number of syscalls executed
-system.cpu1.kern.syscall_lseek                      4      2.92%     33.58% # number of syscalls executed
-system.cpu1.kern.syscall_getpid                     2      1.46%     35.04% # number of syscalls executed
-system.cpu1.kern.syscall_setuid                     3      2.19%     37.23% # number of syscalls executed
-system.cpu1.kern.syscall_getuid                     3      2.19%     39.42% # number of syscalls executed
-system.cpu1.kern.syscall_access                     4      2.92%     42.34% # number of syscalls executed
-system.cpu1.kern.syscall_open                      21     15.33%     57.66% # number of syscalls executed
-system.cpu1.kern.syscall_getgid                     3      2.19%     59.85% # number of syscalls executed
-system.cpu1.kern.syscall_sigprocmask                2      1.46%     61.31% # number of syscalls executed
-system.cpu1.kern.syscall_ioctl                      1      0.73%     62.04% # number of syscalls executed
-system.cpu1.kern.syscall_execve                     2      1.46%     63.50% # number of syscalls executed
-system.cpu1.kern.syscall_mmap                      32     23.36%     86.86% # number of syscalls executed
-system.cpu1.kern.syscall_munmap                     1      0.73%     87.59% # number of syscalls executed
-system.cpu1.kern.syscall_mprotect                  10      7.30%     94.89% # number of syscalls executed
-system.cpu1.kern.syscall_dup2                       1      0.73%     95.62% # number of syscalls executed
-system.cpu1.kern.syscall_fcntl                      2      1.46%     97.08% # number of syscalls executed
-system.cpu1.kern.syscall_setgid                     3      2.19%     99.27% # number of syscalls executed
-system.cpu1.kern.syscall_getrlimit                  1      0.73%    100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction                0.002194                       # Percentage of non-idle cycles
-system.cpu1.numCycles                         7776377                       # number of cpu cycles simulated
-system.cpu1.num_insts                         7774638                       # Number of instructions executed
-system.cpu1.num_refs                          2025195                       # Number of memory references
+system.cpu1.kern.mode_switch_good_idle       0.167232                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel           12634755      0.34%      0.34% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user              1807179      0.05%      0.39% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle           3700889452     99.61%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2246                       # number of times the context was actually changed
+system.cpu1.kern.syscall                          112                       # number of syscalls executed
+system.cpu1.kern.syscall_read                      11      9.82%      9.82% # number of syscalls executed
+system.cpu1.kern.syscall_write                      1      0.89%     10.71% # number of syscalls executed
+system.cpu1.kern.syscall_close                     12     10.71%     21.43% # number of syscalls executed
+system.cpu1.kern.syscall_chmod                      1      0.89%     22.32% # number of syscalls executed
+system.cpu1.kern.syscall_obreak                     9      8.04%     30.36% # number of syscalls executed
+system.cpu1.kern.syscall_setuid                     2      1.79%     32.14% # number of syscalls executed
+system.cpu1.kern.syscall_getuid                     2      1.79%     33.93% # number of syscalls executed
+system.cpu1.kern.syscall_access                     5      4.46%     38.39% # number of syscalls executed
+system.cpu1.kern.syscall_open                      22     19.64%     58.04% # number of syscalls executed
+system.cpu1.kern.syscall_getgid                     2      1.79%     59.82% # number of syscalls executed
+system.cpu1.kern.syscall_ioctl                      1      0.89%     60.71% # number of syscalls executed
+system.cpu1.kern.syscall_readlink                   1      0.89%     61.61% # number of syscalls executed
+system.cpu1.kern.syscall_execve                     1      0.89%     62.50% # number of syscalls executed
+system.cpu1.kern.syscall_mmap                      29     25.89%     88.39% # number of syscalls executed
+system.cpu1.kern.syscall_mprotect                   9      8.04%     96.43% # number of syscalls executed
+system.cpu1.kern.syscall_fcntl                      2      1.79%     98.21% # number of syscalls executed
+system.cpu1.kern.syscall_setgid                     2      1.79%    100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction                0.004619                       # Percentage of non-idle cycles
+system.cpu1.numCycles                        17164125                       # number of cpu cycles simulated
+system.cpu1.num_insts                        17162726                       # Number of instructions executed
+system.cpu1.num_refs                          5316705                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2735104                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 306                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        412                       # Number of DMA write transactions.
+system.disk0.dma_write_bytes                  2702336                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages                 302                       # Number of full page size DMA writes.
+system.disk0.dma_write_txs                        408                       # Number of DMA write transactions.
 system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
index fe3ad68ab..d55b33424 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
@@ -1,6 +1,6 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
 warn: Entering event queue @ 0.  Starting simulation...
-warn: 195722: Trying to launch CPU number 1!
+warn: 195723: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index 039088577..76bd8d3c2 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  5 2006 22:13:02
-M5 started Fri Oct  6 00:24:12 2006
+M5 compiled Oct  8 2006 14:07:02
+M5 started Sun Oct  8 14:07:57 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
-Exiting @ tick 3544247159 because m5_exit instruction encountered
+Exiting @ tick 3716216351 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index e30428078..bdd7566bc 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -75,7 +75,7 @@ side_b=system.membus.port[0]
 type=AtomicSimpleCPU
 children=dtb itb
 clock=1
-cpu_id=-1
+cpu_id=0
 defer_registration=false
 dtb=system.cpu.dtb
 function_trace=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
index ea63dce8b..bc2f45a5e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
@@ -90,9 +90,9 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 itb=system.cpu.itb
 dtb=system.cpu.dtb
-cpu_id=-1
 profile=0
 clock=1
 defer_registration=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
index d6e3955cc..1d150a047 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 1 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -14,28 +14,26 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
 
unix_boot_mem ends at FFFFFC0000076000 
 
k_argc = 0 
-
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
-
CallbackFixup 0 18000, t7=FFFFFC0000700000
-
Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
 
memcluster 0, usage 1, start        0, end      392
 
memcluster 1, usage 0, start      392, end    16384
-
freeing pages 1030:16384
-
reserving pages 1030:1031
+
freeing pages 1069:16384
+
reserving pages 1069:1070
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
-
PID hash table entries: 1024 (order 10: 16384 bytes)
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
 
Using epoch = 1900
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
-
Mount-cache hash table entries: 512 (order: 0, 8192 bytes)
-
per-CPU timeslice cutoff: 374.49 usecs.
-
task migration cache decay timeout: 0 msecs.
+
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
 
SMP mode deactivated.
 
Brought up 1 CPUs
 
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
@@ -48,16 +46,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Initializing Cryptographic API
 
rtc: Standard PC (1900) epoch (1900) detected
 
Real Time Clock Driver v1.12
-
Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
 
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
 
loop: loaded (max 8 devices)
-
Using anticipatory io scheduler
 
nbd: registered device at major 43
 
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
ns83820: irq bound to CPU 0
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
-
eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
 
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
 
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
@@ -70,24 +75,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
 
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
 
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
 
 hdb: unknown partition table
-
scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
-
  Vendor: Linux     Model: scsi_m5       Li  Rev: 0004
-
  Type:   Direct-Access                      ANSI SCSI revision: 03
-
SCSI device sda: 16384 512-byte hdwr sectors (8 MB)
-
SCSI device sda: drive cache: write back
-
 sda: unknown partition table
-
Attached scsi disk sda at scsi0, channel 0, id 0, lun 0
 
mice: PS/2 mouse device common for all mice
 
NET: Registered protocol family 2
-
IP: routing cache hash table of 1024 buckets, 16Kbytes
-
TCP: Hash tables configured (established 8192 bind 8192)
-
ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
 
ip_tables: (C) 2000-2002 Netfilter core team
 
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
 
Initializing IPsec netlink socket
 
NET: Registered protocol family 1
 
NET: Registered protocol family 17
@@ -96,7 +100,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
-
Freeing unused kernel memory: 480k freed
+
Freeing unused kernel memory: 224k freed
 

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
 mounting filesystems...
 loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index 5c403c0a9..c9661f182 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,86 +1,86 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1121378                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194272                       # Number of bytes of host memory used
-host_seconds                                    51.72                       # Real time elapsed on the host
-host_tick_rate                               67313414                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1269893                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197712                       # Number of bytes of host memory used
+host_seconds                                    48.70                       # Real time elapsed on the host
+host_tick_rate                               74667785                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    58001813                       # Number of instructions simulated
-sim_seconds                                  1.740863                       # Number of seconds simulated
-sim_ticks                                  3481726167                       # Number of ticks simulated
-system.cpu.dtb.accesses                       2309470                       # DTB accesses
+sim_insts                                    61839827                       # Number of instructions simulated
+sim_seconds                                  1.818060                       # Number of seconds simulated
+sim_ticks                                  3636120569                       # Number of ticks simulated
+system.cpu.dtb.accesses                       1304498                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          13711941                       # DTB hits
-system.cpu.dtb.misses                           12493                       # DTB misses
-system.cpu.dtb.read_accesses                   828530                       # DTB read accesses
+system.cpu.dtb.hits                          16565944                       # DTB hits
+system.cpu.dtb.misses                           11425                       # DTB misses
+system.cpu.dtb.read_accesses                   900427                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      7597829                       # DTB read hits
-system.cpu.dtb.read_misses                      10298                       # DTB read misses
-system.cpu.dtb.write_accesses                 1480940                       # DTB write accesses
+system.cpu.dtb.read_hits                     10044011                       # DTB read hits
+system.cpu.dtb.read_misses                      10280                       # DTB read misses
+system.cpu.dtb.write_accesses                  404071                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6114112                       # DTB write hits
-system.cpu.dtb.write_misses                      2195                       # DTB write misses
-system.cpu.idle_fraction                     0.983340                       # Percentage of idle cycles
-system.cpu.itb.accesses                       3281346                       # ITB accesses
+system.cpu.dtb.write_hits                     6521933                       # DTB write hits
+system.cpu.dtb.write_misses                      1145                       # DTB write misses
+system.cpu.idle_fraction                     0.982991                       # Percentage of idle cycles
+system.cpu.itb.accesses                       3281310                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           3276356                       # ITB hits
+system.cpu.itb.hits                           3276320                       # ITB hits
 system.cpu.itb.misses                            4990                       # ITB misses
-system.cpu.kern.callpal                        182718                       # number of callpals executed
+system.cpu.kern.callpal                        193942                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx                   1574      0.86%      0.86% # number of callpals executed
-system.cpu.kern.callpal_tbi                        54      0.03%      0.89% # number of callpals executed
-system.cpu.kern.callpal_wrent                       7      0.00%      0.90% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 171359     93.78%     94.68% # number of callpals executed
-system.cpu.kern.callpal_rdps                     5159      2.82%     97.50% # number of callpals executed
-system.cpu.kern.callpal_wrkgp                       1      0.00%     97.50% # number of callpals executed
-system.cpu.kern.callpal_wrusp                       7      0.00%     97.51% # number of callpals executed
-system.cpu.kern.callpal_rdusp                      10      0.01%     97.51% # number of callpals executed
-system.cpu.kern.callpal_whami                       2      0.00%     97.51% # number of callpals executed
-system.cpu.kern.callpal_rti                      3829      2.10%     99.61% # number of callpals executed
-system.cpu.kern.callpal_callsys                   531      0.29%     99.90% # number of callpals executed
-system.cpu.kern.callpal_imb                       181      0.10%    100.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx                   4207      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal_wrent                       7      0.00%      2.20% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 176844     91.18%     93.39% # number of callpals executed
+system.cpu.kern.callpal_rdps                     6881      3.55%     96.93% # number of callpals executed
+system.cpu.kern.callpal_wrkgp                       1      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_wrusp                       7      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_rdusp                       9      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_whami                       2      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_rti                      5214      2.69%     99.63% # number of callpals executed
+system.cpu.kern.callpal_callsys                   531      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     202783                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     213009                       # number of hwrei instructions executed
 system.cpu.kern.inst.ivlb                           0                       # number of ivlb instructions executed
 system.cpu.kern.inst.ivle                           0                       # number of ivle instructions executed
-system.cpu.kern.inst.quiesce                     1877                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      177218                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     74624     42.11%     42.11% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21                      251      0.14%     42.25% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22                     5425      3.06%     45.31% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                    96918     54.69%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       158463                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      74570     47.06%     47.06% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21                       251      0.16%     47.22% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22                      5425      3.42%     50.64% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     78217     49.36%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                  3481725752                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0                3459659082     99.37%     99.37% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21                    39982      0.00%     99.37% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22                   930159      0.03%     99.39% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31                 21096529      0.61%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used                     0.894170                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_0                   0.999276                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6282                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      184158                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     75390     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21                      245      0.13%     41.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22                     1854      1.01%     42.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31                   106669     57.92%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       150141                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      74021     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21                       245      0.16%     49.46% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22                      1854      1.23%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31                     74021     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                  3636120154                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0                3601418096     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                    40474      0.00%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22                   159444      0.00%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31                 34502140      0.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used                     0.815284                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_0                   0.981841                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.807043                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel                 1939                      
+system.cpu.kern.ipl_used_31                  0.693932                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1937                      
 system.cpu.kern.mode_good_user                   1757                      
-system.cpu.kern.mode_good_idle                    182                      
-system.cpu.kern.mode_switch_kernel               3320                       # number of protection mode switches
+system.cpu.kern.mode_good_idle                    180                      
+system.cpu.kern.mode_switch_kernel               5982                       # number of protection mode switches
 system.cpu.kern.mode_switch_user                 1757                       # number of protection mode switches
-system.cpu.kern.mode_switch_idle                 2061                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             0.543289                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.584036                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_idle                 2103                       # number of protection mode switches
+system.cpu.kern.mode_switch_good             0.393619                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.323805                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle        0.088307                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel            31887159      0.92%      0.92% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user               3591270      0.10%      1.02% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle            3446247321     98.98%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     1575                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good_idle        0.085592                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel            54647278      1.50%      1.50% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user               3591234      0.10%      1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle            3577881640     98.40%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4208                       # number of times the context was actually changed
 system.cpu.kern.syscall                           329                       # number of syscalls executed
 system.cpu.kern.syscall_fork                        8      2.43%      2.43% # number of syscalls executed
 system.cpu.kern.syscall_read                       30      9.12%     11.55% # number of syscalls executed
@@ -112,16 +112,16 @@ system.cpu.kern.syscall_connect                     2      0.61%     97.57% # nu
 system.cpu.kern.syscall_setgid                      4      1.22%     98.78% # number of syscalls executed
 system.cpu.kern.syscall_getrlimit                   2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_setsid                      2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.016660                       # Percentage of non-idle cycles
-system.cpu.numCycles                         58006987                       # number of cpu cycles simulated
-system.cpu.num_insts                         58001813                       # Number of instructions executed
-system.cpu.num_refs                          13757191                       # Number of memory references
+system.cpu.not_idle_fraction                 0.017009                       # Percentage of non-idle cycles
+system.cpu.numCycles                         61845001                       # number of cpu cycles simulated
+system.cpu.num_insts                         61839827                       # Number of instructions executed
+system.cpu.num_refs                          16814484                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2735104                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 306                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        412                       # Number of DMA write transactions.
+system.disk0.dma_write_bytes                  2702336                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages                 302                       # Number of full page size DMA writes.
+system.disk0.dma_write_txs                        408                       # Number of DMA write transactions.
 system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
index 6204251a5..4741dd710 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
@@ -1,4 +1,4 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index b3b3e8704..f7fe15009 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  5 2006 22:13:02
-M5 started Fri Oct  6 00:23:19 2006
+M5 compiled Oct  8 2006 14:07:02
+M5 started Sun Oct  8 14:07:07 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
-Exiting @ tick 3481726167 because m5_exit instruction encountered
+Exiting @ tick 3636120569 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 65401b549..8f75c9525 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -75,7 +75,7 @@ side_b=system.membus.port[0]
 type=TimingSimpleCPU
 children=dtb itb
 clock=1
-cpu_id=-1
+cpu_id=0
 defer_registration=false
 dtb=system.cpu0.dtb
 function_trace=false
@@ -104,7 +104,7 @@ size=48
 type=TimingSimpleCPU
 children=dtb itb
 clock=1
-cpu_id=-1
+cpu_id=1
 defer_registration=false
 dtb=system.cpu1.dtb
 function_trace=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
index ed03e445d..9e0948f1e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
@@ -90,9 +90,9 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 itb=system.cpu0.itb
 dtb=system.cpu0.dtb
-cpu_id=-1
 profile=0
 clock=1
 defer_registration=false
@@ -118,9 +118,9 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=1
 itb=system.cpu1.itb
 dtb=system.cpu1.dtb
-cpu_id=-1
 profile=0
 clock=1
 defer_registration=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
index 4a397ddbf..57a610390 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 2 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -16,29 +16,27 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
 
unix_boot_mem ends at FFFFFC0000078000 
 
k_argc = 0 
-
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
-
CallbackFixup 0 18000, t7=FFFFFC0000700000
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
 
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
-
Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
 
memcluster 0, usage 1, start        0, end      392
 
memcluster 1, usage 0, start      392, end    16384
-
freeing pages 1030:16384
-
reserving pages 1030:1031
+
freeing pages 1069:16384
+
reserving pages 1069:1070
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
-
PID hash table entries: 1024 (order 10: 16384 bytes)
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
 
Using epoch = 1900
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
-
Mount-cache hash table entries: 512 (order: 0, 8192 bytes)
-
per-CPU timeslice cutoff: 374.49 usecs.
-
task migration cache decay timeout: 0 msecs.
+
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
 
Slave CPU 1 console command START
 SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
@@ -53,16 +51,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
Initializing Cryptographic API
 
rtc: Standard PC (1900) epoch (1900) detected
 
Real Time Clock Driver v1.12
-
Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
 
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
 
loop: loaded (max 8 devices)
-
Using anticipatory io scheduler
 
nbd: registered device at major 43
 
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
ns83820: irq bound to CPU 1
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
-
eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
 
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
 
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
@@ -75,24 +80,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
 
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
 
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
 
 hdb: unknown partition table
-
scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
-
  Vendor: Linux     Model: scsi_m5       Li  Rev: 0004
-
  Type:   Direct-Access                      ANSI SCSI revision: 03
-
SCSI device sda: 16384 512-byte hdwr sectors (8 MB)
-
SCSI device sda: drive cache: write back
-
 sda: unknown partition table
-
Attached scsi disk sda at scsi0, channel 0, id 0, lun 0
 
mice: PS/2 mouse device common for all mice
 
NET: Registered protocol family 2
-
IP: routing cache hash table of 1024 buckets, 16Kbytes
-
TCP: Hash tables configured (established 8192 bind 8192)
-
ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
 
ip_tables: (C) 2000-2002 Netfilter core team
 
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
 
Initializing IPsec netlink socket
 
NET: Registered protocol family 1
 
NET: Registered protocol family 17
@@ -101,7 +105,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
-
Freeing unused kernel memory: 480k freed
+
Freeing unused kernel memory: 224k freed
 

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
 mounting filesystems...
 loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
index bf7320067..4f8408501 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
@@ -1,232 +1,231 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 825990                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193572                       # Number of bytes of host memory used
-host_seconds                                    74.01                       # Real time elapsed on the host
-host_tick_rate                               47654938                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 779301                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197344                       # Number of bytes of host memory used
+host_seconds                                    85.22                       # Real time elapsed on the host
+host_tick_rate                               43826709                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    61131962                       # Number of instructions simulated
-sim_seconds                                  1.763494                       # Number of seconds simulated
-sim_ticks                                  3526987181                       # Number of ticks simulated
-system.cpu0.dtb.accesses                      1987164                       # DTB accesses
-system.cpu0.dtb.acv                               291                       # DTB access violations
-system.cpu0.dtb.hits                         10431590                       # DTB hits
-system.cpu0.dtb.misses                           9590                       # DTB misses
-system.cpu0.dtb.read_accesses                  606328                       # DTB read accesses
-system.cpu0.dtb.read_acv                          174                       # DTB read access violations
-system.cpu0.dtb.read_hits                     5831565                       # DTB read hits
-system.cpu0.dtb.read_misses                      7663                       # DTB read misses
-system.cpu0.dtb.write_accesses                1380836                       # DTB write accesses
-system.cpu0.dtb.write_acv                         117                       # DTB write access violations
-system.cpu0.dtb.write_hits                    4600025                       # DTB write hits
-system.cpu0.dtb.write_misses                     1927                       # DTB write misses
-system.cpu0.idle_fraction                    0.984514                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      2372045                       # ITB accesses
-system.cpu0.itb.acv                               143                       # ITB acv
-system.cpu0.itb.hits                          2368331                       # ITB hits
-system.cpu0.itb.misses                           3714                       # ITB misses
-system.cpu0.kern.callpal                       145084                       # number of callpals executed
+sim_insts                                    66411500                       # Number of instructions simulated
+sim_seconds                                  1.867451                       # Number of seconds simulated
+sim_ticks                                  3734901822                       # Number of ticks simulated
+system.cpu0.dtb.accesses                       828318                       # DTB accesses
+system.cpu0.dtb.acv                               315                       # DTB access violations
+system.cpu0.dtb.hits                         13279471                       # DTB hits
+system.cpu0.dtb.misses                           7094                       # DTB misses
+system.cpu0.dtb.read_accesses                  572336                       # DTB read accesses
+system.cpu0.dtb.read_acv                          200                       # DTB read access violations
+system.cpu0.dtb.read_hits                     8207004                       # DTB read hits
+system.cpu0.dtb.read_misses                      6394                       # DTB read misses
+system.cpu0.dtb.write_accesses                 255982                       # DTB write accesses
+system.cpu0.dtb.write_acv                         115                       # DTB write access violations
+system.cpu0.dtb.write_hits                    5072467                       # DTB write hits
+system.cpu0.dtb.write_misses                      700                       # DTB write misses
+system.cpu0.idle_fraction                    0.982495                       # Percentage of idle cycles
+system.cpu0.itb.accesses                      1888651                       # ITB accesses
+system.cpu0.itb.acv                               166                       # ITB acv
+system.cpu0.itb.hits                          1885318                       # ITB hits
+system.cpu0.itb.misses                           3333                       # ITB misses
+system.cpu0.kern.callpal                       146866                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir                    54      0.04%      0.04% # number of callpals executed
-system.cpu0.kern.callpal_wrmces                     1      0.00%      0.04% # number of callpals executed
-system.cpu0.kern.callpal_wrfen                      1      0.00%      0.04% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.04% # number of callpals executed
-system.cpu0.kern.callpal_swpctx                  1182      0.81%      0.85% # number of callpals executed
-system.cpu0.kern.callpal_tbi                       42      0.03%      0.88% # number of callpals executed
-system.cpu0.kern.callpal_wrent                      7      0.00%      0.89% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                135050     93.08%     93.97% # number of callpals executed
-system.cpu0.kern.callpal_rdps                    4795      3.30%     97.28% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.28% # number of callpals executed
-system.cpu0.kern.callpal_wrusp                      5      0.00%     97.28% # number of callpals executed
-system.cpu0.kern.callpal_rdusp                      8      0.01%     97.29% # number of callpals executed
-system.cpu0.kern.callpal_whami                      2      0.00%     97.29% # number of callpals executed
-system.cpu0.kern.callpal_rti                     3431      2.36%     99.65% # number of callpals executed
-system.cpu0.kern.callpal_callsys                  364      0.25%     99.90% # number of callpals executed
-system.cpu0.kern.callpal_imb                      139      0.10%    100.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir                   507      0.35%      0.35% # number of callpals executed
+system.cpu0.kern.callpal_wrmces                     1      0.00%      0.35% # number of callpals executed
+system.cpu0.kern.callpal_wrfen                      1      0.00%      0.35% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.35% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  2966      2.02%      2.37% # number of callpals executed
+system.cpu0.kern.callpal_tbi                       47      0.03%      2.40% # number of callpals executed
+system.cpu0.kern.callpal_wrent                      7      0.00%      2.40% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                132441     90.18%     92.58% # number of callpals executed
+system.cpu0.kern.callpal_rdps                    6235      4.25%     96.83% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.83% # number of callpals executed
+system.cpu0.kern.callpal_wrusp                      2      0.00%     96.83% # number of callpals executed
+system.cpu0.kern.callpal_rdusp                      8      0.01%     96.84% # number of callpals executed
+system.cpu0.kern.callpal_whami                      2      0.00%     96.84% # number of callpals executed
+system.cpu0.kern.callpal_rti                     4201      2.86%     99.70% # number of callpals executed
+system.cpu0.kern.callpal_callsys                  317      0.22%     99.91% # number of callpals executed
+system.cpu0.kern.callpal_imb                      128      0.09%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    160926                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    160336                       # number of hwrei instructions executed
 system.cpu0.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu0.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu0.kern.inst.quiesce                    1958                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count                     140584                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    56549     40.22%     40.22% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21                     251      0.18%     40.40% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22                    5487      3.90%     44.31% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30                      51      0.04%     44.34% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                   78246     55.66%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      122461                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     56518     46.15%     46.15% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21                      251      0.20%     46.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22                     5487      4.48%     50.84% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30                       51      0.04%     50.88% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    60154     49.12%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks                 3526986735                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0               3501352281     99.27%     99.27% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21                   53019      0.00%     99.27% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22                 1348211      0.04%     99.31% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30                   18326      0.00%     99.31% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31                24214898      0.69%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used                    0.871088                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_0                  0.999452                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6712                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     139203                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    55746     40.05%     40.05% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21                     245      0.18%     40.22% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22                    1904      1.37%     41.59% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30                     411      0.30%     41.89% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31                   80897     58.11%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      112531                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     55191     49.05%     49.05% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21                      245      0.22%     49.26% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22                     1904      1.69%     50.95% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30                      411      0.37%     51.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    54780     48.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks                 3734378988                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0               3696129107     98.98%     98.98% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21                   53683      0.00%     98.98% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22                  224672      0.01%     98.98% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                  128598      0.00%     98.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31                37842928      1.01%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used                    0.808395                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_0                  0.990044                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.768781                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel                1448                      
-system.cpu0.kern.mode_good_user                  1300                      
-system.cpu0.kern.mode_good_idle                   148                      
-system.cpu0.kern.mode_switch_kernel              2490                       # number of protection mode switches
-system.cpu0.kern.mode_switch_user                1300                       # number of protection mode switches
-system.cpu0.kern.mode_switch_idle                2110                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good            0.490847                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.581526                       # fraction of useful protection mode switches
+system.cpu0.kern.ipl_used_31                 0.677157                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel                1095                      
+system.cpu0.kern.mode_good_user                  1095                      
+system.cpu0.kern.mode_good_idle                     0                      
+system.cpu0.kern.mode_switch_kernel              6633                       # number of protection mode switches
+system.cpu0.kern.mode_switch_user                1095                       # number of protection mode switches
+system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
+system.cpu0.kern.mode_switch_good            0.283385                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.165084                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_idle       0.070142                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel           23256451      0.66%      0.66% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user              3397192      0.10%      0.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_idle           3500333090     99.24%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    1183                       # number of times the context was actually changed
-system.cpu0.kern.syscall                          231                       # number of syscalls executed
-system.cpu0.kern.syscall_fork                       6      2.60%      2.60% # number of syscalls executed
-system.cpu0.kern.syscall_read                      17      7.36%      9.96% # number of syscalls executed
-system.cpu0.kern.syscall_write                      4      1.73%     11.69% # number of syscalls executed
-system.cpu0.kern.syscall_close                     31     13.42%     25.11% # number of syscalls executed
-system.cpu0.kern.syscall_chdir                      1      0.43%     25.54% # number of syscalls executed
-system.cpu0.kern.syscall_obreak                    11      4.76%     30.30% # number of syscalls executed
-system.cpu0.kern.syscall_lseek                      6      2.60%     32.90% # number of syscalls executed
-system.cpu0.kern.syscall_getpid                     4      1.73%     34.63% # number of syscalls executed
-system.cpu0.kern.syscall_setuid                     2      0.87%     35.50% # number of syscalls executed
-system.cpu0.kern.syscall_getuid                     4      1.73%     37.23% # number of syscalls executed
-system.cpu0.kern.syscall_access                     9      3.90%     41.13% # number of syscalls executed
-system.cpu0.kern.syscall_dup                        2      0.87%     41.99% # number of syscalls executed
-system.cpu0.kern.syscall_open                      42     18.18%     60.17% # number of syscalls executed
-system.cpu0.kern.syscall_getgid                     4      1.73%     61.90% # number of syscalls executed
-system.cpu0.kern.syscall_sigprocmask                7      3.03%     64.94% # number of syscalls executed
-system.cpu0.kern.syscall_ioctl                      9      3.90%     68.83% # number of syscalls executed
-system.cpu0.kern.syscall_readlink                   1      0.43%     69.26% # number of syscalls executed
-system.cpu0.kern.syscall_execve                     4      1.73%     71.00% # number of syscalls executed
-system.cpu0.kern.syscall_mmap                      35     15.15%     86.15% # number of syscalls executed
-system.cpu0.kern.syscall_munmap                     2      0.87%     87.01% # number of syscalls executed
-system.cpu0.kern.syscall_mprotect                  10      4.33%     91.34% # number of syscalls executed
-system.cpu0.kern.syscall_gethostname                1      0.43%     91.77% # number of syscalls executed
-system.cpu0.kern.syscall_dup2                       2      0.87%     92.64% # number of syscalls executed
-system.cpu0.kern.syscall_fcntl                      8      3.46%     96.10% # number of syscalls executed
-system.cpu0.kern.syscall_socket                     2      0.87%     96.97% # number of syscalls executed
-system.cpu0.kern.syscall_connect                    2      0.87%     97.84% # number of syscalls executed
-system.cpu0.kern.syscall_setgid                     2      0.87%     98.70% # number of syscalls executed
-system.cpu0.kern.syscall_getrlimit                  1      0.43%     99.13% # number of syscalls executed
-system.cpu0.kern.syscall_setsid                     2      0.87%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.015486                       # Percentage of non-idle cycles
+system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel         3730045371     99.93%     99.93% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user              2718822      0.07%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    2967                       # number of times the context was actually changed
+system.cpu0.kern.syscall                          179                       # number of syscalls executed
+system.cpu0.kern.syscall_fork                       7      3.91%      3.91% # number of syscalls executed
+system.cpu0.kern.syscall_read                      14      7.82%     11.73% # number of syscalls executed
+system.cpu0.kern.syscall_write                      4      2.23%     13.97% # number of syscalls executed
+system.cpu0.kern.syscall_close                     27     15.08%     29.05% # number of syscalls executed
+system.cpu0.kern.syscall_chdir                      1      0.56%     29.61% # number of syscalls executed
+system.cpu0.kern.syscall_obreak                     6      3.35%     32.96% # number of syscalls executed
+system.cpu0.kern.syscall_lseek                      7      3.91%     36.87% # number of syscalls executed
+system.cpu0.kern.syscall_getpid                     4      2.23%     39.11% # number of syscalls executed
+system.cpu0.kern.syscall_setuid                     1      0.56%     39.66% # number of syscalls executed
+system.cpu0.kern.syscall_getuid                     3      1.68%     41.34% # number of syscalls executed
+system.cpu0.kern.syscall_access                     6      3.35%     44.69% # number of syscalls executed
+system.cpu0.kern.syscall_dup                        2      1.12%     45.81% # number of syscalls executed
+system.cpu0.kern.syscall_open                      30     16.76%     62.57% # number of syscalls executed
+system.cpu0.kern.syscall_getgid                     3      1.68%     64.25% # number of syscalls executed
+system.cpu0.kern.syscall_sigprocmask                8      4.47%     68.72% # number of syscalls executed
+system.cpu0.kern.syscall_ioctl                      8      4.47%     73.18% # number of syscalls executed
+system.cpu0.kern.syscall_execve                     5      2.79%     75.98% # number of syscalls executed
+system.cpu0.kern.syscall_mmap                      17      9.50%     85.47% # number of syscalls executed
+system.cpu0.kern.syscall_munmap                     3      1.68%     87.15% # number of syscalls executed
+system.cpu0.kern.syscall_mprotect                   4      2.23%     89.39% # number of syscalls executed
+system.cpu0.kern.syscall_gethostname                1      0.56%     89.94% # number of syscalls executed
+system.cpu0.kern.syscall_dup2                       2      1.12%     91.06% # number of syscalls executed
+system.cpu0.kern.syscall_fcntl                      8      4.47%     95.53% # number of syscalls executed
+system.cpu0.kern.syscall_socket                     2      1.12%     96.65% # number of syscalls executed
+system.cpu0.kern.syscall_connect                    2      1.12%     97.77% # number of syscalls executed
+system.cpu0.kern.syscall_setgid                     1      0.56%     98.32% # number of syscalls executed
+system.cpu0.kern.syscall_getrlimit                  1      0.56%     98.88% # number of syscalls executed
+system.cpu0.kern.syscall_setsid                     2      1.12%    100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction                0.017505                       # Percentage of non-idle cycles
 system.cpu0.numCycles                               0                       # number of cpu cycles simulated
-system.cpu0.num_insts                        44155958                       # Number of instructions executed
-system.cpu0.num_refs                         10463340                       # Number of memory references
-system.cpu1.dtb.accesses                       323344                       # DTB accesses
-system.cpu1.dtb.acv                                82                       # DTB access violations
-system.cpu1.dtb.hits                          4234985                       # DTB hits
-system.cpu1.dtb.misses                           2977                       # DTB misses
-system.cpu1.dtb.read_accesses                  222873                       # DTB read accesses
-system.cpu1.dtb.read_acv                           36                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2431648                       # DTB read hits
-system.cpu1.dtb.read_misses                      2698                       # DTB read misses
-system.cpu1.dtb.write_accesses                 100471                       # DTB write accesses
-system.cpu1.dtb.write_acv                          46                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1803337                       # DTB write hits
-system.cpu1.dtb.write_misses                      279                       # DTB write misses
-system.cpu1.idle_fraction                    0.993979                       # Percentage of idle cycles
-system.cpu1.itb.accesses                       912010                       # ITB accesses
-system.cpu1.itb.acv                                41                       # ITB acv
-system.cpu1.itb.hits                           910678                       # ITB hits
-system.cpu1.itb.misses                           1332                       # ITB misses
-system.cpu1.kern.callpal                        57529                       # number of callpals executed
+system.cpu0.num_insts                        52039310                       # Number of instructions executed
+system.cpu0.num_refs                         13510641                       # Number of memory references
+system.cpu1.dtb.accesses                       477045                       # DTB accesses
+system.cpu1.dtb.acv                                52                       # DTB access violations
+system.cpu1.dtb.hits                          4567143                       # DTB hits
+system.cpu1.dtb.misses                           4359                       # DTB misses
+system.cpu1.dtb.read_accesses                  328553                       # DTB read accesses
+system.cpu1.dtb.read_acv                           10                       # DTB read access violations
+system.cpu1.dtb.read_hits                     2660612                       # DTB read hits
+system.cpu1.dtb.read_misses                      3911                       # DTB read misses
+system.cpu1.dtb.write_accesses                 148492                       # DTB write accesses
+system.cpu1.dtb.write_acv                          42                       # DTB write access violations
+system.cpu1.dtb.write_hits                    1906531                       # DTB write hits
+system.cpu1.dtb.write_misses                      448                       # DTB write misses
+system.cpu1.idle_fraction                    0.994923                       # Percentage of idle cycles
+system.cpu1.itb.accesses                      1392687                       # ITB accesses
+system.cpu1.itb.acv                                18                       # ITB acv
+system.cpu1.itb.hits                          1391015                       # ITB hits
+system.cpu1.itb.misses                           1672                       # ITB misses
+system.cpu1.kern.callpal                        74475                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir                    51      0.09%      0.09% # number of callpals executed
-system.cpu1.kern.callpal_wrmces                     1      0.00%      0.09% # number of callpals executed
-system.cpu1.kern.callpal_wrfen                      1      0.00%      0.09% # number of callpals executed
-system.cpu1.kern.callpal_swpctx                   451      0.78%      0.88% # number of callpals executed
-system.cpu1.kern.callpal_tbi                       12      0.02%      0.90% # number of callpals executed
-system.cpu1.kern.callpal_wrent                      7      0.01%      0.91% # number of callpals executed
-system.cpu1.kern.callpal_swpipl                 54081     94.01%     94.92% # number of callpals executed
-system.cpu1.kern.callpal_rdps                     368      0.64%     95.56% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp                      1      0.00%     95.56% # number of callpals executed
-system.cpu1.kern.callpal_wrusp                      2      0.00%     95.56% # number of callpals executed
-system.cpu1.kern.callpal_rdusp                      2      0.00%     95.57% # number of callpals executed
-system.cpu1.kern.callpal_whami                      3      0.01%     95.57% # number of callpals executed
-system.cpu1.kern.callpal_rti                     2337      4.06%     99.63% # number of callpals executed
-system.cpu1.kern.callpal_callsys                  169      0.29%     99.93% # number of callpals executed
-system.cpu1.kern.callpal_imb                       41      0.07%    100.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir                   411      0.55%      0.55% # number of callpals executed
+system.cpu1.kern.callpal_wrmces                     1      0.00%      0.55% # number of callpals executed
+system.cpu1.kern.callpal_wrfen                      1      0.00%      0.56% # number of callpals executed
+system.cpu1.kern.callpal_swpctx                  2106      2.83%      3.38% # number of callpals executed
+system.cpu1.kern.callpal_tbi                        6      0.01%      3.39% # number of callpals executed
+system.cpu1.kern.callpal_wrent                      7      0.01%      3.40% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 65169     87.50%     90.91% # number of callpals executed
+system.cpu1.kern.callpal_rdps                    2603      3.50%     94.40% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.40% # number of callpals executed
+system.cpu1.kern.callpal_wrusp                      5      0.01%     94.41% # number of callpals executed
+system.cpu1.kern.callpal_rdusp                      1      0.00%     94.41% # number of callpals executed
+system.cpu1.kern.callpal_whami                      3      0.00%     94.41% # number of callpals executed
+system.cpu1.kern.callpal_rti                     3893      5.23%     99.64% # number of callpals executed
+system.cpu1.kern.callpal_callsys                  214      0.29%     99.93% # number of callpals executed
+system.cpu1.kern.callpal_imb                       52      0.07%    100.00% # number of callpals executed
 system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     63811                       # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei                     82987                       # number of hwrei instructions executed
 system.cpu1.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu1.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu1.kern.inst.quiesce                    1898                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count                      58267                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0                    25040     42.97%     42.97% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22                    5452      9.36%     52.33% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30                      54      0.09%     52.42% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31                   27721     47.58%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good                       57331                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0                     25007     43.62%     43.62% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22                     5452      9.51%     53.13% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30                       54      0.09%     53.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31                    26818     46.78%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks                 3526422675                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0               3497592433     99.18%     99.18% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22                 1410084      0.04%     99.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30                   19740      0.00%     99.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31                27400418      0.78%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used                    0.983936                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_0                  0.998682                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2512                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count                      71472                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                    27792     38.89%     38.89% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22                    1902      2.66%     41.55% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30                     507      0.71%     42.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31                   41271     57.74%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       55838                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                     26968     48.30%     48.30% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22                     1902      3.41%     51.70% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30                      507      0.91%     52.61% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                    26461     47.39%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks                 3734901376                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0               3704875983     99.20%     99.20% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22                  224436      0.01%     99.20% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30                  162794      0.00%     99.21% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31                29638163      0.79%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used                    0.781257                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0                  0.970351                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31                 0.967425                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel                 465                      
-system.cpu1.kern.mode_good_user                   465                      
-system.cpu1.kern.mode_good_idle                     0                      
-system.cpu1.kern.mode_switch_kernel              2771                       # number of protection mode switches
-system.cpu1.kern.mode_switch_user                 465                       # number of protection mode switches
-system.cpu1.kern.mode_switch_idle                   0                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good            0.287392                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel     0.167809                       # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31                 0.641152                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel                1094                      
+system.cpu1.kern.mode_good_user                   662                      
+system.cpu1.kern.mode_good_idle                   432                      
+system.cpu1.kern.mode_switch_kernel              2358                       # number of protection mode switches
+system.cpu1.kern.mode_switch_user                 662                       # number of protection mode switches
+system.cpu1.kern.mode_switch_idle                2831                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good            0.373953                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel     0.463953                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle       no value                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel         3525066043     99.96%     99.96% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user              1294184      0.04%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     452                       # number of times the context was actually changed
-system.cpu1.kern.syscall                           98                       # number of syscalls executed
-system.cpu1.kern.syscall_fork                       2      2.04%      2.04% # number of syscalls executed
-system.cpu1.kern.syscall_read                      13     13.27%     15.31% # number of syscalls executed
-system.cpu1.kern.syscall_close                     12     12.24%     27.55% # number of syscalls executed
-system.cpu1.kern.syscall_chmod                      1      1.02%     28.57% # number of syscalls executed
-system.cpu1.kern.syscall_obreak                     4      4.08%     32.65% # number of syscalls executed
-system.cpu1.kern.syscall_lseek                      4      4.08%     36.73% # number of syscalls executed
-system.cpu1.kern.syscall_getpid                     2      2.04%     38.78% # number of syscalls executed
-system.cpu1.kern.syscall_setuid                     2      2.04%     40.82% # number of syscalls executed
-system.cpu1.kern.syscall_getuid                     2      2.04%     42.86% # number of syscalls executed
-system.cpu1.kern.syscall_access                     2      2.04%     44.90% # number of syscalls executed
-system.cpu1.kern.syscall_open                      13     13.27%     58.16% # number of syscalls executed
-system.cpu1.kern.syscall_getgid                     2      2.04%     60.20% # number of syscalls executed
-system.cpu1.kern.syscall_sigprocmask                3      3.06%     63.27% # number of syscalls executed
-system.cpu1.kern.syscall_ioctl                      1      1.02%     64.29% # number of syscalls executed
-system.cpu1.kern.syscall_execve                     3      3.06%     67.35% # number of syscalls executed
-system.cpu1.kern.syscall_mmap                      19     19.39%     86.73% # number of syscalls executed
-system.cpu1.kern.syscall_munmap                     1      1.02%     87.76% # number of syscalls executed
-system.cpu1.kern.syscall_mprotect                   6      6.12%     93.88% # number of syscalls executed
-system.cpu1.kern.syscall_dup2                       1      1.02%     94.90% # number of syscalls executed
-system.cpu1.kern.syscall_fcntl                      2      2.04%     96.94% # number of syscalls executed
-system.cpu1.kern.syscall_setgid                     2      2.04%     98.98% # number of syscalls executed
-system.cpu1.kern.syscall_getrlimit                  1      1.02%    100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction                0.006021                       # Percentage of non-idle cycles
+system.cpu1.kern.mode_switch_good_idle       0.152596                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel           13374855      0.36%      0.36% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user              1967356      0.05%      0.41% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle           3719559163     99.59%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2107                       # number of times the context was actually changed
+system.cpu1.kern.syscall                          150                       # number of syscalls executed
+system.cpu1.kern.syscall_fork                       1      0.67%      0.67% # number of syscalls executed
+system.cpu1.kern.syscall_read                      16     10.67%     11.33% # number of syscalls executed
+system.cpu1.kern.syscall_close                     16     10.67%     22.00% # number of syscalls executed
+system.cpu1.kern.syscall_chmod                      1      0.67%     22.67% # number of syscalls executed
+system.cpu1.kern.syscall_obreak                     9      6.00%     28.67% # number of syscalls executed
+system.cpu1.kern.syscall_lseek                      3      2.00%     30.67% # number of syscalls executed
+system.cpu1.kern.syscall_getpid                     2      1.33%     32.00% # number of syscalls executed
+system.cpu1.kern.syscall_setuid                     3      2.00%     34.00% # number of syscalls executed
+system.cpu1.kern.syscall_getuid                     3      2.00%     36.00% # number of syscalls executed
+system.cpu1.kern.syscall_access                     5      3.33%     39.33% # number of syscalls executed
+system.cpu1.kern.syscall_open                      25     16.67%     56.00% # number of syscalls executed
+system.cpu1.kern.syscall_getgid                     3      2.00%     58.00% # number of syscalls executed
+system.cpu1.kern.syscall_sigprocmask                2      1.33%     59.33% # number of syscalls executed
+system.cpu1.kern.syscall_ioctl                      2      1.33%     60.67% # number of syscalls executed
+system.cpu1.kern.syscall_readlink                   1      0.67%     61.33% # number of syscalls executed
+system.cpu1.kern.syscall_execve                     2      1.33%     62.67% # number of syscalls executed
+system.cpu1.kern.syscall_mmap                      37     24.67%     87.33% # number of syscalls executed
+system.cpu1.kern.syscall_mprotect                  12      8.00%     95.33% # number of syscalls executed
+system.cpu1.kern.syscall_dup2                       1      0.67%     96.00% # number of syscalls executed
+system.cpu1.kern.syscall_fcntl                      2      1.33%     97.33% # number of syscalls executed
+system.cpu1.kern.syscall_setgid                     3      2.00%     99.33% # number of syscalls executed
+system.cpu1.kern.syscall_getrlimit                  1      0.67%    100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction                0.005077                       # Percentage of non-idle cycles
 system.cpu1.numCycles                               0                       # number of cpu cycles simulated
-system.cpu1.num_insts                        16976004                       # Number of instructions executed
-system.cpu1.num_refs                          4251312                       # Number of memory references
+system.cpu1.num_insts                        14372190                       # Number of instructions executed
+system.cpu1.num_refs                          4596339                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2735104                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 306                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        412                       # Number of DMA write transactions.
+system.disk0.dma_write_bytes                  2702336                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages                 302                       # Number of full page size DMA writes.
+system.disk0.dma_write_txs                        408                       # Number of DMA write transactions.
 system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
index 2191bd088..64d80c0d2 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
@@ -1,6 +1,6 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
 warn: Entering event queue @ 0.  Starting simulation...
-warn: 271342: Trying to launch CPU number 1!
+warn: 271343: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 2c496b914..3b92a25f9 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  5 2006 22:13:02
-M5 started Fri Oct  6 00:26:09 2006
+M5 compiled Oct  8 2006 14:07:02
+M5 started Sun Oct  8 14:10:09 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-Exiting @ tick 3526987181 because m5_exit instruction encountered
+Exiting @ tick 3734901822 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 7f27ca121..21d606051 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -75,7 +75,7 @@ side_b=system.membus.port[0]
 type=TimingSimpleCPU
 children=dtb itb
 clock=1
-cpu_id=-1
+cpu_id=0
 defer_registration=false
 dtb=system.cpu.dtb
 function_trace=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
index deba80368..73f9edaea 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
@@ -90,9 +90,9 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 itb=system.cpu.itb
 dtb=system.cpu.dtb
-cpu_id=-1
 profile=0
 clock=1
 defer_registration=false
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
index d6e3955cc..1d150a047 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 1 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -14,28 +14,26 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
 
unix_boot_mem ends at FFFFFC0000076000 
 
k_argc = 0 
-
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028)
-
CallbackFixup 0 18000, t7=FFFFFC0000700000
-
Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
 
memcluster 0, usage 1, start        0, end      392
 
memcluster 1, usage 0, start      392, end    16384
-
freeing pages 1030:16384
-
reserving pages 1030:1031
+
freeing pages 1069:16384
+
reserving pages 1069:1070
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
-
PID hash table entries: 1024 (order 10: 16384 bytes)
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
 
Using epoch = 1900
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init)
-
Mount-cache hash table entries: 512 (order: 0, 8192 bytes)
-
per-CPU timeslice cutoff: 374.49 usecs.
-
task migration cache decay timeout: 0 msecs.
+
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
 
SMP mode deactivated.
 
Brought up 1 CPUs
 
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
@@ -48,16 +46,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Initializing Cryptographic API
 
rtc: Standard PC (1900) epoch (1900) detected
 
Real Time Clock Driver v1.12
-
Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
 
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
 
loop: loaded (max 8 devices)
-
Using anticipatory io scheduler
 
nbd: registered device at major 43
 
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
ns83820: irq bound to CPU 0
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
-
eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
 
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
 
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
@@ -70,24 +75,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
 
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
 
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
 
 hdb: unknown partition table
-
scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0
-
  Vendor: Linux     Model: scsi_m5       Li  Rev: 0004
-
  Type:   Direct-Access                      ANSI SCSI revision: 03
-
SCSI device sda: 16384 512-byte hdwr sectors (8 MB)
-
SCSI device sda: drive cache: write back
-
 sda: unknown partition table
-
Attached scsi disk sda at scsi0, channel 0, id 0, lun 0
 
mice: PS/2 mouse device common for all mice
 
NET: Registered protocol family 2
-
IP: routing cache hash table of 1024 buckets, 16Kbytes
-
TCP: Hash tables configured (established 8192 bind 8192)
-
ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
 
ip_tables: (C) 2000-2002 Netfilter core team
 
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
 
Initializing IPsec netlink socket
 
NET: Registered protocol family 1
 
NET: Registered protocol family 17
@@ -96,7 +100,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
-
Freeing unused kernel memory: 480k freed
+
Freeing unused kernel memory: 224k freed
 

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
 mounting filesystems...
 loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
index 1d45d41a9..8b1a2f192 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
@@ -1,86 +1,86 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 820839                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193264                       # Number of bytes of host memory used
-host_seconds                                    70.65                       # Real time elapsed on the host
-host_tick_rate                               49454399                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 778282                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196900                       # Number of bytes of host memory used
+host_seconds                                    79.42                       # Real time elapsed on the host
+host_tick_rate                               45984556                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    57989043                       # Number of instructions simulated
-sim_seconds                                  1.746889                       # Number of seconds simulated
-sim_ticks                                  3493777466                       # Number of ticks simulated
-system.cpu.dtb.accesses                       2309470                       # DTB accesses
+sim_insts                                    61806956                       # Number of instructions simulated
+sim_seconds                                  1.825933                       # Number of seconds simulated
+sim_ticks                                  3651865694                       # Number of ticks simulated
+system.cpu.dtb.accesses                       1304498                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          13707871                       # DTB hits
-system.cpu.dtb.misses                           12493                       # DTB misses
-system.cpu.dtb.read_accesses                   828530                       # DTB read accesses
+system.cpu.dtb.hits                          16557993                       # DTB hits
+system.cpu.dtb.misses                           11425                       # DTB misses
+system.cpu.dtb.read_accesses                   900427                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      7595606                       # DTB read hits
-system.cpu.dtb.read_misses                      10298                       # DTB read misses
-system.cpu.dtb.write_accesses                 1480940                       # DTB write accesses
+system.cpu.dtb.read_hits                     10039007                       # DTB read hits
+system.cpu.dtb.read_misses                      10280                       # DTB read misses
+system.cpu.dtb.write_accesses                  404071                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6112265                       # DTB write hits
-system.cpu.dtb.write_misses                      2195                       # DTB write misses
-system.cpu.idle_fraction                     0.979465                       # Percentage of idle cycles
-system.cpu.itb.accesses                       3281347                       # ITB accesses
+system.cpu.dtb.write_hits                     6518986                       # DTB write hits
+system.cpu.dtb.write_misses                      1145                       # DTB write misses
+system.cpu.idle_fraction                     0.978522                       # Percentage of idle cycles
+system.cpu.itb.accesses                       3281311                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           3276357                       # ITB hits
+system.cpu.itb.hits                           3276321                       # ITB hits
 system.cpu.itb.misses                            4990                       # ITB misses
-system.cpu.kern.callpal                        182454                       # number of callpals executed
+system.cpu.kern.callpal                        194059                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx                   1571      0.86%      0.86% # number of callpals executed
-system.cpu.kern.callpal_tbi                        54      0.03%      0.89% # number of callpals executed
-system.cpu.kern.callpal_wrent                       7      0.00%      0.90% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 171092     93.77%     94.67% # number of callpals executed
-system.cpu.kern.callpal_rdps                     5160      2.83%     97.50% # number of callpals executed
-system.cpu.kern.callpal_wrkgp                       1      0.00%     97.50% # number of callpals executed
-system.cpu.kern.callpal_wrusp                       7      0.00%     97.50% # number of callpals executed
-system.cpu.kern.callpal_rdusp                      10      0.01%     97.51% # number of callpals executed
-system.cpu.kern.callpal_whami                       2      0.00%     97.51% # number of callpals executed
-system.cpu.kern.callpal_rti                      3834      2.10%     99.61% # number of callpals executed
-system.cpu.kern.callpal_callsys                   531      0.29%     99.90% # number of callpals executed
-system.cpu.kern.callpal_imb                       181      0.10%    100.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx                   4207      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal_wrent                       7      0.00%      2.20% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 176948     91.18%     93.38% # number of callpals executed
+system.cpu.kern.callpal_rdps                     6887      3.55%     96.93% # number of callpals executed
+system.cpu.kern.callpal_wrkgp                       1      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal_wrusp                       7      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_rdusp                       9      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_whami                       2      0.00%     96.94% # number of callpals executed
+system.cpu.kern.callpal_rti                      5221      2.69%     99.63% # number of callpals executed
+system.cpu.kern.callpal_callsys                   531      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     202524                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     213133                       # number of hwrei instructions executed
 system.cpu.kern.inst.ivlb                           0                       # number of ivlb instructions executed
 system.cpu.kern.inst.ivle                           0                       # number of ivle instructions executed
-system.cpu.kern.inst.quiesce                     1876                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      176961                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     74471     42.08%     42.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21                      251      0.14%     42.23% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22                     5439      3.07%     45.30% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                    96800     54.70%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       158180                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      74417     47.05%     47.05% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21                       251      0.16%     47.20% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22                      5439      3.44%     50.64% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     78073     49.36%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                  3493777020                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0                3466334940     99.21%     99.21% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21                    53019      0.00%     99.22% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22                  1268195      0.04%     99.25% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31                 26120866      0.75%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used                     0.893869                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_0                   0.999275                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6280                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      184276                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     75422     40.93%     40.93% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21                      245      0.13%     41.06% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22                     1861      1.01%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31                   106748     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       150212                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      74053     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21                       245      0.16%     49.46% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22                      1861      1.24%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31                     74053     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                  3651865248                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0                3611061665     98.88%     98.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                    53683      0.00%     98.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22                   219598      0.01%     98.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31                 40530302      1.11%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used                     0.815147                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_0                   0.981849                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.806539                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel                 1938                      
-system.cpu.kern.mode_good_user                   1757                      
-system.cpu.kern.mode_good_idle                    181                      
-system.cpu.kern.mode_switch_kernel               3323                       # number of protection mode switches
-system.cpu.kern.mode_switch_user                 1757                       # number of protection mode switches
-system.cpu.kern.mode_switch_idle                 2060                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             0.542857                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.583208                       # fraction of useful protection mode switches
+system.cpu.kern.ipl_used_31                  0.693718                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1935                      
+system.cpu.kern.mode_good_user                   1755                      
+system.cpu.kern.mode_good_idle                    180                      
+system.cpu.kern.mode_switch_kernel               5988                       # number of protection mode switches
+system.cpu.kern.mode_switch_user                 1755                       # number of protection mode switches
+system.cpu.kern.mode_switch_idle                 2104                       # number of protection mode switches
+system.cpu.kern.mode_switch_good             0.393013                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.323146                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle        0.087864                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel            39254786      1.12%      1.12% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user               4685669      0.13%      1.26% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle            3449836563     98.74%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     1572                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good_idle        0.085551                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel            58882589      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user               4685612      0.13%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle            3588297045     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4208                       # number of times the context was actually changed
 system.cpu.kern.syscall                           329                       # number of syscalls executed
 system.cpu.kern.syscall_fork                        8      2.43%      2.43% # number of syscalls executed
 system.cpu.kern.syscall_read                       30      9.12%     11.55% # number of syscalls executed
@@ -112,16 +112,16 @@ system.cpu.kern.syscall_connect                     2      0.61%     97.57% # nu
 system.cpu.kern.syscall_setgid                      4      1.22%     98.78% # number of syscalls executed
 system.cpu.kern.syscall_getrlimit                   2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_setsid                      2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.020535                       # Percentage of non-idle cycles
+system.cpu.not_idle_fraction                 0.021478                       # Percentage of non-idle cycles
 system.cpu.numCycles                                0                       # number of cpu cycles simulated
-system.cpu.num_insts                         57989043                       # Number of instructions executed
-system.cpu.num_refs                          13753099                       # Number of memory references
+system.cpu.num_insts                         61806956                       # Number of instructions executed
+system.cpu.num_refs                          16806539                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2735104                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 306                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        412                       # Number of DMA write transactions.
+system.disk0.dma_write_bytes                  2702336                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages                 302                       # Number of full page size DMA writes.
+system.disk0.dma_write_txs                        408                       # Number of DMA write transactions.
 system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
@@ -130,9 +130,9 @@ system.disk2.dma_write_full_pages                   1                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk        no value                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi         no value                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
index 6204251a5..4741dd710 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
@@ -1,4 +1,4 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index 88e69a41f..8c667881d 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  5 2006 22:13:02
-M5 started Fri Oct  6 00:24:58 2006
+M5 compiled Oct  8 2006 14:07:02
+M5 started Sun Oct  8 14:08:49 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
-Exiting @ tick 3493777466 because m5_exit instruction encountered
+Exiting @ tick 3651865694 because m5_exit instruction encountered
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 8722c1b67..95cccfbf2 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=AtomicSimpleCPU
 children=workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
index 6ae80aecf..1138f2dbe 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
@@ -36,6 +36,7 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.physmem
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index 9fdf1d513..bbc6e55b5 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1393697                       # Simulator instruction rate (inst/s)
+host_inst_rate                                1432213                       # Simulator instruction rate (inst/s)
 host_mem_usage                                 147652                       # Number of bytes of host memory used
-host_seconds                                     0.36                       # Real time elapsed on the host
-host_tick_rate                                1391995                       # Simulator tick rate (ticks/s)
+host_seconds                                     0.35                       # Real time elapsed on the host
+host_tick_rate                                1430432                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 207a0046c..de2559c1c 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 11:12:49
-M5 started Sat Oct  7 11:13:17 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:58 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Exiting @ tick 499999 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index f4bdc8171..72ea32994 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
 clock=1
+cpu_id=0
 defer_registration=false
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index 71a6d33c4..14eb07351 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
@@ -75,6 +75,7 @@ max_loads_all_threads=0
 progress_interval=0
 mem=system.cpu.dcache
 system=system
+cpu_id=0
 workload=system.cpu.workload
 clock=1
 defer_registration=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index f8d2c4ea7..2a6a055ab 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 618043                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159232                       # Number of bytes of host memory used
-host_seconds                                     0.81                       # Real time elapsed on the host
-host_tick_rate                                 843177                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 598582                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159216                       # Number of bytes of host memory used
+host_seconds                                     0.84                       # Real time elapsed on the host
+host_tick_rate                                 816632                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses             500000                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency            3                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                 499597                       # number of overall hits
 system.cpu.icache.overall_miss_latency           1209                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000806                       # miss rate for overall accesses
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 409068a91..70c3f2454 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  7 2006 12:38:12
-M5 started Sat Oct  7 12:38:52 2006
+M5 compiled Oct  8 2006 14:00:39
+M5 started Sun Oct  8 14:00:59 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Exiting @ tick 682488 because a thread reached the max instruction count

From 5df93cc1cd5ce8272032ad1cbf5265b5fdb4713f Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 14:48:24 -0700
Subject: [PATCH 08/38] Replace tests of LOCKED/UNCACHEABLE flags with
 isLocked()/isUncacheable().

--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
---
 src/cpu/base_dyn_inst_impl.hh     |  2 +-
 src/cpu/checker/cpu.cc            |  8 ++++----
 src/cpu/o3/fetch_impl.hh          |  2 +-
 src/cpu/o3/lsq_unit.hh            |  4 ++--
 src/cpu/o3/lsq_unit_impl.hh       |  6 +++---
 src/cpu/ozone/back_end.hh         |  4 ++--
 src/cpu/ozone/back_end_impl.hh    |  2 +-
 src/cpu/ozone/cpu.hh              | 12 ++++++------
 src/cpu/ozone/front_end_impl.hh   |  2 +-
 src/cpu/ozone/inorder_back_end.hh | 18 +++++++++---------
 src/cpu/ozone/lsq_unit.hh         |  2 +-
 src/cpu/ozone/lsq_unit_impl.hh    |  6 +++---
 src/cpu/ozone/lw_lsq.hh           |  4 ++--
 src/cpu/ozone/lw_lsq_impl.hh      | 10 +++++-----
 src/cpu/simple/atomic.cc          |  4 ++--
 src/cpu/simple/timing.cc          |  4 ++--
 src/cpu/simple_thread.hh          |  6 +++---
 src/mem/cache/cache_impl.hh       |  6 +++---
 18 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index f2109e88d..d6cdff5c5 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -193,7 +193,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
     // note this is a local, not BaseDynInst::fault
     Fault trans_fault = cpu->translateDataReadReq(req);
 
-    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
+    if (trans_fault == NoFault && !(req->isUncacheable())) {
         // It's a valid address to cacheable space.  Record key MemReq
         // parameters so we can generate another one just like it for
         // the timing access without calling translate() again (which
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 1540a6b94..f6d56eef6 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -175,7 +175,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
 
     pkt->dataStatic(&data);
 
-    if (!(memReq->getFlags() & UNCACHEABLE)) {
+    if (!(memReq->isUncacheable())) {
         // Access memory to see if we have the same data
         dcachePort->sendFunctional(pkt);
     } else {
@@ -251,9 +251,9 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     // This is because the LSQ would have to be snooped in the CPU to
     // verify this data.
     if (unverifiedReq &&
-        !(unverifiedReq->getFlags() & UNCACHEABLE) &&
-        (!(unverifiedReq->getFlags() & LOCKED) ||
-         ((unverifiedReq->getFlags() & LOCKED) &&
+        !(unverifiedReq->isUncacheable()) &&
+        (!(unverifiedReq->isLocked()) ||
+         ((unverifiedReq->isLocked()) &&
           unverifiedReq->getScResult() == 1))) {
         T inst_data;
 /*
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 2d447bfe5..497179576 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -599,7 +599,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     if (fault == NoFault) {
 #if 0
         if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
-            memReq[tid]->flags & UNCACHEABLE) {
+            memReq[tid]->isUncacheable()) {
             DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
                     "misspeculating path)!",
                     memReq[tid]->paddr);
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 90d1a3d53..58945f04e 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -492,7 +492,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
     // A bit of a hackish way to get uncached accesses to work only if they're
     // at the head of the LSQ and are ready to commit (at the head of the ROB
     // too).
-    if (req->getFlags() & UNCACHEABLE &&
+    if (req->isUncacheable() &&
         (load_idx != loadHead || !load_inst->isAtCommit())) {
         iewStage->rescheduleMemInst(load_inst);
         ++lsqRescheduledLoads;
@@ -509,7 +509,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             load_idx, store_idx, storeHead, req->getPaddr());
 
 #if FULL_SYSTEM
-    if (req->getFlags() & LOCKED) {
+    if (req->isLocked()) {
         cpu->lockAddr = req->getPaddr();
         cpu->lockFlag = true;
     }
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 98bea74fb..63ffcece1 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -416,7 +416,7 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
         // needs to hit the head of commit.
-        if (!(inst->req->getFlags() & UNCACHEABLE) || inst->isAtCommit()) {
+        if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
             inst->setExecuted();
         }
         iewStage->instToCommit(inst);
@@ -613,8 +613,8 @@ LSQUnit<Impl>::writebackStores()
                 storeQueue[storeWBIdx].inst->seqNum);
 
         // @todo: Remove this SC hack once the memory system handles it.
-        if (req->getFlags() & LOCKED) {
-            if (req->getFlags() & UNCACHEABLE) {
+        if (req->isLocked()) {
+            if (req->isUncacheable()) {
                 req->setScResult(2);
             } else {
                 if (cpu->lockFlag) {
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 9bab6a964..8debd277d 100644
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -493,7 +493,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
     }
 */
 /*
-    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+    if (!dcacheInterface && (memReq->isUncacheable()))
         recordEvent("Uncached Read");
 */
     return LSQ.read(req, data, load_idx);
@@ -534,7 +534,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
         *res = memReq->result;
         */
 /*
-    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+    if (!dcacheInterface && (memReq->isUncacheable()))
         recordEvent("Uncached Write");
 */
     return LSQ.write(req, data, store_idx);
diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh
index ac3218c02..4078699fe 100644
--- a/src/cpu/ozone/back_end_impl.hh
+++ b/src/cpu/ozone/back_end_impl.hh
@@ -1256,7 +1256,7 @@ BackEnd<Impl>::executeInsts()
 
 //                ++iewExecStoreInsts;
 
-                if (!(inst->req->flags & LOCKED)) {
+                if (!(inst->req->isLocked())) {
                     inst->setExecuted();
 
                     instToCommit(inst);
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 8c5be9424..70ec1d101 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -455,12 +455,12 @@ class OzoneCPU : public BaseCPU
     {
 #if 0
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
-        if (req->flags & LOCKED) {
+        if (req->isLocked()) {
             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
         }
 #endif
-        if (req->flags & LOCKED) {
+        if (req->isLocked()) {
             lockAddrList.insert(req->paddr);
             lockFlag = true;
         }
@@ -489,10 +489,10 @@ class OzoneCPU : public BaseCPU
         ExecContext *xc;
 
         // If this is a store conditional, act appropriately
-        if (req->flags & LOCKED) {
+        if (req->isLocked()) {
             xc = req->xc;
 
-            if (req->flags & UNCACHEABLE) {
+            if (req->isUncacheable()) {
                 // Don't update result register (see stq_c in isa_desc)
                 req->result = 2;
                 xc->setStCondFailures(0);//Needed? [RGD]
@@ -532,8 +532,8 @@ class OzoneCPU : public BaseCPU
 
 #endif
 
-        if (req->flags & LOCKED) {
-            if (req->flags & UNCACHEABLE) {
+        if (req->isLocked()) {
+            if (req->isUncacheable()) {
                 req->result = 2;
             } else {
                 if (this->lockFlag) {
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index d34716de6..5956c5cba 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -493,7 +493,7 @@ FrontEnd<Impl>::fetchCacheLine()
     if (fault == NoFault) {
 #if 0
         if (cpu->system->memctrl->badaddr(memReq->paddr) ||
-            memReq->flags & UNCACHEABLE) {
+            memReq->isUncacheable()) {
             DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
                     "misspeculating path!",
                     memReq->paddr);
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index ffdba2f6c..76eef6fad 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -231,7 +231,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
         }
     }
 /*
-    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+    if (!dcacheInterface && (memReq->isUncacheable()))
         recordEvent("Uncached Read");
 */
     return fault;
@@ -243,7 +243,7 @@ Fault
 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
 {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
-    if (req->flags & LOCKED) {
+    if (req->isLocked()) {
         req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
         req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
     }
@@ -291,7 +291,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     if (res && (fault == NoFault))
         *res = memReq->result;
 /*
-    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+    if (!dcacheInterface && (memReq->isUncacheable()))
         recordEvent("Uncached Write");
 */
     return fault;
@@ -306,10 +306,10 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
     ExecContext *xc;
 
     // If this is a store conditional, act appropriately
-    if (req->flags & LOCKED) {
+    if (req->isLocked()) {
         xc = req->xc;
 
-        if (req->flags & UNCACHEABLE) {
+        if (req->isUncacheable()) {
             // Don't update result register (see stq_c in isa_desc)
             req->result = 2;
             xc->setStCondFailures(0);//Needed? [RGD]
@@ -391,7 +391,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     }
 
 /*
-    if (!dcacheInterface && (req->flags & UNCACHEABLE))
+    if (!dcacheInterface && (req->isUncacheable()))
         recordEvent("Uncached Read");
 */
     return NoFault;
@@ -455,8 +455,8 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
         }
     }
 /*
-    if (req->flags & LOCKED) {
-        if (req->flags & UNCACHEABLE) {
+    if (req->isLocked()) {
+        if (req->isUncacheable()) {
             // Don't update result register (see stq_c in isa_desc)
             req->result = 2;
         } else {
@@ -469,7 +469,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
         *res = req->result;
         */
 /*
-    if (!dcacheInterface && (req->flags & UNCACHEABLE))
+    if (!dcacheInterface && (req->isUncacheable()))
         recordEvent("Uncached Write");
 */
     return NoFault;
diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index 38c1c09a2..056c79521 100644
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -426,7 +426,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     // at the head of the LSQ and are ready to commit (at the head of the ROB
     // too).
     // @todo: Fix uncached accesses.
-    if (req->flags & UNCACHEABLE &&
+    if (req->isUncacheable() &&
         (load_idx != loadHead || !loadQueue[load_idx]->readyToCommit())) {
 
         return TheISA::genMachineCheckFault();
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh
index ee0804036..c46eb90be 100644
--- a/src/cpu/ozone/lsq_unit_impl.hh
+++ b/src/cpu/ozone/lsq_unit_impl.hh
@@ -577,7 +577,7 @@ OzoneLSQ<Impl>::writebackStores()
             MemAccessResult result = dcacheInterface->access(req);
 
             //@todo temp fix for LL/SC (works fine for 1 CPU)
-            if (req->flags & LOCKED) {
+            if (req->isLocked()) {
                 req->result=1;
                 panic("LL/SC! oh no no support!!!");
             }
@@ -596,7 +596,7 @@ OzoneLSQ<Impl>::writebackStores()
                 Event *wb = NULL;
 /*
                 typename IEW::LdWritebackEvent *wb = NULL;
-                if (req->flags & LOCKED) {
+                if (req->isLocked()) {
                     // Stx_C does not generate a system port transaction.
                     req->result=0;
                     wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
@@ -630,7 +630,7 @@ OzoneLSQ<Impl>::writebackStores()
 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 //                        storeQueue[storeWBIdx].inst->seqNum);
 
-                if (req->flags & LOCKED) {
+                if (req->isLocked()) {
                     // Stx_C does not generate a system port transaction.
                     req->result=1;
                     typename BackEnd::LdWritebackEvent *wb =
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 6640a9f34..347f4569b 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -507,7 +507,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
     // at the head of the LSQ and are ready to commit (at the head of the ROB
     // too).
     // @todo: Fix uncached accesses.
-    if (req->getFlags() & UNCACHEABLE &&
+    if (req->isUncacheable() &&
         (inst != loadQueue.back() || !inst->isAtCommit())) {
         DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of "
                 "commit/LSQ!\n",
@@ -659,7 +659,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
         return NoFault;
     }
 
-    if (req->getFlags() & LOCKED) {
+    if (req->isLocked()) {
         cpu->lockFlag = true;
     }
 
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 4c96ad149..9d17b027f 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -394,7 +394,7 @@ OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
     // Actually probably want the oldest faulting load
     if (load_fault != NoFault) {
         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
-        if (!(inst->req->getFlags() & UNCACHEABLE && !inst->isAtCommit())) {
+        if (!(inst->req->isUncacheable() && !inst->isAtCommit())) {
             inst->setExecuted();
         }
         // Maybe just set it as can commit here, although that might cause
@@ -605,8 +605,8 @@ OzoneLWLSQ<Impl>::writebackStores()
                 inst->seqNum);
 
         // @todo: Remove this SC hack once the memory system handles it.
-        if (req->getFlags() & LOCKED) {
-            if (req->getFlags() & UNCACHEABLE) {
+        if (req->isLocked()) {
+            if (req->isUncacheable()) {
                 req->setScResult(2);
             } else {
                 if (cpu->lockFlag) {
@@ -663,7 +663,7 @@ OzoneLWLSQ<Impl>::writebackStores()
             if (result != MA_HIT && dcacheInterface->doEvents()) {
                 store_event->miss = true;
                 typename BackEnd::LdWritebackEvent *wb = NULL;
-                if (req->flags & LOCKED) {
+                if (req->isLocked()) {
                     wb = new typename BackEnd::LdWritebackEvent(inst,
                                                             be);
                     store_event->wbEvent = wb;
@@ -690,7 +690,7 @@ OzoneLWLSQ<Impl>::writebackStores()
 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 //                        inst->seqNum);
 
-                if (req->flags & LOCKED) {
+                if (req->isLocked()) {
                     // Stx_C does not generate a system port
                     // transaction in the 21264, but that might be
                     // hard to accomplish in this model.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0ca700634..42b0e9783 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -282,7 +282,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     }
 
     // This will need a new way to tell if it has a dcache attached.
-    if (req->getFlags() & UNCACHEABLE)
+    if (req->isUncacheable())
         recordEvent("Uncached Read");
 
     return fault;
@@ -380,7 +380,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     }
 
     // This will need a new way to tell if it's hooked up to a cache or not.
-    if (req->getFlags() & UNCACHEABLE)
+    if (req->isUncacheable())
         recordEvent("Uncached Write");
 
     // If the write needs to have a fault on the access, consider calling
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index cd43bb5fc..a394468b9 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -257,7 +257,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
     }
 
     // This will need a new way to tell if it has a dcache attached.
-    if (req->getFlags() & UNCACHEABLE)
+    if (req->isUncacheable())
         recordEvent("Uncached Read");
 
     return fault;
@@ -342,7 +342,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     }
 
     // This will need a new way to tell if it's hooked up to a cache or not.
-    if (req->getFlags() & UNCACHEABLE)
+    if (req->isUncacheable())
         recordEvent("Uncached Write");
 
     // If the write needs to have a fault on the access, consider calling
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 242cfd0e1..6fa6500bd 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -237,7 +237,7 @@ class SimpleThread : public ThreadState
     Fault read(RequestPtr &req, T &data)
     {
 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
-        if (req->flags & LOCKED) {
+        if (req->isLocked()) {
             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
         }
@@ -256,10 +256,10 @@ class SimpleThread : public ThreadState
         ExecContext *xc;
 
         // If this is a store conditional, act appropriately
-        if (req->flags & LOCKED) {
+        if (req->isLocked()) {
             xc = req->xc;
 
-            if (req->flags & UNCACHEABLE) {
+            if (req->isUncacheable()) {
                 // Don't update result register (see stq_c in isa_desc)
                 req->result = 2;
                 xc->setStCondFailures(0);//Needed? [RGD]
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 46f4b0ebe..63273adc6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -60,7 +60,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 {
     if (isCpuSide)
     {
-        if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
+        if (pkt->isWrite() && (pkt->req->isLocked())) {
             pkt->req->setScResult(1);
         }
         if (!(pkt->flags & SATISFIED)) {
@@ -95,7 +95,7 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
     if (isCpuSide)
     {
         //Temporary solution to LL/SC
-        if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
+        if (pkt->isWrite() && (pkt->req->isLocked())) {
             pkt->req->setScResult(1);
         }
 
@@ -125,7 +125,7 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide)
         pkt->req->setThreadContext(0,0);
 
         //Temporary solution to LL/SC
-        if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
+        if (pkt->isWrite() && (pkt->req->isLocked())) {
             assert("Can't handle LL/SC on functional path\n");
         }
 

From a82f017591ecb78cb098e38314d87d64fcaaa37f Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 8 Oct 2006 18:44:49 -0400
Subject: [PATCH 09/38] bus changes

src/mem/bus.cc:
src/mem/bus.hh:
    minor fix and some formatting changes
src/python/m5/objects/Bus.py:
    changed bits to bytes

--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
---
 src/mem/bus.cc               | 18 +++++++++++++-----
 src/mem/bus.hh               |  6 +++---
 src/python/m5/objects/Bus.py |  2 +-
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 2a38cb635..4cd4dd71a 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -68,7 +68,9 @@ Bus::init()
 }
 
 Bus::BusFreeEvent::BusFreeEvent(Bus *_bus) : Event(&mainEventQueue), bus(_bus)
-{}
+{
+    assert(!scheduled());
+}
 
 void Bus::BusFreeEvent::process()
 {
@@ -104,6 +106,7 @@ Bus::occupyBus(int numCycles)
     } else {
         busIdle.reschedule(tickNextIdle);
     }
+    DPRINTF(Bus, "The bus is now occupied from tick %d to %d\n", curTick, tickNextIdle);
 }
 
 /** Function called by the port when the bus is receiving a Timing
@@ -155,6 +158,11 @@ Bus::recvTiming(Packet *pkt)
 
     if (port->sendTiming(pkt))  {
         // Packet was successfully sent. Return true.
+        // Also take care of retries
+        if (retryingPort) {
+            retryList.pop_front();
+            retryingPort = NULL;
+        }
         return true;
     }
 
@@ -166,15 +174,15 @@ Bus::recvTiming(Packet *pkt)
 void
 Bus::recvRetry(int id)
 {
-    //If there's anything waiting...
+    // If there's anything waiting...
     if (retryList.size()) {
         retryingPort = retryList.front();
         retryingPort->sendRetry();
-        //If the retryingPort pointer isn't null, either sendTiming wasn't
-        //called, or it was and the packet was successfully sent.
+        // If the retryingPort pointer isn't null, sendTiming wasn't called
         if (retryingPort) {
+            warn("sendRetry didn't call sendTiming\n");
             retryList.pop_front();
-            retryingPort = 0;
+            retryingPort = NULL;
         }
     }
 }
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 96f1152a6..f238f134d 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -54,7 +54,7 @@ class Bus : public MemObject
     int busId;
     /** the clock speed for the bus */
     int clock;
-    /** the width of the bus in bits */
+    /** the width of the bus in bytes */
     int width;
     /** the next tick at which the bus will be idle */
     Tick tickNextIdle;
@@ -230,7 +230,7 @@ class Bus : public MemObject
         } else {
             // The device was retrying a packet. It didn't work, so we'll leave
             // it at the head of the retry list.
-            retryingPort = 0;
+            retryingPort = NULL;
 
             // We shouldn't be receiving a packet from one port when a different
             // one is retrying.
@@ -250,7 +250,7 @@ class Bus : public MemObject
 
     Bus(const std::string &n, int bus_id, int _clock, int _width)
         : MemObject(n), busId(bus_id), clock(_clock), width(_width),
-        tickNextIdle(0), busIdle(this), retryingPort(0), defaultPort(NULL)
+        tickNextIdle(0), busIdle(this), retryingPort(NULL), defaultPort(NULL)
     {
         //Both the width and clock period must be positive
         assert(width);
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index b7c55990c..6710111e5 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -7,4 +7,4 @@ class Bus(MemObject):
     default = Port("Default port for requests that aren't handeled by a device.")
     bus_id = Param.Int(0, "blah")
     clock = Param.Clock("1GHz", "bus clock speed")
-    width = Param.Int(64, "bus width (bits)")
+    width = Param.Int(64, "bus width (bytes)")

From 0c574f10695002827b42f750cef16fe4e6118c2b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 8 Oct 2006 18:45:21 -0400
Subject: [PATCH 10/38] missing else

--HG--
extra : convert_revision : 8fe0e00dc3ae70b4449a78c15dd249939e644f02
---
 src/mem/cache/base_cache.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index d7ccca8c0..02a46b444 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -105,8 +105,7 @@ BaseCache::CachePort::recvRetry()
                 drainList.pop_front();
         }
     }
-
-    if (!isCpuSide)
+    else if (!isCpuSide)
     {
         pkt = cache->getPacket();
         bool success = sendTiming(pkt);

From 1345183a89a148bf48110c4559448dd708549252 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sun, 8 Oct 2006 18:48:03 -0400
Subject: [PATCH 11/38] Move away from using the statusChange function on
 snoops.  Clean up snooping code in general.

--HG--
extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
---
 src/mem/bus.cc              | 38 +++++++++++--------------------------
 src/mem/bus.hh              | 14 +++-----------
 src/mem/cache/base_cache.hh |  7 -------
 src/mem/cache/cache_impl.hh | 13 +++----------
 src/mem/port.hh             |  3 +--
 5 files changed, 18 insertions(+), 57 deletions(-)

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 3c5283a77..daca6f985 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -79,9 +79,15 @@ Bus::recvTiming(Packet *pkt)
 
     short dest = pkt->getDest();
     if (dest == Packet::Broadcast) {
-        if ( timingSnoopPhase1(pkt) )
+        if (timingSnoop(pkt))
         {
-            timingSnoopPhase2(pkt);
+            pkt->flags |= SNOOP_COMMIT;
+            bool success = timingSnoop(pkt);
+            assert(success);
+            if (pkt->flags & SATISFIED) {
+                //Cache-Cache transfer occuring
+                return true;
+            }
             port = findPort(pkt->getAddr(), pkt->getSrc());
         }
         else
@@ -195,42 +201,20 @@ Bus::atomicSnoop(Packet *pkt)
 }
 
 bool
-Bus::timingSnoopPhase1(Packet *pkt)
+Bus::timingSnoop(Packet *pkt)
 {
     std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
     bool success = true;
 
     while (!ports.empty() && success)
     {
-        snoopCallbacks.push_back(ports.back());
         success = interfaces[ports.back()]->sendTiming(pkt);
         ports.pop_back();
     }
-    if (!success)
-    {
-        while (!snoopCallbacks.empty())
-        {
-            interfaces[snoopCallbacks.back()]->sendStatusChange(Port::SnoopSquash);
-            snoopCallbacks.pop_back();
-        }
-        return false;
-    }
-    return true;
+
+    return success;
 }
 
-void
-Bus::timingSnoopPhase2(Packet *pkt)
-{
-    bool success;
-    pkt->flags |= SNOOP_COMMIT;
-    while (!snoopCallbacks.empty())
-    {
-        success = interfaces[snoopCallbacks.back()]->sendTiming(pkt);
-        //We should not fail on snoop callbacks
-        assert(success);
-        snoopCallbacks.pop_back();
-    }
-}
 
 /** Function called by the port when the bus is receiving a Atomic
  * transaction.*/
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 941389296..3d7f4ad65 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -62,9 +62,6 @@ class Bus : public MemObject
     AddrRangeList defaultRange;
     std::vector<DevMap> portSnoopList;
 
-    std::vector<int> snoopCallbacks;
-
-
     /** Function called by the port when the bus is recieving a Timing
       transaction.*/
     bool recvTiming(Packet *pkt);
@@ -105,16 +102,11 @@ class Bus : public MemObject
     /** Snoop all relevant ports atomicly. */
     void atomicSnoop(Packet *pkt);
 
-    /** Snoop for NACK and Blocked in phase 1
+    /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want
+     * the snoop to happen
      * @return True if succeds.
      */
-    bool timingSnoopPhase1(Packet *pkt);
-
-    /** @todo Don't need to commit all snoops just those that need it
-     *(register somehow). */
-    /** Commit all snoops now that we know if any of them would have blocked.
-     */
-    void timingSnoopPhase2(Packet *pkt);
+    bool timingSnoop(Packet *pkt);
 
     /** Process address range request.
      * @param resp addresses that we can respond to
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index c69fb7fd5..4b0e114b9 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -165,10 +165,6 @@ class BaseCache : public MemObject
                 memSidePort->sendStatusChange(Port::RangeChange);
             }
         }
-        else if (status == Port::SnoopSquash) {
-            assert(snoopPhase2);
-            snoopPhase2 = false;
-        }
     }
 
     virtual Packet *getPacket()
@@ -215,9 +211,6 @@ class BaseCache : public MemObject
     bool topLevelCache;
 
 
-    /** True if we are now in phase 2 of the snoop process. */
-    bool snoopPhase2;
-
     /** Stores time the cache blocked for statistics. */
     Tick blockedCycle;
 
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 46f4b0ebe..0d625054c 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -72,16 +72,9 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
         if (pkt->isResponse())
             handleResponse(pkt);
         else {
-            //Check if we are in phase1
-            if (!snoopPhase2) {
-                snoopPhase2 = true;
-            }
-            else {
-                //Check if we should do the snoop
-                if (pkt->flags && SNOOP_COMMIT)
-                    snoop(pkt);
-                snoopPhase2 = false;
-            }
+            //Check if we should do the snoop
+            if (pkt->flags && SNOOP_COMMIT)
+                snoop(pkt);
         }
     }
     return true;
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 6b4184043..bb3bc1b1b 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -106,8 +106,7 @@ class Port
     /** Holds the ports status.  Currently just that a range recomputation needs
      * to be done. */
     enum Status {
-        RangeChange,
-        SnoopSquash
+        RangeChange
     };
 
     void setName(const std::string &name)

From e65f0cef3ca70edf37ff74920def4ac899f6c7e3 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sun, 8 Oct 2006 19:05:48 -0400
Subject: [PATCH 12/38] Only respond if the pkt needs a response. Fix an issue
 with memory handling writebacks.

src/mem/cache/base_cache.hh:
src/mem/tport.cc:
    Only respond if the pkt needs a response.
src/mem/physical.cc:
    Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.

--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
---
 src/mem/cache/base_cache.hh | 13 +++++++++----
 src/mem/physical.cc         | 15 +++++++++------
 src/mem/tport.cc            |  8 +++++---
 3 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 4b0e114b9..2e92e7730 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -516,8 +516,10 @@ class BaseCache : public MemObject
      */
     void respond(Packet *pkt, Tick time)
     {
-        CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
-        reqCpu->schedule(time);
+        if (pkt->needsResponse()) {
+            CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+            reqCpu->schedule(time);
+        }
     }
 
     /**
@@ -530,8 +532,10 @@ class BaseCache : public MemObject
         if (!pkt->req->isUncacheable()) {
             missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
         }
-        CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
-        reqCpu->schedule(time);
+        if (pkt->needsResponse()) {
+            CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+            reqCpu->schedule(time);
+        }
     }
 
     /**
@@ -542,6 +546,7 @@ class BaseCache : public MemObject
     {
 //        assert("Implement\n" && 0);
 //	mi->respond(pkt,curTick + hitLatency);
+        assert (pkt->needsResponse());
         CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
         reqMem->schedule(time);
     }
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 23b1d5ffc..070693442 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -197,22 +197,25 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
 {
     assert(pkt->getAddr() + pkt->getSize() < params()->addrRange.size());
 
-    switch (pkt->cmd) {
-      case Packet::ReadReq:
+    if (pkt->isRead()) {
         if (pkt->req->isLocked()) {
             trackLoadLocked(pkt->req);
         }
         memcpy(pkt->getPtr<uint8_t>(),
                pmemAddr + pkt->getAddr() - params()->addrRange.start,
                pkt->getSize());
-        break;
-      case Packet::WriteReq:
+    }
+    else if (pkt->isWrite()) {
         if (writeOK(pkt->req)) {
             memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
                    pkt->getPtr<uint8_t>(), pkt->getSize());
         }
-        break;
-      default:
+    }
+    else if (pkt->isInvalidate()) {
+        //upgrade or invalidate
+        pkt->flags |= SATISFIED;
+    }
+    else {
         panic("unimplemented");
     }
 
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 55c301c87..cef7a2a5b 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -47,9 +47,11 @@ SimpleTimingPort::recvTiming(Packet *pkt)
     // if we ever added it back.
     assert(pkt->result != Packet::Nacked);
     Tick latency = recvAtomic(pkt);
-    // turn packet around to go back to requester
-    pkt->makeTimingResponse();
-    sendTimingLater(pkt, latency);
+    // turn packet around to go back to requester if response expected
+    if (pkt->needsResponse()) {
+        pkt->makeTimingResponse();
+        sendTimingLater(pkt, latency);
+    }
     return true;
 }
 

From 5cb1840b311a7bba93a658481703ce1e09ccf7bb Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sun, 8 Oct 2006 20:30:42 -0400
Subject: [PATCH 13/38] Fixes for functional path.

If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
    Make the fuctional path do the correct tye of snoop

--HG--
extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
---
 src/cpu/o3/fetch_impl.hh        |  2 +-
 src/cpu/o3/lsq_impl.hh          |  2 +-
 src/cpu/ozone/front_end_impl.hh |  2 +-
 src/cpu/ozone/lw_lsq_impl.hh    |  2 +-
 src/cpu/simple/atomic.cc        |  5 +++--
 src/cpu/simple/timing.cc        |  3 ++-
 src/mem/bus.cc                  | 14 +++++++++++++-
 src/mem/bus.hh                  |  3 +++
 8 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 497179576..b3c3caaad 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -63,7 +63,7 @@ template<class Impl>
 void
 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
 {
-    panic("DefaultFetch doesn't expect recvFunctional callback!");
+    warn("Default fetch doesn't update it's state from a functional call.");
 }
 
 template<class Impl>
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 2bbab71f0..7b7d1eb8e 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -46,7 +46,7 @@ template <class Impl>
 void
 LSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
 {
-    panic("O3CPU doesn't expect recvFunctional callback!");
+    warn("O3CPU doesn't update things on a recvFunctional.");
 }
 
 template <class Impl>
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 5956c5cba..c814ff9c7 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -59,7 +59,7 @@ template<class Impl>
 void
 FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
 {
-    panic("FrontEnd doesn't expect recvFunctional callback!");
+    warn("FrontEnd doesn't update state from functional calls");
 }
 
 template<class Impl>
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 9d17b027f..e523712da 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -72,7 +72,7 @@ template <class Impl>
 void
 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
 {
-    panic("O3CPU doesn't expect recvFunctional callback!");
+    warn("O3CPU doesn't update things on a recvFunctional");
 }
 
 template <class Impl>
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 42b0e9783..e21065ebc 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -94,7 +94,7 @@ AtomicSimpleCPU::init()
 bool
 AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
 {
-    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
+    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
     return true;
 }
 
@@ -108,7 +108,8 @@ AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
 void
 AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
 {
-    panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
+    //No internal storage to update, just return
+    return;
 }
 
 void
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a394468b9..48362c42a 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -74,7 +74,8 @@ TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
 void
 TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
 {
-    panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
+    //No internal storage to update, jusst return
+    return;
 }
 
 void
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index daca6f985..1646cbd57 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -200,6 +200,18 @@ Bus::atomicSnoop(Packet *pkt)
     }
 }
 
+void
+Bus::functionalSnoop(Packet *pkt)
+{
+    std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
+
+    while (!ports.empty())
+    {
+        interfaces[ports.back()]->sendFunctional(pkt);
+        ports.pop_back();
+    }
+}
+
 bool
 Bus::timingSnoop(Packet *pkt)
 {
@@ -236,7 +248,7 @@ Bus::recvFunctional(Packet *pkt)
     DPRINTF(Bus, "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n",
             pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
     assert(pkt->getDest() == Packet::Broadcast);
-    atomicSnoop(pkt);
+    functionalSnoop(pkt);
     findPort(pkt->getAddr(), pkt->getSrc())->sendFunctional(pkt);
 }
 
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 3d7f4ad65..ff4ec9c8c 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -102,6 +102,9 @@ class Bus : public MemObject
     /** Snoop all relevant ports atomicly. */
     void atomicSnoop(Packet *pkt);
 
+    /** Snoop all relevant ports functionally. */
+    void functionalSnoop(Packet *pkt);
+
     /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want
      * the snoop to happen
      * @return True if succeds.

From 4cfddc0d772eff614a5b6d61efa846aa7fa706a8 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sun, 8 Oct 2006 20:47:50 -0400
Subject: [PATCH 14/38] Make sure to propogate sendFunctional calls with
 functional not atomic.

src/mem/cache/cache_impl.hh:
    Fix a error case by putting a panic in.
    Make sure to propogate sendFunctional calls with functional not atomic.

--HG--
extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
---
 src/mem/cache/cache_impl.hh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 1f03065b6..9ce8f515d 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -603,7 +603,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort
             // update the cache state and statistics
             if (mshr || !writes.empty()){
                 // Can't handle it, return pktuest unsatisfied.
-                return 0;
+                panic("Atomic access ran into outstanding MSHR's or WB's!");
             }
             if (!pkt->req->isUncacheable()) {
                 // Fetch the cache block to fill
@@ -655,7 +655,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort
             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
         } else if (pkt->isWrite()) {
             // Still need to change data in all locations.
-            return otherSidePort->sendAtomic(pkt);
+            otherSidePort->sendFunctional(pkt);
         }
         return curTick + lat;
     }

From 0a3e4d56e5d7d9aad4a34dc561a5b4fa84337c5f Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sun, 8 Oct 2006 21:08:27 -0400
Subject: [PATCH 15/38] Update stats for functional path fix

--HG--
extra : convert_revision : 0f38abab28e7e44f1dc748c25938185651dd1b7d
---
 .../ref/alpha/linux/o3-timing/m5stats.txt     | 30 ++++---
 .../00.hello/ref/alpha/linux/o3-timing/stderr |  9 ++
 .../00.hello/ref/alpha/linux/o3-timing/stdout |  4 +-
 .../ref/alpha/linux/simple-timing/m5stats.txt | 30 ++++---
 .../ref/alpha/linux/o3-timing/m5stats.txt     | 84 +++++++++----------
 .../ref/alpha/linux/o3-timing/stderr          | 18 ++++
 .../ref/alpha/linux/o3-timing/stdout          |  4 +-
 .../ref/alpha/eio/simple-timing/m5stats.txt   | 32 ++++---
 .../ref/alpha/eio/simple-timing/stdout        |  4 +-
 9 files changed, 116 insertions(+), 99 deletions(-)

diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index b8dbf28af..59cda42d9 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    420                       # Nu
 global.BPredUnit.condPredicted                   1302                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         2254                       # Number of BP lookups
 global.BPredUnit.usedRAS                          291                       # Number of times the RAS was used to get a target.
-host_inst_rate                                   1748                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 160364                       # Number of bytes of host memory used
-host_seconds                                     3.22                       # Real time elapsed on the host
-host_tick_rate                                   2135                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  46995                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 160420                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                                  57256                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 12                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               259                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  2049                       # Number of loads inserted to the mem dependence unit.
@@ -334,41 +334,39 @@ system.cpu.l2cache.ReadReq_misses                 492                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency          492                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995951                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            492                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses                2                       # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits                    2                       # number of WriteReq hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.008130                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.004065                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                496                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                494                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency     2.071138                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      4                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency           1019                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.991935                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.995951                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  492                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency          492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.991935                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.995951                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             492                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               496                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses               494                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency     2.071138                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     4                       # number of overall hits
+system.cpu.l2cache.overall_hits                     2                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency          1019                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.991935                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.995951                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 492                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency          492                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.991935                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.995951                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            492                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -385,7 +383,7 @@ system.cpu.l2cache.replacements                     0                       # nu
 system.cpu.l2cache.sampled_refs                   492                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.l2cache.tagsinuse               290.948901                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       4                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.numCycles                             6869                       # number of cpu cycles simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
index 8893caac8..558105896 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1,12 @@
 warn: Entering event queue @ 0.  Starting simulation...
 warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 718827a30..f2a1151c4 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:00:39
-M5 started Sun Oct  8 14:00:45 2006
+M5 compiled Oct  8 2006 20:54:51
+M5 started Sun Oct  8 20:55:10 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
 Exiting @ tick 6868 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 757bbb920..2ee3181d8 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  98835                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159632                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                                 144603                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 292635                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159688                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                                 422303                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
@@ -153,41 +153,39 @@ system.cpu.l2cache.ReadReq_misses                 441                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency          441                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997738                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            441                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses                2                       # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits                    2                       # number of WriteReq hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.006803                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002268                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                444                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                442                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency            882                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.993243                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.997738                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  441                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency          441                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.993243                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.997738                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             441                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               444                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses               442                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     3                       # number of overall hits
+system.cpu.l2cache.overall_hits                     1                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency           882                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.993243                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.997738                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 441                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency          441                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.993243                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.997738                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            441                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -204,7 +202,7 @@ system.cpu.l2cache.replacements                     0                       # nu
 system.cpu.l2cache.sampled_refs                   441                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.l2cache.tagsinuse               240.276061                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
index 15172b43c..9871af3ab 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   1081                       # Nu
 global.BPredUnit.condPredicted                   2449                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         4173                       # Number of BP lookups
 global.BPredUnit.usedRAS                          551                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  40630                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 161244                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
-host_tick_rate                                  30458                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  48339                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 161300                       # Number of bytes of host memory used
+host_seconds                                     0.23                       # Real time elapsed on the host
+host_tick_rate                                  36232                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 41                       # Number of conflicting loads.
 memdepunit.memDep.conflictingLoads                 39                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               194                       # Number of conflicting stores.
@@ -193,7 +193,7 @@ system.cpu.dcache.overall_mshr_miss_latency_0          741
 system.cpu.dcache.overall_mshr_miss_latency_1            0                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.075551                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate_0     0.075551                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_1     no value                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             343                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses_0           343                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses_1             0                       # number of overall MSHR misses
@@ -476,20 +476,20 @@ system.cpu.ipc_1                             0.666272                       # IP
 system.cpu.ipc_total                         1.332425                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    8158                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
-(null)                                              2      0.02%            # Type of FU issued
-IntAlu                                           5514     67.59%            # Type of FU issued
-IntMult                                             1      0.01%            # Type of FU issued
-IntDiv                                              0      0.00%            # Type of FU issued
-FloatAdd                                            2      0.02%            # Type of FU issued
-FloatCmp                                            0      0.00%            # Type of FU issued
-FloatCvt                                            0      0.00%            # Type of FU issued
-FloatMult                                           0      0.00%            # Type of FU issued
-FloatDiv                                            0      0.00%            # Type of FU issued
-FloatSqrt                                           0      0.00%            # Type of FU issued
-MemRead                                          1662     20.37%            # Type of FU issued
-MemWrite                                          977     11.98%            # Type of FU issued
-IprAccess                                           0      0.00%            # Type of FU issued
-InstPrefetch                                        0      0.00%            # Type of FU issued
+                          (null)            2      0.02%            # Type of FU issued
+                          IntAlu         5514     67.59%            # Type of FU issued
+                         IntMult            1      0.01%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd            2      0.02%            # Type of FU issued
+                        FloatCmp            0      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            0      0.00%            # Type of FU issued
+                        FloatDiv            0      0.00%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead         1662     20.37%            # Type of FU issued
+                        MemWrite          977     11.98%            # Type of FU issued
+                       IprAccess            0      0.00%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.end_dist
 system.cpu.iq.ISSUE:FU_type_1                    8090                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_1.start_dist
@@ -590,35 +590,31 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994802                       # m
 system.cpu.l2cache.ReadReq_mshr_miss_rate_0     0.994802                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            957                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses_0          957                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses                4                       # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_accesses_0              4                       # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits                    4                       # number of WriteReq hits
-system.cpu.l2cache.WriteReq_hits_0                  4                       # number of WriteReq hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.009404                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  0.005225                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                966                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0              966                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                962                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0              962                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses_1                0                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency     2.059561                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency_0     2.059561                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0>                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency_0            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_1     no value                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      9                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits_0                    9                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0>                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                      5                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits_0                    5                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits_1                    0                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency           1971                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency_0         1971                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency_1            0                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.990683                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_0        0.990683                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.994802                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_0        0.994802                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate_1    <err: div-0>                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  957                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses_0                957                       # number of demand (read+write) misses
@@ -629,8 +625,8 @@ system.cpu.l2cache.demand_mshr_hits_1               0                       # nu
 system.cpu.l2cache.demand_mshr_miss_latency          957                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency_0          957                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency_1            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.990683                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_0     0.990683                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.994802                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_0     0.994802                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             957                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses_0           957                       # number of demand (read+write) MSHR misses
@@ -640,8 +636,8 @@ system.cpu.l2cache.mshr_cap_events                  0                       # nu
 system.cpu.l2cache.mshr_cap_events_0                0                       # number of times MSHR cap was activated
 system.cpu.l2cache.mshr_cap_events_1                0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               966                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0             966                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses               962                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0             962                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses_1               0                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency     2.059561                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency_0     2.059561                       # average overall miss latency
@@ -652,14 +648,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0>
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     9                       # number of overall hits
-system.cpu.l2cache.overall_hits_0                   9                       # number of overall hits
+system.cpu.l2cache.overall_hits                     5                       # number of overall hits
+system.cpu.l2cache.overall_hits_0                   5                       # number of overall hits
 system.cpu.l2cache.overall_hits_1                   0                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency          1971                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency_0         1971                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency_1            0                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.990683                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_0       0.990683                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.994802                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_0       0.994802                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate_1   <err: div-0>                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 957                       # number of overall misses
 system.cpu.l2cache.overall_misses_0               957                       # number of overall misses
@@ -670,8 +666,8 @@ system.cpu.l2cache.overall_mshr_hits_1              0                       # nu
 system.cpu.l2cache.overall_mshr_miss_latency          957                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency_0          957                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency_1            0                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.990683                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_0     0.990683                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.994802                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_0     0.994802                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            957                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses_0          957                       # number of overall MSHR misses
@@ -699,7 +695,7 @@ system.cpu.l2cache.soft_prefetch_mshr_full            0                       #
 system.cpu.l2cache.soft_prefetch_mshr_full_0            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.l2cache.soft_prefetch_mshr_full_1            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.l2cache.tagsinuse               558.911632                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       9                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                       5                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.writebacks_0                     0                       # number of writebacks
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
index 890488cd2..48d711163 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
@@ -2,3 +2,21 @@ warn: Entering event queue @ 0.  Starting simulation...
 warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
+warn: Default fetch doesn't update it's state from a functional call.
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
index 6b640d359..41cca6f14 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:00:39
-M5 started Sun Oct  8 14:00:56 2006
+M5 compiled Oct  8 2006 20:54:51
+M5 started Sun Oct  8 20:55:24 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
 Exiting @ tick 8441 because target called exit()
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index 2a6a055ab..ebc70e1f0 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 598582                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159216                       # Number of bytes of host memory used
-host_seconds                                     0.84                       # Real time elapsed on the host
-host_tick_rate                                 816632                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 620088                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159272                       # Number of bytes of host memory used
+host_seconds                                     0.81                       # Real time elapsed on the host
+host_tick_rate                                 845969                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses             500000                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency            3                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                 499597                       # number of overall hits
 system.cpu.icache.overall_miss_latency           1209                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000806                       # miss rate for overall accesses
@@ -152,41 +152,39 @@ system.cpu.l2cache.ReadReq_misses                 857                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency          857                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            857                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses              165                       # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits                  165                       # number of WriteReq hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.192532                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               1022                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                857                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                    165                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency           1714                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.838552                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  857                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency          857                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.838552                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             857                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses              1022                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses               857                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                   165                       # number of overall hits
+system.cpu.l2cache.overall_hits                     0                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency          1714                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.838552                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 857                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency          857                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.838552                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            857                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -203,7 +201,7 @@ system.cpu.l2cache.replacements                     0                       # nu
 system.cpu.l2cache.sampled_refs                   857                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.l2cache.tagsinuse               560.393094                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     165                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 70c3f2454..076cf0a5a 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:00:39
-M5 started Sun Oct  8 14:00:59 2006
+M5 compiled Oct  8 2006 20:54:51
+M5 started Sun Oct  8 20:55:29 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Exiting @ tick 682488 because a thread reached the max instruction count

From 31f3f2421454b8ba3286f6e536bcc58af5debf48 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 18:26:59 -0700
Subject: [PATCH 16/38] Fixes for Port proxies and proxy parameters.

--HG--
extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
---
 src/python/m5/params.py |  2 +-
 src/python/m5/proxy.py  | 17 +++++++++++++----
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index cbbd23004..93d784181 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -804,7 +804,7 @@ class PortRef(object):
         newRef.simobj = simobj
         assert(isSimObject(newRef.simobj))
         if self.peer and not proxy.isproxy(self.peer):
-            peerObj = memo[self.peer.simobj]
+            peerObj = self.peer.simobj(_memo=memo)
             newRef.peer = self.peer.clone(peerObj, memo)
             assert(not isinstance(newRef.peer, VectorPortRef))
         return newRef
diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py
index 7ebc0ae19..e539f14ee 100644
--- a/src/python/m5/proxy.py
+++ b/src/python/m5/proxy.py
@@ -33,6 +33,8 @@
 #
 #####################################################################
 
+import copy
+
 class BaseProxy(object):
     def __init__(self, search_self, search_up):
         self._search_self = search_self
@@ -129,15 +131,22 @@ class AttrProxy(BaseProxy):
             return super(AttrProxy, self).__getattr__(self, attr)
         if hasattr(self, '_pdesc'):
             raise AttributeError, "Attribute reference on bound proxy"
-        self._modifiers.append(attr)
-        return self
+        # Return a copy of self rather than modifying self in place
+        # since self could be an indirect reference via a variable or
+        # parameter
+        new_self = copy.deepcopy(self)
+        new_self._modifiers.append(attr)
+        return new_self
 
     # support indexing on proxies (e.g., Self.cpu[0])
     def __getitem__(self, key):
         if not isinstance(key, int):
             raise TypeError, "Proxy object requires integer index"
-        self._modifiers.append(key)
-        return self
+        if hasattr(self, '_pdesc'):
+            raise AttributeError, "Index operation on bound proxy"
+        new_self = copy.deepcopy(self)
+        new_self._modifiers.append(key)
+        return new_self
 
     def find(self, obj):
         try:

From ce6c752ede773388da21dd05f6eff20398a1f447 Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Sun, 8 Oct 2006 22:05:34 -0400
Subject: [PATCH 17/38] update for m5 base linux. (the last changes were for
 the latest m5hack, i.e. with nate's stuff in it).

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
    update for m5 base linux.

--HG--
extra : convert_revision : c78a1748bf8a0950450c29a7b96bb8735c1bb3d2
---
 .../console.system.sim_console                |   8 +-
 .../tsunami-simple-atomic-dual/m5stats.txt    | 377 +++++++++---------
 .../linux/tsunami-simple-atomic-dual/stderr   |   6 +-
 .../linux/tsunami-simple-atomic-dual/stdout   |   8 +-
 .../console.system.sim_console                |   8 +-
 .../linux/tsunami-simple-atomic/m5stats.txt   | 102 ++---
 .../alpha/linux/tsunami-simple-atomic/stderr  |   4 +-
 .../alpha/linux/tsunami-simple-atomic/stdout  |   8 +-
 .../console.system.sim_console                |   8 +-
 .../tsunami-simple-timing-dual/m5stats.txt    | 168 ++++----
 .../linux/tsunami-simple-timing-dual/stderr   |   6 +-
 .../linux/tsunami-simple-timing-dual/stdout   |   8 +-
 .../console.system.sim_console                |   8 +-
 .../linux/tsunami-simple-timing/m5stats.txt   |  98 ++---
 .../alpha/linux/tsunami-simple-timing/stderr  |   4 +-
 .../alpha/linux/tsunami-simple-timing/stdout  |   8 +-
 16 files changed, 410 insertions(+), 419 deletions(-)

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
index 57a610390..27adebb82 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 2 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -19,7 +19,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
 
CallbackFixup 0 18000, t7=FFFFFC000070C000
 
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
-
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
@@ -35,7 +35,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
 
Slave CPU 1 console command START
@@ -59,9 +59,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
io scheduler cfq registered
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
-
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
-
ns83820: irq bound to CPU 1
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index 537721d92..e76c1d683 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,219 +1,218 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1292093                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197872                       # Number of bytes of host memory used
-host_seconds                                    51.53                       # Real time elapsed on the host
-host_tick_rate                               72118724                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1270607                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197696                       # Number of bytes of host memory used
+host_seconds                                    51.09                       # Real time elapsed on the host
+host_tick_rate                               72782461                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    66579941                       # Number of instructions simulated
-sim_seconds                                  1.858108                       # Number of seconds simulated
-sim_ticks                                  3716216351                       # Number of ticks simulated
-system.cpu0.dtb.accesses                       604194                       # DTB accesses
-system.cpu0.dtb.acv                               337                       # DTB access violations
-system.cpu0.dtb.hits                         12597930                       # DTB hits
-system.cpu0.dtb.misses                           7857                       # DTB misses
-system.cpu0.dtb.read_accesses                  426113                       # DTB read accesses
+sim_insts                                    64909600                       # Number of instructions simulated
+sim_seconds                                  1.859078                       # Number of seconds simulated
+sim_ticks                                  3718155709                       # Number of ticks simulated
+system.cpu0.dtb.accesses                       544556                       # DTB accesses
+system.cpu0.dtb.acv                               335                       # DTB access violations
+system.cpu0.dtb.hits                         14841931                       # DTB hits
+system.cpu0.dtb.misses                           7356                       # DTB misses
+system.cpu0.dtb.read_accesses                  377530                       # DTB read accesses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_hits                     7793080                       # DTB read hits
-system.cpu0.dtb.read_misses                      7107                       # DTB read misses
-system.cpu0.dtb.write_accesses                 178081                       # DTB write accesses
-system.cpu0.dtb.write_acv                         127                       # DTB write access violations
-system.cpu0.dtb.write_hits                    4804850                       # DTB write hits
-system.cpu0.dtb.write_misses                      750                       # DTB write misses
-system.cpu0.idle_fraction                    0.986701                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      1567177                       # ITB accesses
+system.cpu0.dtb.read_hits                     8970576                       # DTB read hits
+system.cpu0.dtb.read_misses                      6581                       # DTB read misses
+system.cpu0.dtb.write_accesses                 167026                       # DTB write accesses
+system.cpu0.dtb.write_acv                         125                       # DTB write access violations
+system.cpu0.dtb.write_hits                    5871355                       # DTB write hits
+system.cpu0.dtb.write_misses                      775                       # DTB write misses
+system.cpu0.idle_fraction                    0.984943                       # Percentage of idle cycles
+system.cpu0.itb.accesses                      1436270                       # ITB accesses
 system.cpu0.itb.acv                               184                       # ITB acv
-system.cpu0.itb.hits                          1563535                       # ITB hits
-system.cpu0.itb.misses                           3642                       # ITB misses
-system.cpu0.kern.callpal                       140535                       # number of callpals executed
+system.cpu0.itb.hits                          1432801                       # ITB hits
+system.cpu0.itb.misses                           3469                       # ITB misses
+system.cpu0.kern.callpal                       182754                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir                   567      0.40%      0.40% # number of callpals executed
-system.cpu0.kern.callpal_wrmces                     1      0.00%      0.40% # number of callpals executed
-system.cpu0.kern.callpal_wrfen                      1      0.00%      0.41% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.41% # number of callpals executed
-system.cpu0.kern.callpal_swpctx                  2926      2.08%      2.49% # number of callpals executed
-system.cpu0.kern.callpal_tbi                       49      0.03%      2.52% # number of callpals executed
-system.cpu0.kern.callpal_wrent                      7      0.00%      2.53% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                126411     89.95%     92.48% # number of callpals executed
-system.cpu0.kern.callpal_rdps                    5784      4.12%     96.59% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.59% # number of callpals executed
-system.cpu0.kern.callpal_wrusp                      2      0.00%     96.60% # number of callpals executed
-system.cpu0.kern.callpal_rdusp                      9      0.01%     96.60% # number of callpals executed
-system.cpu0.kern.callpal_whami                      2      0.00%     96.60% # number of callpals executed
-system.cpu0.kern.callpal_rti                     4273      3.04%     99.64% # number of callpals executed
-system.cpu0.kern.callpal_callsys                  366      0.26%     99.90% # number of callpals executed
-system.cpu0.kern.callpal_imb                      134      0.10%    100.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir                   115      0.06%      0.06% # number of callpals executed
+system.cpu0.kern.callpal_wrmces                     1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal_wrfen                      1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  3791      2.07%      2.14% # number of callpals executed
+system.cpu0.kern.callpal_tbi                       49      0.03%      2.17% # number of callpals executed
+system.cpu0.kern.callpal_wrent                      7      0.00%      2.17% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                167832     91.83%     94.01% # number of callpals executed
+system.cpu0.kern.callpal_rdps                    5780      3.16%     97.17% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.17% # number of callpals executed
+system.cpu0.kern.callpal_wrusp                      2      0.00%     97.17% # number of callpals executed
+system.cpu0.kern.callpal_rdusp                      9      0.00%     97.17% # number of callpals executed
+system.cpu0.kern.callpal_whami                      2      0.00%     97.18% # number of callpals executed
+system.cpu0.kern.callpal_rti                     4696      2.57%     99.75% # number of callpals executed
+system.cpu0.kern.callpal_callsys                  344      0.19%     99.93% # number of callpals executed
+system.cpu0.kern.callpal_imb                      122      0.07%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    155157                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    196249                       # number of hwrei instructions executed
 system.cpu0.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu0.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu0.kern.inst.quiesce                    6712                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count                     133285                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    53228     39.94%     39.94% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21                     245      0.18%     40.12% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22                    1895      1.42%     41.54% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30                     460      0.35%     41.89% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                   77457     58.11%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      107676                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     52768     49.01%     49.01% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21                      245      0.23%     49.23% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22                     1895      1.76%     50.99% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30                      460      0.43%     51.42% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    52308     48.58%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks                 3716215936                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0               3683825506     99.13%     99.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21                   40474      0.00%     99.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22                  162970      0.00%     99.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30                  103364      0.00%     99.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31                32083622      0.86%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used                    0.807863                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_0                  0.991358                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6184                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     174678                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    70736     40.50%     40.50% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21                     245      0.14%     40.64% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22                    1896      1.09%     41.72% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30                       8      0.00%     41.73% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31                  101793     58.27%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      140889                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     69374     49.24%     49.24% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21                      245      0.17%     49.41% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22                     1896      1.35%     50.76% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30                        8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    69366     49.23%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks                 3718155294                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0               3683661066     99.07%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21                   40474      0.00%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22                  163056      0.00%     99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                    2026      0.00%     99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31                34288672      0.92%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used                    0.806564                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_0                  0.980745                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.675317                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel                1221                      
-system.cpu0.kern.mode_good_user                  1222                      
+system.cpu0.kern.ipl_used_31                 0.681442                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel                1192                      
+system.cpu0.kern.mode_good_user                  1193                      
 system.cpu0.kern.mode_good_idle                     0                      
-system.cpu0.kern.mode_switch_kernel              6758                       # number of protection mode switches
-system.cpu0.kern.mode_switch_user                1222                       # number of protection mode switches
+system.cpu0.kern.mode_switch_kernel              7143                       # number of protection mode switches
+system.cpu0.kern.mode_switch_user                1193                       # number of protection mode switches
 system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good            0.306140                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.180675                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good            0.286108                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.166877                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel         3714429703     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user              1786231      0.05%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel         3716512331     99.96%     99.96% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user              1642961      0.04%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    2927                       # number of times the context was actually changed
-system.cpu0.kern.syscall                          217                       # number of syscalls executed
-system.cpu0.kern.syscall_fork                       8      3.69%      3.69% # number of syscalls executed
-system.cpu0.kern.syscall_read                      19      8.76%     12.44% # number of syscalls executed
-system.cpu0.kern.syscall_write                      3      1.38%     13.82% # number of syscalls executed
-system.cpu0.kern.syscall_close                     31     14.29%     28.11% # number of syscalls executed
-system.cpu0.kern.syscall_chdir                      1      0.46%     28.57% # number of syscalls executed
-system.cpu0.kern.syscall_obreak                     6      2.76%     31.34% # number of syscalls executed
-system.cpu0.kern.syscall_lseek                     10      4.61%     35.94% # number of syscalls executed
-system.cpu0.kern.syscall_getpid                     6      2.76%     38.71% # number of syscalls executed
-system.cpu0.kern.syscall_setuid                     2      0.92%     39.63% # number of syscalls executed
-system.cpu0.kern.syscall_getuid                     4      1.84%     41.47% # number of syscalls executed
-system.cpu0.kern.syscall_access                     6      2.76%     44.24% # number of syscalls executed
-system.cpu0.kern.syscall_dup                        2      0.92%     45.16% # number of syscalls executed
-system.cpu0.kern.syscall_open                      33     15.21%     60.37% # number of syscalls executed
-system.cpu0.kern.syscall_getgid                     4      1.84%     62.21% # number of syscalls executed
-system.cpu0.kern.syscall_sigprocmask               10      4.61%     66.82% # number of syscalls executed
-system.cpu0.kern.syscall_ioctl                      9      4.15%     70.97% # number of syscalls executed
-system.cpu0.kern.syscall_execve                     6      2.76%     73.73% # number of syscalls executed
-system.cpu0.kern.syscall_mmap                      25     11.52%     85.25% # number of syscalls executed
-system.cpu0.kern.syscall_munmap                     3      1.38%     86.64% # number of syscalls executed
-system.cpu0.kern.syscall_mprotect                   7      3.23%     89.86% # number of syscalls executed
-system.cpu0.kern.syscall_gethostname                1      0.46%     90.32% # number of syscalls executed
-system.cpu0.kern.syscall_dup2                       3      1.38%     91.71% # number of syscalls executed
-system.cpu0.kern.syscall_fcntl                      8      3.69%     95.39% # number of syscalls executed
-system.cpu0.kern.syscall_socket                     2      0.92%     96.31% # number of syscalls executed
-system.cpu0.kern.syscall_connect                    2      0.92%     97.24% # number of syscalls executed
-system.cpu0.kern.syscall_setgid                     2      0.92%     98.16% # number of syscalls executed
-system.cpu0.kern.syscall_getrlimit                  2      0.92%     99.08% # number of syscalls executed
-system.cpu0.kern.syscall_setsid                     2      0.92%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.013299                       # Percentage of non-idle cycles
-system.cpu0.numCycles                        49421041                       # number of cpu cycles simulated
-system.cpu0.num_insts                        49417215                       # Number of instructions executed
-system.cpu0.num_refs                         12829669                       # Number of memory references
-system.cpu1.dtb.accesses                       701326                       # DTB accesses
-system.cpu1.dtb.acv                                30                       # DTB access violations
-system.cpu1.dtb.hits                          5286923                       # DTB hits
-system.cpu1.dtb.misses                           3658                       # DTB misses
-system.cpu1.dtb.read_accesses                  474933                       # DTB read accesses
+system.cpu0.kern.swap_context                    3792                       # number of times the context was actually changed
+system.cpu0.kern.syscall                          199                       # number of syscalls executed
+system.cpu0.kern.syscall_fork                       8      4.02%      4.02% # number of syscalls executed
+system.cpu0.kern.syscall_read                      17      8.54%     12.56% # number of syscalls executed
+system.cpu0.kern.syscall_write                      4      2.01%     14.57% # number of syscalls executed
+system.cpu0.kern.syscall_close                     29     14.57%     29.15% # number of syscalls executed
+system.cpu0.kern.syscall_chdir                      1      0.50%     29.65% # number of syscalls executed
+system.cpu0.kern.syscall_obreak                     4      2.01%     31.66% # number of syscalls executed
+system.cpu0.kern.syscall_lseek                     10      5.03%     36.68% # number of syscalls executed
+system.cpu0.kern.syscall_getpid                     6      3.02%     39.70% # number of syscalls executed
+system.cpu0.kern.syscall_setuid                     1      0.50%     40.20% # number of syscalls executed
+system.cpu0.kern.syscall_getuid                     3      1.51%     41.71% # number of syscalls executed
+system.cpu0.kern.syscall_access                     6      3.02%     44.72% # number of syscalls executed
+system.cpu0.kern.syscall_dup                        2      1.01%     45.73% # number of syscalls executed
+system.cpu0.kern.syscall_open                      31     15.58%     61.31% # number of syscalls executed
+system.cpu0.kern.syscall_getgid                     3      1.51%     62.81% # number of syscalls executed
+system.cpu0.kern.syscall_sigprocmask               10      5.03%     67.84% # number of syscalls executed
+system.cpu0.kern.syscall_ioctl                      9      4.52%     72.36% # number of syscalls executed
+system.cpu0.kern.syscall_execve                     6      3.02%     75.38% # number of syscalls executed
+system.cpu0.kern.syscall_mmap                      20     10.05%     85.43% # number of syscalls executed
+system.cpu0.kern.syscall_munmap                     3      1.51%     86.93% # number of syscalls executed
+system.cpu0.kern.syscall_mprotect                   5      2.51%     89.45% # number of syscalls executed
+system.cpu0.kern.syscall_gethostname                1      0.50%     89.95% # number of syscalls executed
+system.cpu0.kern.syscall_dup2                       3      1.51%     91.46% # number of syscalls executed
+system.cpu0.kern.syscall_fcntl                      8      4.02%     95.48% # number of syscalls executed
+system.cpu0.kern.syscall_socket                     2      1.01%     96.48% # number of syscalls executed
+system.cpu0.kern.syscall_connect                    2      1.01%     97.49% # number of syscalls executed
+system.cpu0.kern.syscall_setgid                     1      0.50%     97.99% # number of syscalls executed
+system.cpu0.kern.syscall_getrlimit                  2      1.01%     98.99% # number of syscalls executed
+system.cpu0.kern.syscall_setsid                     2      1.01%    100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction                0.015057                       # Percentage of non-idle cycles
+system.cpu0.numCycles                        55984201                       # number of cpu cycles simulated
+system.cpu0.num_insts                        55980548                       # Number of instructions executed
+system.cpu0.num_refs                         15081320                       # Number of memory references
+system.cpu1.dtb.accesses                       761000                       # DTB accesses
+system.cpu1.dtb.acv                                32                       # DTB access violations
+system.cpu1.dtb.hits                          2653187                       # DTB hits
+system.cpu1.dtb.misses                           4173                       # DTB misses
+system.cpu1.dtb.read_accesses                  523552                       # DTB read accesses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_hits                     3100008                       # DTB read hits
-system.cpu1.dtb.read_misses                      3260                       # DTB read misses
-system.cpu1.dtb.write_accesses                 226393                       # DTB write accesses
-system.cpu1.dtb.write_acv                          30                       # DTB write access violations
-system.cpu1.dtb.write_hits                    2186915                       # DTB write hits
-system.cpu1.dtb.write_misses                      398                       # DTB write misses
-system.cpu1.idle_fraction                    0.995381                       # Percentage of idle cycles
-system.cpu1.itb.accesses                      1714255                       # ITB accesses
+system.cpu1.dtb.read_hits                     1675663                       # DTB read hits
+system.cpu1.dtb.read_misses                      3798                       # DTB read misses
+system.cpu1.dtb.write_accesses                 237448                       # DTB write accesses
+system.cpu1.dtb.write_acv                          32                       # DTB write access violations
+system.cpu1.dtb.write_hits                     977524                       # DTB write hits
+system.cpu1.dtb.write_misses                      375                       # DTB write misses
+system.cpu1.idle_fraction                    0.997598                       # Percentage of idle cycles
+system.cpu1.itb.accesses                      1845187                       # ITB accesses
 system.cpu1.itb.acv                                 0                       # ITB acv
-system.cpu1.itb.hits                          1712856                       # ITB hits
-system.cpu1.itb.misses                           1399                       # ITB misses
-system.cpu1.kern.callpal                        81795                       # number of callpals executed
+system.cpu1.itb.hits                          1843600                       # ITB hits
+system.cpu1.itb.misses                           1587                       # ITB misses
+system.cpu1.kern.callpal                        34405                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir                   460      0.56%      0.56% # number of callpals executed
-system.cpu1.kern.callpal_wrmces                     1      0.00%      0.56% # number of callpals executed
-system.cpu1.kern.callpal_wrfen                      1      0.00%      0.57% # number of callpals executed
-system.cpu1.kern.callpal_swpctx                  2245      2.74%      3.31% # number of callpals executed
-system.cpu1.kern.callpal_tbi                        4      0.00%      3.32% # number of callpals executed
-system.cpu1.kern.callpal_wrent                      7      0.01%      3.32% # number of callpals executed
-system.cpu1.kern.callpal_swpipl                 71908     87.91%     91.24% # number of callpals executed
-system.cpu1.kern.callpal_rdps                    3034      3.71%     94.95% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.95% # number of callpals executed
-system.cpu1.kern.callpal_wrusp                      5      0.01%     94.95% # number of callpals executed
-system.cpu1.kern.callpal_whami                      3      0.00%     94.96% # number of callpals executed
-system.cpu1.kern.callpal_rti                     3913      4.78%     99.74% # number of callpals executed
-system.cpu1.kern.callpal_callsys                  165      0.20%     99.94% # number of callpals executed
-system.cpu1.kern.callpal_imb                       46      0.06%    100.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir                     8      0.02%      0.03% # number of callpals executed
+system.cpu1.kern.callpal_wrmces                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal_wrfen                      1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal_swpctx                   468      1.36%      1.39% # number of callpals executed
+system.cpu1.kern.callpal_tbi                        5      0.01%      1.41% # number of callpals executed
+system.cpu1.kern.callpal_wrent                      7      0.02%      1.43% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 28030     81.47%     82.90% # number of callpals executed
+system.cpu1.kern.callpal_rdps                    3042      8.84%     91.74% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp                      1      0.00%     91.74% # number of callpals executed
+system.cpu1.kern.callpal_wrusp                      5      0.01%     91.76% # number of callpals executed
+system.cpu1.kern.callpal_whami                      3      0.01%     91.77% # number of callpals executed
+system.cpu1.kern.callpal_rti                     2586      7.52%     99.28% # number of callpals executed
+system.cpu1.kern.callpal_callsys                  187      0.54%     99.83% # number of callpals executed
+system.cpu1.kern.callpal_imb                       59      0.17%    100.00% # number of callpals executed
 system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     89345                       # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei                     42209                       # number of hwrei instructions executed
 system.cpu1.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu1.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu1.kern.inst.quiesce                    2592                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count                      78283                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0                    30809     39.36%     39.36% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22                    1894      2.42%     41.78% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30                     567      0.72%     42.50% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31                   45013     57.50%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good                       61674                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0                     29890     48.46%     48.46% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22                     1894      3.07%     51.54% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30                      567      0.92%     52.45% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31                    29323     47.55%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks                 3715795413                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0               3690163762     99.31%     99.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22                  162884      0.00%     99.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30                  130370      0.00%     99.32% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31                25338397      0.68%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used                    0.787834                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_0                  0.970171                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2146                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count                      32627                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                    11165     34.22%     34.22% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22                    1895      5.81%     40.03% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30                     115      0.35%     40.38% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31                   19452     59.62%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       24195                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                     11150     46.08%     46.08% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22                     1895      7.83%     53.92% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30                      115      0.48%     54.39% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                    11035     45.61%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks                 3717733449                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0               3695802393     99.41%     99.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22                  162970      0.00%     99.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30                   29122      0.00%     99.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31                21738964      0.58%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used                    0.741564                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0                  0.998657                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31                 0.651434                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel                1028                      
-system.cpu1.kern.mode_good_user                   535                      
-system.cpu1.kern.mode_good_idle                   493                      
-system.cpu1.kern.mode_switch_kernel              2307                       # number of protection mode switches
-system.cpu1.kern.mode_switch_user                 535                       # number of protection mode switches
-system.cpu1.kern.mode_switch_idle                2948                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good            0.355095                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel     0.445600                       # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31                 0.567294                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel                 602                      
+system.cpu1.kern.mode_good_user                   563                      
+system.cpu1.kern.mode_good_idle                    39                      
+system.cpu1.kern.mode_switch_kernel              1011                       # number of protection mode switches
+system.cpu1.kern.mode_switch_user                 563                       # number of protection mode switches
+system.cpu1.kern.mode_switch_idle                2045                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good            0.332689                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel     0.595450                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle       0.167232                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel           12634755      0.34%      0.34% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user              1807179      0.05%      0.39% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle           3700889452     99.61%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2246                       # number of times the context was actually changed
-system.cpu1.kern.syscall                          112                       # number of syscalls executed
-system.cpu1.kern.syscall_read                      11      9.82%      9.82% # number of syscalls executed
-system.cpu1.kern.syscall_write                      1      0.89%     10.71% # number of syscalls executed
-system.cpu1.kern.syscall_close                     12     10.71%     21.43% # number of syscalls executed
-system.cpu1.kern.syscall_chmod                      1      0.89%     22.32% # number of syscalls executed
-system.cpu1.kern.syscall_obreak                     9      8.04%     30.36% # number of syscalls executed
-system.cpu1.kern.syscall_setuid                     2      1.79%     32.14% # number of syscalls executed
-system.cpu1.kern.syscall_getuid                     2      1.79%     33.93% # number of syscalls executed
-system.cpu1.kern.syscall_access                     5      4.46%     38.39% # number of syscalls executed
-system.cpu1.kern.syscall_open                      22     19.64%     58.04% # number of syscalls executed
-system.cpu1.kern.syscall_getgid                     2      1.79%     59.82% # number of syscalls executed
-system.cpu1.kern.syscall_ioctl                      1      0.89%     60.71% # number of syscalls executed
-system.cpu1.kern.syscall_readlink                   1      0.89%     61.61% # number of syscalls executed
-system.cpu1.kern.syscall_execve                     1      0.89%     62.50% # number of syscalls executed
-system.cpu1.kern.syscall_mmap                      29     25.89%     88.39% # number of syscalls executed
-system.cpu1.kern.syscall_mprotect                   9      8.04%     96.43% # number of syscalls executed
-system.cpu1.kern.syscall_fcntl                      2      1.79%     98.21% # number of syscalls executed
-system.cpu1.kern.syscall_setgid                     2      1.79%    100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction                0.004619                       # Percentage of non-idle cycles
-system.cpu1.numCycles                        17164125                       # number of cpu cycles simulated
-system.cpu1.num_insts                        17162726                       # Number of instructions executed
-system.cpu1.num_refs                          5316705                       # Number of memory references
+system.cpu1.kern.mode_switch_good_idle       0.019071                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel            4713507      0.13%      0.13% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user              1950903      0.05%      0.18% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle           3710606044     99.82%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     469                       # number of times the context was actually changed
+system.cpu1.kern.syscall                          130                       # number of syscalls executed
+system.cpu1.kern.syscall_read                      13     10.00%     10.00% # number of syscalls executed
+system.cpu1.kern.syscall_close                     14     10.77%     20.77% # number of syscalls executed
+system.cpu1.kern.syscall_chmod                      1      0.77%     21.54% # number of syscalls executed
+system.cpu1.kern.syscall_obreak                    11      8.46%     30.00% # number of syscalls executed
+system.cpu1.kern.syscall_setuid                     3      2.31%     32.31% # number of syscalls executed
+system.cpu1.kern.syscall_getuid                     3      2.31%     34.62% # number of syscalls executed
+system.cpu1.kern.syscall_access                     5      3.85%     38.46% # number of syscalls executed
+system.cpu1.kern.syscall_open                      24     18.46%     56.92% # number of syscalls executed
+system.cpu1.kern.syscall_getgid                     3      2.31%     59.23% # number of syscalls executed
+system.cpu1.kern.syscall_ioctl                      1      0.77%     60.00% # number of syscalls executed
+system.cpu1.kern.syscall_readlink                   1      0.77%     60.77% # number of syscalls executed
+system.cpu1.kern.syscall_execve                     1      0.77%     61.54% # number of syscalls executed
+system.cpu1.kern.syscall_mmap                      34     26.15%     87.69% # number of syscalls executed
+system.cpu1.kern.syscall_mprotect                  11      8.46%     96.15% # number of syscalls executed
+system.cpu1.kern.syscall_fcntl                      2      1.54%     97.69% # number of syscalls executed
+system.cpu1.kern.syscall_setgid                     3      2.31%    100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction                0.002402                       # Percentage of non-idle cycles
+system.cpu1.numCycles                         8930639                       # number of cpu cycles simulated
+system.cpu1.num_insts                         8929052                       # Number of instructions executed
+system.cpu1.num_refs                          2665347                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
index d55b33424..14aa2c9ff 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
@@ -1,6 +1,6 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
 warn: 195723: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index 76bd8d3c2..18365db1c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:07:02
-M5 started Sun Oct  8 14:07:57 2006
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Oct  8 2006 21:57:24
+M5 started Sun Oct  8 21:58:13 2006
+M5 executing on zed.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
-Exiting @ tick 3716216351 because m5_exit instruction encountered
+Exiting @ tick 3718155709 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
index 1d150a047..5461cc4ab 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 1 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -16,7 +16,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
k_argc = 0 
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
 
CallbackFixup 0 18000, t7=FFFFFC000070C000
-
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
@@ -32,7 +32,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP mode deactivated.
 
Brought up 1 CPUs
@@ -54,9 +54,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
io scheduler cfq registered
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
-
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
-
ns83820: irq bound to CPU 0
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index c9661f182..e276e91a7 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,86 +1,86 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1269893                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197712                       # Number of bytes of host memory used
-host_seconds                                    48.70                       # Real time elapsed on the host
-host_tick_rate                               74667785                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1389289                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197652                       # Number of bytes of host memory used
+host_seconds                                    44.48                       # Real time elapsed on the host
+host_tick_rate                               81712411                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    61839827                       # Number of instructions simulated
-sim_seconds                                  1.818060                       # Number of seconds simulated
-sim_ticks                                  3636120569                       # Number of ticks simulated
-system.cpu.dtb.accesses                       1304498                       # DTB accesses
+sim_insts                                    61788439                       # Number of instructions simulated
+sim_seconds                                  1.817090                       # Number of seconds simulated
+sim_ticks                                  3634179176                       # Number of ticks simulated
+system.cpu.dtb.accesses                       1304494                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          16565944                       # DTB hits
+system.cpu.dtb.hits                          16552094                       # DTB hits
 system.cpu.dtb.misses                           11425                       # DTB misses
-system.cpu.dtb.read_accesses                   900427                       # DTB read accesses
+system.cpu.dtb.read_accesses                   900425                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                     10044011                       # DTB read hits
+system.cpu.dtb.read_hits                     10038384                       # DTB read hits
 system.cpu.dtb.read_misses                      10280                       # DTB read misses
-system.cpu.dtb.write_accesses                  404071                       # DTB write accesses
+system.cpu.dtb.write_accesses                  404069                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6521933                       # DTB write hits
+system.cpu.dtb.write_hits                     6513710                       # DTB write hits
 system.cpu.dtb.write_misses                      1145                       # DTB write misses
-system.cpu.idle_fraction                     0.982991                       # Percentage of idle cycles
+system.cpu.idle_fraction                     0.982997                       # Percentage of idle cycles
 system.cpu.itb.accesses                       3281310                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
 system.cpu.itb.hits                           3276320                       # ITB hits
 system.cpu.itb.misses                            4990                       # ITB misses
-system.cpu.kern.callpal                        193942                       # number of callpals executed
+system.cpu.kern.callpal                        193842                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx                   4207      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal_swpctx                   4203      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal_wrent                       7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 176844     91.18%     93.39% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 176751     91.18%     93.38% # number of callpals executed
 system.cpu.kern.callpal_rdps                     6881      3.55%     96.93% # number of callpals executed
 system.cpu.kern.callpal_wrkgp                       1      0.00%     96.94% # number of callpals executed
 system.cpu.kern.callpal_wrusp                       7      0.00%     96.94% # number of callpals executed
 system.cpu.kern.callpal_rdusp                       9      0.00%     96.94% # number of callpals executed
 system.cpu.kern.callpal_whami                       2      0.00%     96.94% # number of callpals executed
-system.cpu.kern.callpal_rti                      5214      2.69%     99.63% # number of callpals executed
+system.cpu.kern.callpal_rti                      5211      2.69%     99.63% # number of callpals executed
 system.cpu.kern.callpal_callsys                   531      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     213009                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     212908                       # number of hwrei instructions executed
 system.cpu.kern.inst.ivlb                           0                       # number of ivlb instructions executed
 system.cpu.kern.inst.ivle                           0                       # number of ivle instructions executed
-system.cpu.kern.inst.quiesce                     6282                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      184158                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     75390     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6207                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      184061                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     75348     40.94%     40.94% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_21                      245      0.13%     41.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22                     1854      1.01%     42.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                   106669     57.92%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       150141                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      74021     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count_22                     1853      1.01%     42.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31                   106615     57.92%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       150060                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      73981     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_21                       245      0.16%     49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22                      1854      1.23%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     74021     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                  3636120154                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0                3601418096     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good_22                      1853      1.23%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31                     73981     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                  3634178761                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0                3599646819     99.05%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_21                    40474      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22                   159444      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31                 34502140      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used                     0.815284                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_0                   0.981841                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_ticks_22                   159358      0.00%     99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31                 34332110      0.94%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used                     0.815273                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_0                   0.981858                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.693932                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel                 1937                      
-system.cpu.kern.mode_good_user                   1757                      
+system.cpu.kern.ipl_used_31                  0.693908                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1938                      
+system.cpu.kern.mode_good_user                   1758                      
 system.cpu.kern.mode_good_idle                    180                      
-system.cpu.kern.mode_switch_kernel               5982                       # number of protection mode switches
-system.cpu.kern.mode_switch_user                 1757                       # number of protection mode switches
-system.cpu.kern.mode_switch_idle                 2103                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             0.393619                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.323805                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_kernel               5978                       # number of protection mode switches
+system.cpu.kern.mode_switch_user                 1758                       # number of protection mode switches
+system.cpu.kern.mode_switch_idle                 2102                       # number of protection mode switches
+system.cpu.kern.mode_switch_good             0.393983                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.324189                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle        0.085592                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel            54647278      1.50%      1.50% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user               3591234      0.10%      1.60% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle            3577881640     98.40%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4208                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good_idle        0.085633                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel            54682435      1.50%      1.50% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user               3591244      0.10%      1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle            3575905080     98.40%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4204                       # number of times the context was actually changed
 system.cpu.kern.syscall                           329                       # number of syscalls executed
 system.cpu.kern.syscall_fork                        8      2.43%      2.43% # number of syscalls executed
 system.cpu.kern.syscall_read                       30      9.12%     11.55% # number of syscalls executed
@@ -112,10 +112,10 @@ system.cpu.kern.syscall_connect                     2      0.61%     97.57% # nu
 system.cpu.kern.syscall_setgid                      4      1.22%     98.78% # number of syscalls executed
 system.cpu.kern.syscall_getrlimit                   2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_setsid                      2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.017009                       # Percentage of non-idle cycles
-system.cpu.numCycles                         61845001                       # number of cpu cycles simulated
-system.cpu.num_insts                         61839827                       # Number of instructions executed
-system.cpu.num_refs                          16814484                       # Number of memory references
+system.cpu.not_idle_fraction                 0.017003                       # Percentage of non-idle cycles
+system.cpu.numCycles                         61793613                       # number of cpu cycles simulated
+system.cpu.num_insts                         61788439                       # Number of instructions executed
+system.cpu.num_refs                          16800623                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
index 4741dd710..6204251a5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
@@ -1,4 +1,4 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index f7fe15009..bb7f4ca1e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:07:02
-M5 started Sun Oct  8 14:07:07 2006
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Oct  8 2006 21:57:24
+M5 started Sun Oct  8 21:57:28 2006
+M5 executing on zed.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
-Exiting @ tick 3636120569 because m5_exit instruction encountered
+Exiting @ tick 3634179176 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
index 57a610390..27adebb82 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 2 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -19,7 +19,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
 
CallbackFixup 0 18000, t7=FFFFFC000070C000
 
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
-
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
@@ -35,7 +35,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
 
Slave CPU 1 console command START
@@ -59,9 +59,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
io scheduler cfq registered
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
-
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
-
ns83820: irq bound to CPU 1
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
index 4f8408501..ff9a06cc7 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
@@ -1,91 +1,91 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 779301                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197344                       # Number of bytes of host memory used
-host_seconds                                    85.22                       # Real time elapsed on the host
-host_tick_rate                               43826709                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 719379                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197268                       # Number of bytes of host memory used
+host_seconds                                    92.21                       # Real time elapsed on the host
+host_tick_rate                               40502079                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    66411500                       # Number of instructions simulated
-sim_seconds                                  1.867451                       # Number of seconds simulated
-sim_ticks                                  3734901822                       # Number of ticks simulated
+sim_insts                                    66337257                       # Number of instructions simulated
+sim_seconds                                  1.867449                       # Number of seconds simulated
+sim_ticks                                  3734898877                       # Number of ticks simulated
 system.cpu0.dtb.accesses                       828318                       # DTB accesses
 system.cpu0.dtb.acv                               315                       # DTB access violations
-system.cpu0.dtb.hits                         13279471                       # DTB hits
+system.cpu0.dtb.hits                         13264910                       # DTB hits
 system.cpu0.dtb.misses                           7094                       # DTB misses
 system.cpu0.dtb.read_accesses                  572336                       # DTB read accesses
 system.cpu0.dtb.read_acv                          200                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8207004                       # DTB read hits
+system.cpu0.dtb.read_hits                     8201218                       # DTB read hits
 system.cpu0.dtb.read_misses                      6394                       # DTB read misses
 system.cpu0.dtb.write_accesses                 255982                       # DTB write accesses
 system.cpu0.dtb.write_acv                         115                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5072467                       # DTB write hits
+system.cpu0.dtb.write_hits                    5063692                       # DTB write hits
 system.cpu0.dtb.write_misses                      700                       # DTB write misses
-system.cpu0.idle_fraction                    0.982495                       # Percentage of idle cycles
+system.cpu0.idle_fraction                    0.982517                       # Percentage of idle cycles
 system.cpu0.itb.accesses                      1888651                       # ITB accesses
 system.cpu0.itb.acv                               166                       # ITB acv
 system.cpu0.itb.hits                          1885318                       # ITB hits
 system.cpu0.itb.misses                           3333                       # ITB misses
-system.cpu0.kern.callpal                       146866                       # number of callpals executed
+system.cpu0.kern.callpal                       146863                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir                   507      0.35%      0.35% # number of callpals executed
+system.cpu0.kern.callpal_wripir                   506      0.34%      0.35% # number of callpals executed
 system.cpu0.kern.callpal_wrmces                     1      0.00%      0.35% # number of callpals executed
 system.cpu0.kern.callpal_wrfen                      1      0.00%      0.35% # number of callpals executed
 system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.35% # number of callpals executed
-system.cpu0.kern.callpal_swpctx                  2966      2.02%      2.37% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  2962      2.02%      2.36% # number of callpals executed
 system.cpu0.kern.callpal_tbi                       47      0.03%      2.40% # number of callpals executed
 system.cpu0.kern.callpal_wrent                      7      0.00%      2.40% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                132441     90.18%     92.58% # number of callpals executed
-system.cpu0.kern.callpal_rdps                    6235      4.25%     96.83% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                132443     90.18%     92.58% # number of callpals executed
+system.cpu0.kern.callpal_rdps                    6236      4.25%     96.83% # number of callpals executed
 system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.83% # number of callpals executed
 system.cpu0.kern.callpal_wrusp                      2      0.00%     96.83% # number of callpals executed
 system.cpu0.kern.callpal_rdusp                      8      0.01%     96.84% # number of callpals executed
 system.cpu0.kern.callpal_whami                      2      0.00%     96.84% # number of callpals executed
-system.cpu0.kern.callpal_rti                     4201      2.86%     99.70% # number of callpals executed
+system.cpu0.kern.callpal_rti                     4200      2.86%     99.70% # number of callpals executed
 system.cpu0.kern.callpal_callsys                  317      0.22%     99.91% # number of callpals executed
 system.cpu0.kern.callpal_imb                      128      0.09%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    160336                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    160332                       # number of hwrei instructions executed
 system.cpu0.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu0.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu0.kern.inst.quiesce                    6712                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    6637                       # number of quiesce instructions executed
 system.cpu0.kern.ipl_count                     139203                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    55746     40.05%     40.05% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    55744     40.05%     40.05% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_21                     245      0.18%     40.22% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_22                    1904      1.37%     41.59% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30                     411      0.30%     41.89% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                   80897     58.11%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      112531                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     55191     49.05%     49.05% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count_30                     410      0.29%     41.88% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31                   80900     58.12%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      112527                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     55189     49.05%     49.05% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_21                      245      0.22%     49.26% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_22                     1904      1.69%     50.95% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30                      411      0.37%     51.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    54780     48.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30                      410      0.36%     51.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    54779     48.68%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_ticks                 3734378988                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0               3696129107     98.98%     98.98% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0               3696326531     98.98%     98.98% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks_21                   53683      0.00%     98.98% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22                  224672      0.01%     98.98% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30                  128598      0.00%     98.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31                37842928      1.01%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used                    0.808395                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_ticks_22                  224672      0.01%     98.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                  128286      0.00%     98.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31                37645816      1.01%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used                    0.808366                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_0                  0.990044                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.677157                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31                 0.677120                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.mode_good_kernel                1095                      
 system.cpu0.kern.mode_good_user                  1095                      
 system.cpu0.kern.mode_good_idle                     0                      
-system.cpu0.kern.mode_switch_kernel              6633                       # number of protection mode switches
+system.cpu0.kern.mode_switch_kernel              6628                       # number of protection mode switches
 system.cpu0.kern.mode_switch_user                1095                       # number of protection mode switches
 system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good            0.283385                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.165084                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good            0.283569                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.165208                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel         3730045371     99.93%     99.93% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel         3730042316     99.93%     99.93% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_user              2718822      0.07%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    2967                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    2963                       # number of times the context was actually changed
 system.cpu0.kern.syscall                          179                       # number of syscalls executed
 system.cpu0.kern.syscall_fork                       7      3.91%      3.91% # number of syscalls executed
 system.cpu0.kern.syscall_read                      14      7.82%     11.73% # number of syscalls executed
@@ -115,84 +115,84 @@ system.cpu0.kern.syscall_connect                    2      1.12%     97.77% # nu
 system.cpu0.kern.syscall_setgid                     1      0.56%     98.32% # number of syscalls executed
 system.cpu0.kern.syscall_getrlimit                  1      0.56%     98.88% # number of syscalls executed
 system.cpu0.kern.syscall_setsid                     2      1.12%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.017505                       # Percentage of non-idle cycles
+system.cpu0.not_idle_fraction                0.017483                       # Percentage of non-idle cycles
 system.cpu0.numCycles                               0                       # number of cpu cycles simulated
-system.cpu0.num_insts                        52039310                       # Number of instructions executed
-system.cpu0.num_refs                         13510641                       # Number of memory references
-system.cpu1.dtb.accesses                       477045                       # DTB accesses
+system.cpu0.num_insts                        51973218                       # Number of instructions executed
+system.cpu0.num_refs                         13496062                       # Number of memory references
+system.cpu1.dtb.accesses                       477041                       # DTB accesses
 system.cpu1.dtb.acv                                52                       # DTB access violations
-system.cpu1.dtb.hits                          4567143                       # DTB hits
+system.cpu1.dtb.hits                          4561390                       # DTB hits
 system.cpu1.dtb.misses                           4359                       # DTB misses
-system.cpu1.dtb.read_accesses                  328553                       # DTB read accesses
+system.cpu1.dtb.read_accesses                  328551                       # DTB read accesses
 system.cpu1.dtb.read_acv                           10                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2660612                       # DTB read hits
+system.cpu1.dtb.read_hits                     2657400                       # DTB read hits
 system.cpu1.dtb.read_misses                      3911                       # DTB read misses
-system.cpu1.dtb.write_accesses                 148492                       # DTB write accesses
+system.cpu1.dtb.write_accesses                 148490                       # DTB write accesses
 system.cpu1.dtb.write_acv                          42                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1906531                       # DTB write hits
+system.cpu1.dtb.write_hits                    1903990                       # DTB write hits
 system.cpu1.dtb.write_misses                      448                       # DTB write misses
-system.cpu1.idle_fraction                    0.994923                       # Percentage of idle cycles
+system.cpu1.idle_fraction                    0.994927                       # Percentage of idle cycles
 system.cpu1.itb.accesses                      1392687                       # ITB accesses
 system.cpu1.itb.acv                                18                       # ITB acv
 system.cpu1.itb.hits                          1391015                       # ITB hits
 system.cpu1.itb.misses                           1672                       # ITB misses
-system.cpu1.kern.callpal                        74475                       # number of callpals executed
+system.cpu1.kern.callpal                        74370                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir                   411      0.55%      0.55% # number of callpals executed
+system.cpu1.kern.callpal_wripir                   410      0.55%      0.55% # number of callpals executed
 system.cpu1.kern.callpal_wrmces                     1      0.00%      0.55% # number of callpals executed
 system.cpu1.kern.callpal_wrfen                      1      0.00%      0.56% # number of callpals executed
-system.cpu1.kern.callpal_swpctx                  2106      2.83%      3.38% # number of callpals executed
+system.cpu1.kern.callpal_swpctx                  2102      2.83%      3.38% # number of callpals executed
 system.cpu1.kern.callpal_tbi                        6      0.01%      3.39% # number of callpals executed
 system.cpu1.kern.callpal_wrent                      7      0.01%      3.40% # number of callpals executed
-system.cpu1.kern.callpal_swpipl                 65169     87.50%     90.91% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 65072     87.50%     90.90% # number of callpals executed
 system.cpu1.kern.callpal_rdps                    2603      3.50%     94.40% # number of callpals executed
 system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.40% # number of callpals executed
 system.cpu1.kern.callpal_wrusp                      5      0.01%     94.41% # number of callpals executed
 system.cpu1.kern.callpal_rdusp                      1      0.00%     94.41% # number of callpals executed
 system.cpu1.kern.callpal_whami                      3      0.00%     94.41% # number of callpals executed
-system.cpu1.kern.callpal_rti                     3893      5.23%     99.64% # number of callpals executed
+system.cpu1.kern.callpal_rti                     3890      5.23%     99.64% # number of callpals executed
 system.cpu1.kern.callpal_callsys                  214      0.29%     99.93% # number of callpals executed
 system.cpu1.kern.callpal_imb                       52      0.07%    100.00% # number of callpals executed
 system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     82987                       # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei                     82881                       # number of hwrei instructions executed
 system.cpu1.kern.inst.ivlb                          0                       # number of ivlb instructions executed
 system.cpu1.kern.inst.ivle                          0                       # number of ivle instructions executed
-system.cpu1.kern.inst.quiesce                    2512                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count                      71472                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0                    27792     38.89%     38.89% # number of times we switched to this ipl
+system.cpu1.kern.inst.quiesce                    2511                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count                      71371                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                    27750     38.88%     38.88% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count_22                    1902      2.66%     41.55% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30                     507      0.71%     42.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31                   41271     57.74%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good                       55838                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0                     26968     48.30%     48.30% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22                     1902      3.41%     51.70% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30                      507      0.91%     52.61% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31                    26461     47.39%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks                 3734901376                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0               3704875983     99.20%     99.20% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_count_30                     506      0.71%     42.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31                   41213     57.74%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       55758                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                     26928     48.29%     48.29% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22                     1902      3.41%     51.71% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30                      506      0.91%     52.61% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                    26422     47.39%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks                 3734898431                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0               3704872588     99.20%     99.20% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks_22                  224436      0.01%     99.20% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30                  162794      0.00%     99.21% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31                29638163      0.79%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used                    0.781257                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_0                  0.970351                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_ticks_30                  162482      0.00%     99.21% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31                29638925      0.79%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used                    0.781242                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_0                  0.970378                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31                 0.641152                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel                1094                      
+system.cpu1.kern.ipl_used_31                 0.641108                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel                1093                      
 system.cpu1.kern.mode_good_user                   662                      
-system.cpu1.kern.mode_good_idle                   432                      
-system.cpu1.kern.mode_switch_kernel              2358                       # number of protection mode switches
+system.cpu1.kern.mode_good_idle                   431                      
+system.cpu1.kern.mode_switch_kernel              2354                       # number of protection mode switches
 system.cpu1.kern.mode_switch_user                 662                       # number of protection mode switches
-system.cpu1.kern.mode_switch_idle                2831                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good            0.373953                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel     0.463953                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_idle                2830                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good            0.373931                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel     0.464316                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle       0.152596                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel           13374855      0.36%      0.36% # number of ticks spent at the given mode
+system.cpu1.kern.mode_switch_good_idle       0.152297                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel           13359666      0.36%      0.36% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks_user              1967356      0.05%      0.41% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle           3719559163     99.59%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2107                       # number of times the context was actually changed
+system.cpu1.kern.mode_ticks_idle           3719571407     99.59%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2103                       # number of times the context was actually changed
 system.cpu1.kern.syscall                          150                       # number of syscalls executed
 system.cpu1.kern.syscall_fork                       1      0.67%      0.67% # number of syscalls executed
 system.cpu1.kern.syscall_read                      16     10.67%     11.33% # number of syscalls executed
@@ -216,10 +216,10 @@ system.cpu1.kern.syscall_dup2                       1      0.67%     96.00% # nu
 system.cpu1.kern.syscall_fcntl                      2      1.33%     97.33% # number of syscalls executed
 system.cpu1.kern.syscall_setgid                     3      2.00%     99.33% # number of syscalls executed
 system.cpu1.kern.syscall_getrlimit                  1      0.67%    100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction                0.005077                       # Percentage of non-idle cycles
+system.cpu1.not_idle_fraction                0.005073                       # Percentage of non-idle cycles
 system.cpu1.numCycles                               0                       # number of cpu cycles simulated
-system.cpu1.num_insts                        14372190                       # Number of instructions executed
-system.cpu1.num_refs                          4596339                       # Number of memory references
+system.cpu1.num_insts                        14364039                       # Number of instructions executed
+system.cpu1.num_refs                          4590544                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -234,7 +234,7 @@ system.disk2.dma_write_full_pages                   1                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk        no value                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
 system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
index 64d80c0d2..c8703fde1 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
@@ -1,6 +1,6 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
 warn: 271343: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 3b92a25f9..498a94b6f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:07:02
-M5 started Sun Oct  8 14:10:09 2006
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Oct  8 2006 21:57:24
+M5 started Sun Oct  8 22:00:29 2006
+M5 executing on zed.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-Exiting @ tick 3734901822 because m5_exit instruction encountered
+Exiting @ tick 3734898877 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
index 1d150a047..5461cc4ab 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
@@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memsize 8000000 pages 4000 
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
 
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 1 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
@@ -16,7 +16,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
k_argc = 0 
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
 
CallbackFixup 0 18000, t7=FFFFFC000070C000
-
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
 
Command line: root=/dev/hda1 console=ttyS0
@@ -32,7 +32,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Console: colour dummy device 80x25
 
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
 
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-
Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP mode deactivated.
 
Brought up 1 CPUs
@@ -54,9 +54,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
io scheduler cfq registered
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
-
sinic.c: M5 Simple Integrated NIC driver
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
-
ns83820: irq bound to CPU 0
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
index 8b1a2f192..ba645e5c7 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
@@ -1,86 +1,86 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 778282                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 196900                       # Number of bytes of host memory used
-host_seconds                                    79.42                       # Real time elapsed on the host
-host_tick_rate                               45984556                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 740935                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196820                       # Number of bytes of host memory used
+host_seconds                                    83.36                       # Real time elapsed on the host
+host_tick_rate                               43810981                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-sim_insts                                    61806956                       # Number of instructions simulated
-sim_seconds                                  1.825933                       # Number of seconds simulated
-sim_ticks                                  3651865694                       # Number of ticks simulated
-system.cpu.dtb.accesses                       1304498                       # DTB accesses
+sim_insts                                    61760478                       # Number of instructions simulated
+sim_seconds                                  1.825937                       # Number of seconds simulated
+sim_ticks                                  3651873858                       # Number of ticks simulated
+system.cpu.dtb.accesses                       1304494                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          16557993                       # DTB hits
+system.cpu.dtb.hits                          16545335                       # DTB hits
 system.cpu.dtb.misses                           11425                       # DTB misses
-system.cpu.dtb.read_accesses                   900427                       # DTB read accesses
+system.cpu.dtb.read_accesses                   900425                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                     10039007                       # DTB read hits
+system.cpu.dtb.read_hits                     10034117                       # DTB read hits
 system.cpu.dtb.read_misses                      10280                       # DTB read misses
-system.cpu.dtb.write_accesses                  404071                       # DTB write accesses
+system.cpu.dtb.write_accesses                  404069                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6518986                       # DTB write hits
+system.cpu.dtb.write_hits                     6511218                       # DTB write hits
 system.cpu.dtb.write_misses                      1145                       # DTB write misses
-system.cpu.idle_fraction                     0.978522                       # Percentage of idle cycles
+system.cpu.idle_fraction                     0.978539                       # Percentage of idle cycles
 system.cpu.itb.accesses                       3281311                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
 system.cpu.itb.hits                           3276321                       # ITB hits
 system.cpu.itb.misses                            4990                       # ITB misses
-system.cpu.kern.callpal                        194059                       # number of callpals executed
+system.cpu.kern.callpal                        193987                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx                   4207      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal_swpctx                   4203      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal_wrent                       7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 176948     91.18%     93.38% # number of callpals executed
-system.cpu.kern.callpal_rdps                     6887      3.55%     96.93% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 176881     91.18%     93.38% # number of callpals executed
+system.cpu.kern.callpal_rdps                     6888      3.55%     96.93% # number of callpals executed
 system.cpu.kern.callpal_wrkgp                       1      0.00%     96.93% # number of callpals executed
 system.cpu.kern.callpal_wrusp                       7      0.00%     96.94% # number of callpals executed
 system.cpu.kern.callpal_rdusp                       9      0.00%     96.94% # number of callpals executed
 system.cpu.kern.callpal_whami                       2      0.00%     96.94% # number of callpals executed
-system.cpu.kern.callpal_rti                      5221      2.69%     99.63% # number of callpals executed
+system.cpu.kern.callpal_rti                      5219      2.69%     99.63% # number of callpals executed
 system.cpu.kern.callpal_callsys                   531      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     213133                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     213061                       # number of hwrei instructions executed
 system.cpu.kern.inst.ivlb                           0                       # number of ivlb instructions executed
 system.cpu.kern.inst.ivle                           0                       # number of ivle instructions executed
-system.cpu.kern.inst.quiesce                     6280                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      184276                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     75422     40.93%     40.93% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6207                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      184207                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     75390     40.93%     40.93% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_21                      245      0.13%     41.06% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_22                     1861      1.01%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                   106748     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       150212                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      74053     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count_31                   106711     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       150152                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      74023     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_21                       245      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_22                      1861      1.24%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     74053     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                  3651865248                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0                3611061665     98.88%     98.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21                    53683      0.00%     98.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good_31                     74023     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                  3651873412                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0                3611240657     98.89%     98.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                    53683      0.00%     98.89% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks_22                   219598      0.01%     98.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31                 40530302      1.11%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used                     0.815147                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_0                   0.981849                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_ticks_31                 40359474      1.11%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used                     0.815126                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_0                   0.981868                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.693718                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel                 1935                      
-system.cpu.kern.mode_good_user                   1755                      
+system.cpu.kern.ipl_used_31                  0.693677                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1934                      
+system.cpu.kern.mode_good_user                   1754                      
 system.cpu.kern.mode_good_idle                    180                      
-system.cpu.kern.mode_switch_kernel               5988                       # number of protection mode switches
-system.cpu.kern.mode_switch_user                 1755                       # number of protection mode switches
+system.cpu.kern.mode_switch_kernel               5984                       # number of protection mode switches
+system.cpu.kern.mode_switch_user                 1754                       # number of protection mode switches
 system.cpu.kern.mode_switch_idle                 2104                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             0.393013                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.323146                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good             0.393010                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.323195                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_idle        0.085551                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel            58882589      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user               4685612      0.13%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle            3588297045     98.26%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4208                       # number of times the context was actually changed
+system.cpu.kern.mode_ticks_kernel            58926919      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user               4685602      0.13%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle            3588260889     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4204                       # number of times the context was actually changed
 system.cpu.kern.syscall                           329                       # number of syscalls executed
 system.cpu.kern.syscall_fork                        8      2.43%      2.43% # number of syscalls executed
 system.cpu.kern.syscall_read                       30      9.12%     11.55% # number of syscalls executed
@@ -112,10 +112,10 @@ system.cpu.kern.syscall_connect                     2      0.61%     97.57% # nu
 system.cpu.kern.syscall_setgid                      4      1.22%     98.78% # number of syscalls executed
 system.cpu.kern.syscall_getrlimit                   2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_setsid                      2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.021478                       # Percentage of non-idle cycles
+system.cpu.not_idle_fraction                 0.021461                       # Percentage of non-idle cycles
 system.cpu.numCycles                                0                       # number of cpu cycles simulated
-system.cpu.num_insts                         61806956                       # Number of instructions executed
-system.cpu.num_refs                          16806539                       # Number of memory references
+system.cpu.num_insts                         61760478                       # Number of instructions executed
+system.cpu.num_refs                          16793874                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -130,9 +130,9 @@ system.disk2.dma_write_full_pages                   1                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk        no value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi         no value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
index 4741dd710..6204251a5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
@@ -1,4 +1,4 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index 8c667881d..b54e58e73 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:07:02
-M5 started Sun Oct  8 14:08:49 2006
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Oct  8 2006 21:57:24
+M5 started Sun Oct  8 21:59:05 2006
+M5 executing on zed.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
-Exiting @ tick 3651865694 because m5_exit instruction encountered
+Exiting @ tick 3651873858 because m5_exit instruction encountered

From 91c76278b95f74a7a237ba9d89ad2818c2e20a4d Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 8 Oct 2006 19:11:06 -0700
Subject: [PATCH 18/38] Set cpu_id params (required by ll/sc code now).

--HG--
extra : convert_revision : e0f7ccbeccca191a8edb54494d2b4f9369e9914c
---
 configs/example/fs.py | 2 ++
 configs/example/se.py | 1 +
 2 files changed, 3 insertions(+)

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 5edda6e5f..6db26a02a 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -77,6 +77,8 @@ else:
 
 cpu.clock = '2GHz'
 cpu2.clock = '2GHz'
+cpu.cpu_id = 0
+cpu2.cpu_id = 0
 
 if options.benchmark:
     if options.benchmark not in Benchmarks:
diff --git a/configs/example/se.py b/configs/example/se.py
index de8b6c890..d1d19eebc 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -91,6 +91,7 @@ else:
     cpu = AtomicSimpleCPU()
 
 cpu.workload = process
+cpu.cpu_id = 0
 
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),

From d52117d1e3b833727ce115c0d6fafeabd826bd90 Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Sun, 8 Oct 2006 23:16:40 -0400
Subject: [PATCH 19/38] add in serialization of AtomicSimpleCPU _status.  This
 is needed because right now unserializing breaks an assert since CPU status
 is not saved. Kev says that this will break uniform serialization across CPUs
 since each type of CPU has its own "status" enum set.  So, the repercussions
 are that if you serialize in this CPU, you must first unserialize in this CPU
 before switching to something else you want.

src/cpu/simple/atomic.cc:
    add in serialization of AtomicSimpleCPU _status.  Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set.  So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.

--HG--
extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
---
 src/cpu/simple/atomic.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 42b0e9783..b0356b2bf 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -161,6 +161,8 @@ AtomicSimpleCPU::serialize(ostream &os)
 {
     SimObject::State so_state = SimObject::getState();
     SERIALIZE_ENUM(so_state);
+    Status _status = status();
+    SERIALIZE_ENUM(_status);
     BaseSimpleCPU::serialize(os);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
@@ -171,6 +173,7 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
     SimObject::State so_state;
     UNSERIALIZE_ENUM(so_state);
+    UNSERIALIZE_ENUM(_status);
     BaseSimpleCPU::unserialize(cp, section);
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 }

From 97c1f6eff75fb1698b04f0f681681cbf80ba58c8 Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Sun, 8 Oct 2006 23:18:19 -0400
Subject: [PATCH 20/38] post checkpoint restoration the bus ranges need to be
 re-initialized for ALL pci devs, not just ide.

src/dev/ide_ctrl.cc:
    this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
    range change needs to be done at here, not in the ide_ctrl file.

--HG--
extra : convert_revision : 60c65c55e965b02d671dba7aa8793e5a81f40348
---
 src/dev/ide_ctrl.cc | 1 -
 src/dev/pcidev.cc   | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
index e8d7f4817..8007fda5e 100644
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -742,7 +742,6 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(bm_enabled);
     UNSERIALIZE_ARRAY(cmd_in_progress,
                       sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
-    pioPort->sendStatusChange(Port::RangeChange);
 }
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index c3b83f448..b16ddb31a 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -302,6 +302,8 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
     UNSERIALIZE_ARRAY(config.data,
                       sizeof(config.data) / sizeof(config.data[0]));
+    pioPort->sendStatusChange(Port::RangeChange);
+
 }
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS

From 67a114fc29662d262a3d7ae867f6ee4c25c0ce8f Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Mon, 9 Oct 2006 00:12:16 -0400
Subject: [PATCH 21/38] add in checkpoint restoration option, you can restore a
 checkpoint by giving a directory, and then giving a checkpoint number, the
 earliest checkpoint is 1, the latest is N.  the default checkpoint directory
 is the cwd.

so you can restore by a command line like this:

m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3

configs/example/fs.py:
    add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.

--HG--
extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
---
 configs/example/fs.py | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 6db26a02a..0dadcbe1b 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -55,6 +55,8 @@ parser.add_option("--etherdump", action="store", type="string", dest="etherdump"
                   "ethernet traffic")
 parser.add_option("--checkpoint_dir", action="store", type="string",
                   help="Place all checkpoints in this absolute directory")
+parser.add_option("-c", "--checkpoint", action="store", type="int",
+                  help="restore from checkpoint <N>")
 
 (options, args) = parser.parse_args()
 
@@ -115,6 +117,31 @@ else:
 
 m5.instantiate(root)
 
+if options.checkpoint:
+    from os.path import isdir
+    from os import listdir, getcwd
+    import re
+    if options.checkpoint_dir:
+        cptdir = options.checkpoint_dir
+    else:
+        cptdir = getcwd()
+
+    if not isdir(cptdir):
+        m5.panic("checkpoint dir %s does not exist!" % cptdir)
+
+    dirs = listdir(cptdir)
+    expr = re.compile('cpt.([0-9]*)')
+    cpts = []
+    for dir in dirs:
+        match = expr.match(dir)
+        if match:
+            cpts.append(match.group(1))
+
+    if options.checkpoint > len(cpts):
+        m5.panic('Checkpoint %d not found' % options.checkpoint)
+
+    m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[options.checkpoint - 1]]))
+
 if options.maxtick:
     maxtick = options.maxtick
 elif options.maxtime:

From 6c7ab02682aba37c173962ec907b97483625d18b Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 00:26:10 -0400
Subject: [PATCH 22/38] Update the Memtester, commit a config file/test for it.

src/cpu/SConscript:
    Add memtester to the compilation environment.
    Someone who knows this better should make the MemTest a cpu model parameter.

    For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
    Update memtest python description

--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
---
 src/cpu/SConscript               |   1 +
 src/cpu/memtest/memtest.cc       | 328 +++++++++++++++++++------------
 src/cpu/memtest/memtest.hh       | 102 ++++++----
 src/python/m5/objects/MemTest.py |  10 +-
 tests/configs/memtest.py         |  88 +++++++++
 tests/quick/50.memtest/test.py   |  28 +++
 6 files changed, 392 insertions(+), 165 deletions(-)
 create mode 100644 tests/configs/memtest.py
 create mode 100644 tests/quick/50.memtest/test.py

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 2bb9a2399..5771a7904 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -158,6 +158,7 @@ if 'O3CPU' in env['CPU_MODELS']:
         o3/scoreboard.cc
         o3/store_set.cc
         ''')
+    sources += Split('memtest/memtest.cc')
     if env['USE_CHECKER']:
         sources += Split('o3/checker_builder.cc')
     else:
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 7ea9eaefc..186b6ba50 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -38,39 +38,80 @@
 
 #include "base/misc.hh"
 #include "base/statistics.hh"
-#include "cpu/simple_thread.hh"
+//#include "cpu/simple_thread.hh"
 #include "cpu/memtest/memtest.hh"
-#include "mem/cache/base_cache.hh"
+//#include "mem/cache/base_cache.hh"
+//#include "mem/physical.hh"
 #include "sim/builder.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "mem/port.hh"
+#include "mem/mem_object.hh"
 
 using namespace std;
-using namespace TheISA;
 
 int TESTER_ALLOCATOR=0;
 
+bool
+MemTest::CpuPort::recvTiming(Packet *pkt)
+{
+    memtest->completeRequest(pkt);
+    return true;
+}
+
+Tick
+MemTest::CpuPort::recvAtomic(Packet *pkt)
+{
+    panic("MemTest doesn't expect recvAtomic callback!");
+    return curTick;
+}
+
+void
+MemTest::CpuPort::recvFunctional(Packet *pkt)
+{
+    memtest->completeRequest(pkt);
+}
+
+void
+MemTest::CpuPort::recvStatusChange(Status status)
+{
+    if (status == RangeChange)
+        return;
+
+    panic("MemTest doesn't expect recvStatusChange callback!");
+}
+
+void
+MemTest::CpuPort::recvRetry()
+{
+    memtest->doRetry();
+}
+
 MemTest::MemTest(const string &name,
-                 MemInterface *_cache_interface,
-                 FunctionalMemory *main_mem,
-                 FunctionalMemory *check_mem,
+//		 MemInterface *_cache_interface,
+//		 PhysicalMemory *main_mem,
+//		 PhysicalMemory *check_mem,
                  unsigned _memorySize,
                  unsigned _percentReads,
-                 unsigned _percentCopies,
+//		 unsigned _percentCopies,
                  unsigned _percentUncacheable,
                  unsigned _progressInterval,
                  unsigned _percentSourceUnaligned,
                  unsigned _percentDestUnaligned,
                  Addr _traceAddr,
                  Counter _max_loads)
-    : SimObject(name),
+    : MemObject(name),
       tickEvent(this),
-      cacheInterface(_cache_interface),
-      mainMem(main_mem),
-      checkMem(check_mem),
+      cachePort("test", this),
+      funcPort("functional", this),
+      retryPkt(NULL),
+//      mainMem(main_mem),
+//      checkMem(check_mem),
       size(_memorySize),
       percentReads(_percentReads),
-      percentCopies(_percentCopies),
+//      percentCopies(_percentCopies),
       percentUncacheable(_percentUncacheable),
       progressInterval(_progressInterval),
       nextProgressMessage(_progressInterval),
@@ -81,43 +122,52 @@ MemTest::MemTest(const string &name,
     vector<string> cmd;
     cmd.push_back("/bin/ls");
     vector<string> null_vec;
-    thread = new SimpleThread(NULL, 0, mainMem, 0);
-
-    blockSize = cacheInterface->getBlockSize();
-    blockAddrMask = blockSize - 1;
-    traceBlockAddr = blockAddr(_traceAddr);
-
-    //setup data storage with interesting values
-    uint8_t *data1 = new uint8_t[size];
-    uint8_t *data2 = new uint8_t[size];
-    uint8_t *data3 = new uint8_t[size];
-    memset(data1, 1, size);
-    memset(data2, 2, size);
-    memset(data3, 3, size);
+    //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
     curTick = 0;
 
+    // Needs to be masked off once we know the block size.
+    traceBlockAddr = _traceAddr;
     baseAddr1 = 0x100000;
     baseAddr2 = 0x400000;
     uncacheAddr = 0x800000;
 
-    // set up intial memory contents here
-    mainMem->prot_write(baseAddr1, data1, size);
-    checkMem->prot_write(baseAddr1, data1, size);
-    mainMem->prot_write(baseAddr2, data2, size);
-    checkMem->prot_write(baseAddr2, data2, size);
-    mainMem->prot_write(uncacheAddr, data3, size);
-    checkMem->prot_write(uncacheAddr, data3, size);
-
-    delete [] data1;
-    delete [] data2;
-    delete [] data3;
-
     // set up counters
     noResponseCycles = 0;
     numReads = 0;
     tickEvent.schedule(0);
 
     id = TESTER_ALLOCATOR++;
+
+    accessRetry = false;
+}
+
+Port *
+MemTest::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "functional")
+        return &funcPort;
+    else if (if_name == "test")
+        return &cachePort;
+    else
+        panic("No Such Port\n");
+}
+
+void
+MemTest::init()
+{
+    // By the time init() is called, the ports should be hooked up.
+    blockSize = cachePort.peerBlockSize();
+    blockAddrMask = blockSize - 1;
+    traceBlockAddr = blockAddr(traceBlockAddr);
+
+    // set up intial memory contents here
+
+    cachePort.memsetBlob(baseAddr1, 1, size);
+    funcPort.memsetBlob(baseAddr1, 1, size);
+    cachePort.memsetBlob(baseAddr2, 2, size);
+    funcPort.memsetBlob(baseAddr2, 2, size);
+    cachePort.memsetBlob(uncacheAddr, 3, size);
+    funcPort.memsetBlob(uncacheAddr, 3, size);
 }
 
 static void
@@ -132,23 +182,31 @@ printData(ostream &os, uint8_t *data, int nbytes)
 }
 
 void
-MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
+MemTest::completeRequest(Packet *pkt)
 {
+    MemTestSenderState *state =
+        dynamic_cast<MemTestSenderState *>(pkt->senderState);
+
+    uint8_t *data = state->data;
+    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
+    Request *req = pkt->req;
+
     //Remove the address from the list of outstanding
-    std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->paddr);
+    std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
     assert(removeAddr != outstandingAddrs.end());
     outstandingAddrs.erase(removeAddr);
 
-    switch (req->cmd) {
-      case Read:
-        if (memcmp(req->data, data, req->size) != 0) {
-            cerr << name() << ": on read of 0x" << hex << req->paddr
-                 << " (0x" << hex << blockAddr(req->paddr) << ")"
+    switch (pkt->cmd) {
+      case Packet::ReadResp:
+
+        if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
+            cerr << name() << ": on read of 0x" << hex << req->getPaddr()
+                 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
                  << "@ cycle " << dec << curTick
                  << ", cache returns 0x";
-            printData(cerr, req->data, req->size);
+            printData(cerr, pkt_data, pkt->getSize());
             cerr << ", expected 0x";
-            printData(cerr, data, req->size);
+            printData(cerr, data, pkt->getSize());
             cerr << endl;
             fatal("");
         }
@@ -163,13 +221,13 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
         }
 
         if (numReads >= maxLoads)
-            SimExit(curTick, "Maximum number of loads reached!");
+            exitSimLoop("Maximum number of loads reached!");
         break;
 
-      case Write:
+      case Packet::WriteResp:
         numWritesStat++;
         break;
-
+/*
       case Copy:
         //Also remove dest from outstanding list
         removeAddr = outstandingAddrs.find(req->dest);
@@ -177,36 +235,37 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
         outstandingAddrs.erase(removeAddr);
         numCopiesStat++;
         break;
-
+*/
       default:
         panic("invalid command");
     }
 
-    if (blockAddr(req->paddr) == traceBlockAddr) {
+    if (blockAddr(req->getPaddr()) == traceBlockAddr) {
         cerr << name() << ": completed "
-             << (req->cmd.isWrite() ? "write" : "read")
+             << (pkt->isWrite() ? "write" : "read")
              << " access of "
-             << dec << req->size << " bytes at address 0x"
-             << hex << req->paddr
-             << " (0x" << hex << blockAddr(req->paddr) << ")"
+             << dec << pkt->getSize() << " bytes at address 0x"
+             << hex << req->getPaddr()
+             << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
              << ", value = 0x";
-        printData(cerr, req->data, req->size);
+        printData(cerr, pkt_data, pkt->getSize());
         cerr << " @ cycle " << dec << curTick;
 
         cerr << endl;
     }
 
     noResponseCycles = 0;
+    delete state;
     delete [] data;
+    delete pkt->req;
+    delete pkt;
 }
 
-
 void
 MemTest::regStats()
 {
     using namespace Stats;
 
-
     numReadsStat
         .name(name() + ".num_reads")
         .desc("number of read accesses completed")
@@ -234,7 +293,7 @@ MemTest::tick()
         fatal("");
     }
 
-    if (cacheInterface->isBlocked()) {
+    if (accessRetry) {
         return;
     }
 
@@ -248,30 +307,30 @@ MemTest::tick()
 
     //If we aren't doing copies, use id as offset, and do a false sharing
     //mem tester
-    if (percentCopies == 0) {
-        //We can eliminate the lower bits of the offset, and then use the id
-        //to offset within the blks
-        offset &= ~63; //Not the low order bits
-        offset += id;
-        access_size = 0;
-    }
+    //We can eliminate the lower bits of the offset, and then use the id
+    //to offset within the blks
+    offset &= ~63; //Not the low order bits
+    offset += id;
+    access_size = 0;
 
-    MemReqPtr req = new MemReq();
+    Request *req = new Request();
+    uint32_t flags = 0;
+    Addr paddr;
 
     if (cacheable < percentUncacheable) {
-        req->flags |= UNCACHEABLE;
-        req->paddr = uncacheAddr + offset;
+        flags |= UNCACHEABLE;
+        paddr = uncacheAddr + offset;
     } else {
-        req->paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
+        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
     }
     // bool probe = (random() % 2 == 1) && !req->isUncacheable();
     bool probe = false;
 
-    req->size = 1 << access_size;
-    req->data = new uint8_t[req->size];
-    req->paddr &= ~(req->size - 1);
-    req->time = curTick;
-    req->xc = thread->getProxy();
+    paddr &= ~((1 << access_size) - 1);
+    req->setPhys(paddr, 1 << access_size, flags);
+    req->setThreadContext(id,0);
+
+    uint8_t *result = new uint8_t[8];
 
     if (cmd < percentReads) {
         // read
@@ -279,60 +338,81 @@ MemTest::tick()
         //For now we only allow one outstanding request per addreess per tester
         //This means we assume CPU does write forwarding to reads that alias something
         //in the cpu store buffer.
-        if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
-        else outstandingAddrs.insert(req->paddr);
+        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
+        else outstandingAddrs.insert(paddr);
 
-        req->cmd = Read;
-        uint8_t *result = new uint8_t[8];
-        checkMem->access(Read, req->paddr, result, req->size);
-        if (blockAddr(req->paddr) == traceBlockAddr) {
+        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
+        funcPort.readBlob(req->getPaddr(), result, req->getSize());
+
+        if (blockAddr(paddr) == traceBlockAddr) {
             cerr << name()
                  << ": initiating read "
                  << ((probe) ? "probe of " : "access of ")
-                 << dec << req->size << " bytes from addr 0x"
-                 << hex << req->paddr
-                 << " (0x" << hex << blockAddr(req->paddr) << ")"
+                 << dec << req->getSize() << " bytes from addr 0x"
+                 << hex << paddr
+                 << " (0x" << hex << blockAddr(paddr) << ")"
                  << " at cycle "
                  << dec << curTick << endl;
         }
+
+        Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
+        MemTestSenderState *state = new MemTestSenderState(result);
+        pkt->senderState = state;
+
         if (probe) {
-            cacheInterface->probeAndUpdate(req);
-            completeRequest(req, result);
+            cachePort.sendFunctional(pkt);
+//	    completeRequest(pkt, result);
         } else {
-            req->completionEvent = new MemCompleteEvent(req, result, this);
-            cacheInterface->access(req);
+//	    req->completionEvent = new MemCompleteEvent(req, result, this);
+            if (!cachePort.sendTiming(pkt)) {
+                accessRetry = true;
+                retryPkt = pkt;
+            }
         }
-    } else if (cmd < (100 - percentCopies)){
+    } else {
         // write
 
         //For now we only allow one outstanding request per addreess per tester
         //This means we assume CPU does write forwarding to reads that alias something
         //in the cpu store buffer.
-        if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
-        else outstandingAddrs.insert(req->paddr);
+        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
+        else outstandingAddrs.insert(paddr);
 
-        req->cmd = Write;
-        memcpy(req->data, &data, req->size);
-        checkMem->access(Write, req->paddr, req->data, req->size);
-        if (blockAddr(req->paddr) == traceBlockAddr) {
+/*
+        if (blockAddr(req->getPaddr()) == traceBlockAddr) {
             cerr << name() << ": initiating write "
                  << ((probe)?"probe of ":"access of ")
-                 << dec << req->size << " bytes (value = 0x";
-            printData(cerr, req->data, req->size);
+                 << dec << req->getSize() << " bytes (value = 0x";
+            printData(cerr, data_pkt->getPtr(), req->getSize());
             cerr << ") to addr 0x"
-                 << hex << req->paddr
-                 << " (0x" << hex << blockAddr(req->paddr) << ")"
+                 << hex << req->getPaddr()
+                 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
                  << " at cycle "
                  << dec << curTick << endl;
         }
+*/
+        Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+        uint8_t *pkt_data = new uint8_t[req->getSize()];
+        pkt->dataDynamicArray(pkt_data);
+        memcpy(pkt_data, &data, req->getSize());
+        MemTestSenderState *state = new MemTestSenderState(result);
+        pkt->senderState = state;
+
+        funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
+
         if (probe) {
-            cacheInterface->probeAndUpdate(req);
-            completeRequest(req, NULL);
+            cachePort.sendFunctional(pkt);
+//	    completeRequest(req, NULL);
         } else {
-            req->completionEvent = new MemCompleteEvent(req, NULL, this);
-            cacheInterface->access(req);
+//	    req->completionEvent = new MemCompleteEvent(req, NULL, this);
+            if (!cachePort.sendTiming(pkt)) {
+                accessRetry = true;
+                retryPkt = pkt;
+            }
         }
-    } else {
+    }
+/*    else {
         // copy
         unsigned source_align = random() % 100;
         unsigned dest_align = random() % 100;
@@ -369,38 +449,32 @@ MemTest::tick()
                  << " (0x" << hex << blockAddr(dest) << ")"
                  << " at cycle "
                  << dec << curTick << endl;
-        }
+        }*
         cacheInterface->access(req);
         uint8_t result[blockSize];
         checkMem->access(Read, source, &result, blockSize);
         checkMem->access(Write, dest, &result, blockSize);
     }
+*/
 }
 
-
 void
-MemCompleteEvent::process()
+MemTest::doRetry()
 {
-    tester->completeRequest(req, data);
-    delete this;
+    if (cachePort.sendTiming(retryPkt)) {
+        accessRetry = false;
+        retryPkt = NULL;
+    }
 }
 
-
-const char *
-MemCompleteEvent::description()
-{
-    return "memory access completion";
-}
-
-
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 
-    SimObjectParam<BaseCache *> cache;
-    SimObjectParam<FunctionalMemory *> main_mem;
-    SimObjectParam<FunctionalMemory *> check_mem;
+//    SimObjectParam<BaseCache *> cache;
+//    SimObjectParam<PhysicalMemory *> main_mem;
+//    SimObjectParam<PhysicalMemory *> check_mem;
     Param<unsigned> memory_size;
     Param<unsigned> percent_reads;
-    Param<unsigned> percent_copies;
+//    Param<unsigned> percent_copies;
     Param<unsigned> percent_uncacheable;
     Param<unsigned> progress_interval;
     Param<unsigned> percent_source_unaligned;
@@ -413,12 +487,12 @@ END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 
-    INIT_PARAM(cache, "L1 cache"),
-    INIT_PARAM(main_mem, "hierarchical memory"),
-    INIT_PARAM(check_mem, "check memory"),
+//    INIT_PARAM(cache, "L1 cache"),
+//    INIT_PARAM(main_mem, "hierarchical memory"),
+//    INIT_PARAM(check_mem, "check memory"),
     INIT_PARAM(memory_size, "memory size"),
     INIT_PARAM(percent_reads, "target read percentage"),
-    INIT_PARAM(percent_copies, "target copy percentage"),
+//    INIT_PARAM(percent_copies, "target copy percentage"),
     INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
     INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
     INIT_PARAM(percent_source_unaligned,
@@ -433,8 +507,8 @@ END_INIT_SIM_OBJECT_PARAMS(MemTest)
 
 CREATE_SIM_OBJECT(MemTest)
 {
-    return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
-                       check_mem, memory_size, percent_reads, percent_copies,
+    return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
+                       /*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
                        percent_uncacheable, progress_interval,
                        percent_source_unaligned, percent_dest_unaligned,
                        trace_addr, max_loads);
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 42fb235db..278012eba 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -35,25 +35,27 @@
 #include <set>
 
 #include "base/statistics.hh"
-#include "mem/functional/functional.hh"
-#include "mem/mem_interface.hh"
+//#include "mem/functional/functional.hh"
+//#include "mem/mem_interface.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
+#include "mem/mem_object.hh"
+#include "mem/port.hh"
 
-class ThreadContext;
-class MemTest : public SimObject
+class Packet;
+class MemTest : public MemObject
 {
   public:
 
     MemTest(const std::string &name,
-            MemInterface *_cache_interface,
-            FunctionalMemory *main_mem,
-            FunctionalMemory *check_mem,
+//	    MemInterface *_cache_interface,
+//	    PhysicalMemory *main_mem,
+//	    PhysicalMemory *check_mem,
             unsigned _memorySize,
             unsigned _percentReads,
-            unsigned _percentCopies,
+//	    unsigned _percentCopies,
             unsigned _percentUncacheable,
             unsigned _progressInterval,
             unsigned _percentSourceUnaligned,
@@ -61,6 +63,8 @@ class MemTest : public SimObject
             Addr _traceAddr,
             Counter _max_loads);
 
+    virtual void init();
+
     // register statistics
     virtual void regStats();
 
@@ -69,6 +73,8 @@ class MemTest : public SimObject
     // main simulation loop (one cycle)
     void tick();
 
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
+
   protected:
     class TickEvent : public Event
     {
@@ -82,16 +88,62 @@ class MemTest : public SimObject
     };
 
     TickEvent tickEvent;
+    class CpuPort : public Port
+    {
 
-    MemInterface *cacheInterface;
-    FunctionalMemory *mainMem;
-    FunctionalMemory *checkMem;
-    SimpleThread *thread;
+        MemTest *memtest;
+
+      public:
+
+        CpuPort(const std::string &_name, MemTest *_memtest)
+            : Port(_name), memtest(_memtest)
+        { }
+
+      protected:
+
+        virtual bool recvTiming(Packet *pkt);
+
+        virtual Tick recvAtomic(Packet *pkt);
+
+        virtual void recvFunctional(Packet *pkt);
+
+        virtual void recvStatusChange(Status status);
+
+        virtual void recvRetry();
+
+        virtual void getDeviceAddressRanges(AddrRangeList &resp,
+            AddrRangeList &snoop)
+        { resp.clear(); snoop.clear(); }
+    };
+
+    CpuPort cachePort;
+    CpuPort funcPort;
+
+    class MemTestSenderState : public Packet::SenderState
+    {
+      public:
+        /** Constructor. */
+        MemTestSenderState(uint8_t *_data)
+            : data(_data)
+        { }
+
+        // Hold onto data pointer
+        uint8_t *data;
+    };
+
+//    Request *dataReq;
+    Packet  *retryPkt;
+//    MemInterface *cacheInterface;
+//    PhysicalMemory *mainMem;
+//    PhysicalMemory *checkMem;
+//    SimpleThread *thread;
+
+    bool accessRetry;
 
     unsigned size;		// size of testing memory region
 
     unsigned percentReads;	// target percentage of read accesses
-    unsigned percentCopies;	// target percentage of copy accesses
+//    unsigned percentCopies;	// target percentage of copy accesses
     unsigned percentUncacheable;
 
     int id;
@@ -128,31 +180,13 @@ class MemTest : public SimObject
     Stats::Scalar<> numCopiesStat;
 
     // called by MemCompleteEvent::process()
-    void completeRequest(MemReqPtr &req, uint8_t *data);
+    void completeRequest(Packet *pkt);
+
+    void doRetry();
 
     friend class MemCompleteEvent;
 };
 
-
-class MemCompleteEvent : public Event
-{
-    MemReqPtr req;
-    uint8_t *data;
-    MemTest *tester;
-
-  public:
-
-    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
-        : Event(&mainEventQueue),
-          req(_req), data(_data), tester(_tester)
-    {
-    }
-
-    void process();
-
-    virtual const char *description();
-};
-
 #endif // __CPU_MEMTEST_MEMTEST_HH__
 
 
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
index 97600768f..18aff03f4 100644
--- a/src/python/m5/objects/MemTest.py
+++ b/src/python/m5/objects/MemTest.py
@@ -1,13 +1,12 @@
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+
 class MemTest(SimObject):
     type = 'MemTest'
-    cache = Param.BaseCache("L1 cache")
-    check_mem = Param.FunctionalMemory("check memory")
-    main_mem = Param.FunctionalMemory("hierarchical memory")
     max_loads = Param.Counter("number of loads to execute")
     memory_size = Param.Int(65536, "memory size")
-    percent_copies = Param.Percent(0, "target copy percentage")
     percent_dest_unaligned = Param.Percent(50,
         "percent of copy dest address that are unaligned")
     percent_reads = Param.Percent(65, "target read percentage")
@@ -18,3 +17,6 @@ class MemTest(SimObject):
     progress_interval = Param.Counter(1000000,
         "progress report interval (in accesses)")
     trace_addr = Param.Addr(0, "address to trace")
+
+    test = Port("Port to the memory system to test")
+    functional = Port("Port to the functional memory used for verification")
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
new file mode 100644
index 000000000..cfcefbcb9
--- /dev/null
+++ b/tests/configs/memtest.py
@@ -0,0 +1,88 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = 1
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    protocol = CoherenceProtocol(protocol='moesi')
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = 100
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+nb_cores = 1
+cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, funcmem = PhysicalMemory(),
+                physmem = PhysicalMemory(), membus = Bus())
+
+# l2cache & bus
+system.toL2Bus = Bus()
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.port
+
+# add L1 caches
+for cpu in cpus:
+    cpu.l1c = L1(size = '32kB', assoc = 4)
+    cpu.l1c.cpu_side = cpu.test
+    cpu.l1c.mem_side = system.toL2Bus.port
+    system.funcmem.port = cpu.functional
+
+
+# connect memory to membus
+system.physmem.port = system.membus.port
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( system = system )
+root.system.mem_mode = 'timing'
+#root.trace.flags="InstExec"
+root.trace.flags="Bus"
diff --git a/tests/quick/50.memtest/test.py b/tests/quick/50.memtest/test.py
new file mode 100644
index 000000000..e894b8fb8
--- /dev/null
+++ b/tests/quick/50.memtest/test.py
@@ -0,0 +1,28 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+

From 4f93c43d34f66b164cc67f87e7a75fc500a79fa6 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 00:27:03 -0400
Subject: [PATCH 23/38] Don't block responses even if the cache is blocked.

--HG--
extra : convert_revision : a1558eb55806b2a3e7e63249601df2c143e2235d
---
 src/mem/cache/base_cache.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index d7ccca8c0..6b035bc16 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -71,7 +71,7 @@ BaseCache::CachePort::deviceBlockSize()
 bool
 BaseCache::CachePort::recvTiming(Packet *pkt)
 {
-    if (blocked)
+    if (pkt->isRequest() && blocked)
     {
         DPRINTF(Cache,"Scheduling a retry while blocked\n");
         mustSendRetry = true;

From 0087061681869c9aaab81c3797020b083a83d46a Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 00:27:41 -0400
Subject: [PATCH 24/38] Don't create a response if one isn't needed.

--HG--
extra : convert_revision : 37bd230f527f64eb12779157869aae9dcfdde7fd
---
 src/mem/cache/cache_impl.hh | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 9ce8f515d..ac2d7af8b 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -620,7 +620,9 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort
                 lat = memSidePort->sendAtomic(busPkt);
 
                 //Be sure to flip the response to a request for coherence
-                busPkt->makeAtomicResponse();
+                if (busPkt->needsResponse()) {
+                    busPkt->makeAtomicResponse();
+                }
 
 /*		if (!(busPkt->flags & SATISFIED)) {
                     // blocked at a higher level, just return

From 095d5991f50aaccd2a25792cb7ce44b43a98b29c Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 00:31:24 -0400
Subject: [PATCH 25/38] Put a check in so people know not to create more than 8
 memtesters.

--HG--
extra : convert_revision : 41ab297dc681b2601be1df33aba30c39f49466d8
---
 src/cpu/memtest/memtest.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 186b6ba50..609a07a8e 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -137,6 +137,8 @@ MemTest::MemTest(const string &name,
     tickEvent.schedule(0);
 
     id = TESTER_ALLOCATOR++;
+    if (TESTER_ALLOCATOR > 8)
+        panic("False sharing memtester only allows up to 8 testers");
 
     accessRetry = false;
 }

From bc732b59fd82689490306090974f1f4c06741b0a Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 01:04:37 -0400
Subject: [PATCH 26/38] Have cpus send snoop ranges

--HG--
extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
---
 src/cpu/o3/fetch.hh         |  2 +-
 src/cpu/o3/lsq.hh           |  2 +-
 src/cpu/ozone/front_end.hh  |  2 +-
 src/cpu/ozone/lw_lsq.hh     |  2 +-
 src/cpu/simple/atomic.hh    |  4 ++--
 src/cpu/simple/timing.hh    |  2 +-
 src/mem/cache/base_cache.hh | 16 ++++++++--------
 7 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 1a2ca32a4..280bf0e71 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -96,7 +96,7 @@ class DefaultFetch
         /** Returns the address ranges of this device. */
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
                                             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
 
         /** Timing version of receive.  Handles setting fetch to the
          * proper status to start fetching. */
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 190734dc2..6b12d75b4 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -311,7 +311,7 @@ class LSQ {
         /** Returns the address ranges of this device. */
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
                                             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
 
         /** Timing version of receive.  Handles writing back and
          * completing the load or store that has returned from
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 5ffd3666e..59cf9785c 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -92,7 +92,7 @@ class FrontEnd
         /** Returns the address ranges of this device. */
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
                                             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
 
         /** Timing version of receive.  Handles setting fetch to the
          * proper status to start fetching. */
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 347f4569b..9b93ce74f 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -260,7 +260,7 @@ class OzoneLWLSQ {
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
                                             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1); }
 
         virtual bool recvTiming(PacketPtr pkt);
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index b602af558..52afd76ef 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -104,9 +104,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
-    };
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
 
+    };
     CpuPort icachePort;
     CpuPort dcachePort;
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index b65eebd99..18e13aeb2 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -92,7 +92,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
 
         struct TickEvent : public Event
         {
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 2e92e7730..de8a19cac 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -156,7 +156,7 @@ class BaseCache : public MemObject
         if (status == Port::RangeChange){
             if (!isCpuSide) {
                 cpuSidePort->sendStatusChange(Port::RangeChange);
-                if (topLevelCache && !snoopRangesSent) {
+                if (!snoopRangesSent) {
                     snoopRangesSent = true;
                     memSidePort->sendStatusChange(Port::RangeChange);
                 }
@@ -568,14 +568,14 @@ class BaseCache : public MemObject
         {
             //This is where snoops get updated
             AddrRangeList dummy;
-            if (!topLevelCache)
-            {
+//            if (!topLevelCache)
+//            {
                 cpuSidePort->getPeerAddressRanges(dummy, snoop);
-            }
-            else
-            {
-                snoop.push_back(RangeSize(0,-1));
-            }
+//            }
+//            else
+//            {
+//                snoop.push_back(RangeSize(0,-1));
+//            }
 
             return;
         }

From afce51d10ad1441247b39edb2a61b85d3cd7af04 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 16:37:02 -0400
Subject: [PATCH 27/38] Set size properly on uncache accesses Don't use the
 senderState after you get a succesful sendTiming.  Not guarnteed to be
 correct

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
    Don't use the senderState after you get a succesful sendTiming.  Not guarnteed to be correct

--HG--
extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
---
 src/mem/cache/base_cache.cc           | 16 ++++++++++++----
 src/mem/cache/base_cache.hh           |  5 ++++-
 src/mem/cache/cache.hh                |  2 +-
 src/mem/cache/cache_impl.hh           |  6 +++---
 src/mem/cache/miss/blocking_buffer.cc |  6 +++---
 src/mem/cache/miss/blocking_buffer.hh |  2 +-
 src/mem/cache/miss/miss_queue.cc      | 13 ++++++-------
 src/mem/cache/miss/miss_queue.hh      |  2 +-
 8 files changed, 31 insertions(+), 21 deletions(-)

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 6b035bc16..1a0f63d17 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -109,10 +109,11 @@ BaseCache::CachePort::recvRetry()
     if (!isCpuSide)
     {
         pkt = cache->getPacket();
+        MSHR* mshr = (MSHR*)pkt->senderState;
         bool success = sendTiming(pkt);
         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
-        cache->sendResult(pkt, success);
+        cache->sendResult(pkt, mshr, success);
         if (success && cache->doMasterRequest())
         {
             //Still more to issue, rerequest in 1 cycle
@@ -123,7 +124,9 @@ BaseCache::CachePort::recvRetry()
     }
     else
     {
-        pkt = cache->getCoherencePacket();
+        //pkt = cache->getCoherencePacket();
+        //We save the packet, no reordering on CSHRS
+        pkt = cshrRetry;
         bool success = sendTiming(pkt);
         if (success && cache->doSlaveRequest())
         {
@@ -182,10 +185,11 @@ BaseCache::CacheEvent::process()
         {
             //MSHR
             pkt = cachePort->cache->getPacket();
+            MSHR* mshr = (MSHR*) pkt->senderState;
             bool success = cachePort->sendTiming(pkt);
             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
-            cachePort->cache->sendResult(pkt, success);
+            cachePort->cache->sendResult(pkt, mshr, success);
             if (success && cachePort->cache->doMasterRequest())
             {
                 //Still more to issue, rerequest in 1 cycle
@@ -198,7 +202,11 @@ BaseCache::CacheEvent::process()
             //CSHR
             pkt = cachePort->cache->getCoherencePacket();
             bool success = cachePort->sendTiming(pkt);
-            if (success && cachePort->cache->doSlaveRequest())
+            if (!success) {
+                //Need to send on a retry
+                cachePort->cshrRetry = pkt;
+            }
+            else if (cachePort->cache->doSlaveRequest())
             {
                 //Still more to issue, rerequest in 1 cycle
                 pkt = NULL;
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index de8a19cac..c45f3b71b 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -72,6 +72,7 @@ enum RequestCause{
     Request_PF
 };
 
+class MSHR;
 /**
  * A basic cache interface. Implements some common functions for speed.
  */
@@ -112,6 +113,8 @@ class BaseCache : public MemObject
         bool isCpuSide;
 
         std::list<Packet *> drainList;
+
+        Packet *cshrRetry;
     };
 
     struct CacheEvent : public Event
@@ -177,7 +180,7 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
-    virtual void sendResult(Packet* &pkt, bool success)
+    virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
     {
 
         fatal("No implementation");
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4b8870c95..923bf8255 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -175,7 +175,7 @@ class Cache : public BaseCache
      * @param pkt The request.
      * @param success True if the request was sent successfully.
      */
-    virtual void sendResult(Packet * &pkt, bool success);
+    virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index ac2d7af8b..32f561d71 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -287,10 +287,10 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
 
 template<class TagStore, class Buffering, class Coherence>
 void
-Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
+Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 {
     if (success) {
-        missQueue->markInService(pkt);
+              missQueue->markInService(pkt, mshr);
           //Temp Hack for UPGRADES
           if (pkt->cmd == Packet::UpgradeReq) {
               handleResponse(pkt);
@@ -444,7 +444,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 
                     if (pkt->isInvalidate()) {
                         //This must be an upgrade or other cache will take ownership
-                        missQueue->markInService(mshr->pkt);
+                        missQueue->markInService(mshr->pkt, mshr);
                     }
                     return;
                 }
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index 7a6ea9133..f7aacff89 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -123,12 +123,12 @@ BlockingBuffer::restoreOrigCmd(Packet * &pkt)
 }
 
 void
-BlockingBuffer::markInService(Packet * &pkt)
+BlockingBuffer::markInService(Packet * &pkt, MSHR* mshr)
 {
     if (!pkt->isCacheFill() && pkt->isWrite()) {
         // Forwarding a write/ writeback, don't need to change
         // the command
-        assert((MSHR*)pkt->senderState == &wb);
+        assert(mshr == &wb);
         cache->clearMasterRequest(Request_WB);
         if (!pkt->needsResponse()) {
             assert(wb.getNumTargets() == 0);
@@ -138,7 +138,7 @@ BlockingBuffer::markInService(Packet * &pkt)
             wb.inService = true;
         }
     } else {
-        assert((MSHR*)pkt->senderState == &miss);
+        assert(mshr == &miss);
         cache->clearMasterRequest(Request_MSHR);
         if (!pkt->needsResponse()) {
             assert(miss.getNumTargets() == 0);
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 641d5a798..f7069696c 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -152,7 +152,7 @@ public:
      * are successfully sent.
      * @param pkt The request that was sent on the bus.
      */
-    void markInService(Packet * &pkt);
+    void markInService(Packet * &pkt, MSHR* mshr);
 
     /**
      * Frees the resources of the pktuest and unblock the cache.
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 273b6587f..bdb7a39c8 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -372,7 +372,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
 MSHR*
 MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
 {
-    MSHR* mshr = wb.allocate(pkt,blkSize);
+    MSHR* mshr = wb.allocate(pkt,size);
     mshr->order = order++;
 
 //REMOVING COMPRESSION FOR NOW
@@ -446,7 +446,7 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
         /**
          * @todo Add write merging here.
          */
-        mshr = allocateWrite(pkt, blkSize, time);
+        mshr = allocateWrite(pkt, pkt->getSize(), time);
         return;
     }
 
@@ -526,9 +526,8 @@ MissQueue::restoreOrigCmd(Packet * &pkt)
 }
 
 void
-MissQueue::markInService(Packet * &pkt)
+MissQueue::markInService(Packet * &pkt, MSHR* mshr)
 {
-    assert(pkt->senderState != 0);
     bool unblock = false;
     BlockedCause cause = NUM_BLOCKED_CAUSES;
 
@@ -540,7 +539,7 @@ MissQueue::markInService(Packet * &pkt)
         // Forwarding a write/ writeback, don't need to change
         // the command
         unblock = wb.isFull();
-        wb.markInService((MSHR*)pkt->senderState);
+        wb.markInService(mshr);
         if (!wb.havePending()){
             cache->clearMasterRequest(Request_WB);
         }
@@ -551,11 +550,11 @@ MissQueue::markInService(Packet * &pkt)
         }
     } else {
         unblock = mq.isFull();
-        mq.markInService((MSHR*)pkt->senderState);
+        mq.markInService(mshr);
         if (!mq.havePending()){
             cache->clearMasterRequest(Request_MSHR);
         }
-        if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
+        if (mshr->originalCmd == Packet::HardPFReq) {
             DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n",
                     cache->name());
             //Also clear pending if need be
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index 505d1f90c..179638d2b 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -256,7 +256,7 @@ class MissQueue
      * are successfully sent.
      * @param pkt The request that was sent on the bus.
      */
-    void markInService(Packet * &pkt);
+    void markInService(Packet * &pkt, MSHR* mshr);
 
     /**
      * Collect statistics and free resources of a satisfied pktuest.

From 45732376f6f781cf3671b830321e96478a01dd3d Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 16:47:55 -0400
Subject: [PATCH 28/38] Add more DPRINTF's fix a supply condition.

src/mem/cache/cache_impl.hh:
    Add more usefull DPRINTF's
    REmove the PC to get rid of asserts

--HG--
extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
---
 src/mem/cache/cache_impl.hh | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index ac2d7af8b..b6556f252 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -236,9 +236,9 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
         missQueue->doWriteback(writebacks.front());
         writebacks.pop_front();
     }
-    DPRINTF(Cache, "%s %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
+    DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
-            pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
+            pkt->getAddr() & ~((Addr)blkSize - 1));
     if (blk) {
         // Hit
         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
@@ -314,9 +314,11 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
             blk = tags->findBlock(pkt);
             CacheBlk::State old_state = (blk) ? blk->status : 0;
             PacketList writebacks;
+            CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
+            DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
+                    pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
-                                   coherence->getNewState(pkt,old_state),
-                                   writebacks, pkt);
+                                   new_state, writebacks, pkt);
             while (!writebacks.empty()) {
                     missQueue->doWriteback(writebacks.front());
                     writebacks.pop_front();
@@ -387,6 +389,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
                     //If the outstanding request was an invalidate (upgrade,readex,..)
                     //Then we need to ACK the request until we get the data
                     //Also NACK if the outstanding request is not a cachefill (writeback)
+                    assert(!(pkt->flags & SATISFIED));
                     pkt->flags |= SATISFIED;
                     pkt->flags |= NACKED_LINE;
                     assert("Don't detect these on the other side yet\n");
@@ -426,6 +429,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
                     if (pkt->isRead()) {
                         //Only Upgrades don't get here
                         //Supply the data
+                        assert(!(pkt->flags & SATISFIED));
                         pkt->flags |= SATISFIED;
 
                         //If we are in an exclusive protocol, make it ask again
@@ -454,10 +458,16 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
     CacheBlk::State new_state;
     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
     if (satisfy) {
+        DPRINTF(Cache, "Cache snooped a %c request and now supplying data,"
+                "new state is %i\n",
+                pkt->cmdString(), new_state);
+
         tags->handleSnoop(blk, new_state, pkt);
         respondToSnoop(pkt, curTick + hitLatency);
         return;
     }
+    if (blk) DPRINTF(Cache, "Cache snooped a %c request, new state is %i\n",
+                     pkt->cmdString(), new_state);
     tags->handleSnoop(blk, new_state);
 }
 
@@ -675,9 +685,15 @@ Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
         CacheBlk::State new_state = 0;
         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
         if (satisfy) {
+            DPRINTF(Cache, "Cache snooped a %c request and now supplying data,"
+                    "new state is %i\n",
+                    pkt->cmdString(), new_state);
+
             tags->handleSnoop(blk, new_state, pkt);
             return hitLatency;
         }
+        if (blk) DPRINTF(Cache, "Cache snooped a %c request, new state is %i\n",
+                     pkt->cmdString(), new_state);
         tags->handleSnoop(blk, new_state);
         return 0;
 }

From b9fb4d4870dd45c552fd4cd5e531e9626754f19f Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 17:13:50 -0400
Subject: [PATCH 29/38] Make memtest work with 8 memtesters

src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
---
 src/mem/physical.cc                     |  2 +-
 src/python/m5/objects/PhysicalMemory.py |  1 +
 tests/configs/memtest.py                | 10 ++++++++--
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 070693442..96d78bd99 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -231,7 +231,7 @@ PhysicalMemory::getPort(const std::string &if_name, int idx)
         port = new MemoryPort(name() + "-port", this);
         return port;
     } else if (if_name == "functional") {
-        /* special port for functional writes at startup. */
+        /* special port for functional writes at startup. And for memtester */
         return new MemoryPort(name() + "-funcport", this);
     } else {
         panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index dd3ffd651..4e097543d 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -5,6 +5,7 @@ from MemObject import *
 class PhysicalMemory(MemObject):
     type = 'PhysicalMemory'
     port = Port("the access port")
+    functional = Port("Functional Access Port")
     range = Param.AddrRange(AddrRange('128MB'), "Device Address")
     file = Param.String('', "memory mapped file")
     latency = Param.Latency(Parent.clock, "latency of an access")
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index cfcefbcb9..c5cd0246d 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -51,7 +51,8 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
-nb_cores = 1
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
 cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
 
 # system simulated
@@ -66,12 +67,17 @@ system.l2c.cpu_side = system.toL2Bus.port
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
 
+which_port = 0
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.port
-    system.funcmem.port = cpu.functional
+    if  which_port == 0:
+         system.funcmem.port = cpu.functional
+         which_port = 1
+    else:
+         system.funcmem.functional = cpu.functional
 
 
 # connect memory to membus

From fd27c229b6bae09098864361dd6e51065fbaec3c Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 17:18:34 -0400
Subject: [PATCH 30/38] Fix a bitwise operation that was accidentally a logical
 operation.

--HG--
extra : convert_revision : 30f64bcb6bea47fd8cd6d77b0df17eff04dbbad0
---
 src/mem/cache/cache_impl.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 8d028e97f..7764b97c1 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -73,7 +73,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
             handleResponse(pkt);
         else {
             //Check if we should do the snoop
-            if (pkt->flags && SNOOP_COMMIT)
+            if (pkt->flags & SNOOP_COMMIT)
                 snoop(pkt);
         }
     }

From 094c6de663c1203d3bc64f8d973daba1690e2d33 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 17:25:43 -0400
Subject: [PATCH 31/38] Multiprogrammed workload, need to generate ref's for it
 yet.  But Nate wanted the config. Not sure on the naming convention for
 tests.

--HG--
extra : convert_revision : 052c2fc95dc7e2bbd78d4a177600d7ec2a530a4c
---
 tests/quick/00.hello.mp/test.py | 44 +++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 tests/quick/00.hello.mp/test.py

diff --git a/tests/quick/00.hello.mp/test.py b/tests/quick/00.hello.mp/test.py
new file mode 100644
index 000000000..91fbfb7ed
--- /dev/null
+++ b/tests/quick/00.hello.mp/test.py
@@ -0,0 +1,44 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+# workload
+benchmarks = [
+    "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
+    "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
+    "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
+    "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
+    ]
+
+for i, cpu in zip(range(len(cpus)), root.system.cpu):
+    p            = LiveProcess()
+    p.executable = benchmarks[i*2]
+    p.cmd        = benchmarks[(i*2)+1]
+    root.system.cpu[i].workload = p
+    root.system.cpu[i].max_insts_all_threads = 10000000
+#root.system.cpu.workload = LiveProcess(cmd = 'hello',
+ #                                      executable = binpath('hello'))

From c4dba7a8ed496c2e534b6caa8754678d642124c7 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 17:30:54 -0400
Subject: [PATCH 32/38] Fix a typo in the printf

--HG--
extra : convert_revision : bfa8ffae0a9bef25ceca168ff376ba816abf23f3
---
 src/mem/cache/cache_impl.hh | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 7764b97c1..bde7ac04b 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -458,7 +458,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
     CacheBlk::State new_state;
     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
     if (satisfy) {
-        DPRINTF(Cache, "Cache snooped a %c request and now supplying data,"
+        DPRINTF(Cache, "Cache snooped a %s request and now supplying data,"
                 "new state is %i\n",
                 pkt->cmdString(), new_state);
 
@@ -466,7 +466,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
         respondToSnoop(pkt, curTick + hitLatency);
         return;
     }
-    if (blk) DPRINTF(Cache, "Cache snooped a %c request, new state is %i\n",
+    if (blk) DPRINTF(Cache, "Cache snooped a %s request, new state is %i\n",
                      pkt->cmdString(), new_state);
     tags->handleSnoop(blk, new_state);
 }
@@ -685,14 +685,14 @@ Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
         CacheBlk::State new_state = 0;
         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
         if (satisfy) {
-            DPRINTF(Cache, "Cache snooped a %c request and now supplying data,"
+            DPRINTF(Cache, "Cache snooped a %s request and now supplying data,"
                     "new state is %i\n",
                     pkt->cmdString(), new_state);
 
             tags->handleSnoop(blk, new_state, pkt);
             return hitLatency;
         }
-        if (blk) DPRINTF(Cache, "Cache snooped a %c request, new state is %i\n",
+        if (blk) DPRINTF(Cache, "Cache snooped a %s request, new state is %i\n",
                      pkt->cmdString(), new_state);
         tags->handleSnoop(blk, new_state);
         return 0;

From 727dea78c4b603a63d6c8bee10d317cb2905ffd4 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 17:31:58 -0400
Subject: [PATCH 33/38] Update configs for cpu_id

tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
    Update config for cpu_id

--HG--
extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
---
 tests/configs/o3-timing-mp.py     | 4 ++--
 tests/configs/simple-atomic-mp.py | 4 ++--
 tests/configs/simple-timing-mp.py | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 881c23156..55af8be0d 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -54,7 +54,7 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ]
+cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
@@ -86,5 +86,5 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
-root.trace.flags="Bus Cache"
+#root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index cc1a36dda..eaa6ec66e 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -52,10 +52,10 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
+system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
 Bus())
 
 # l2cache & bus
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 9fc5f3874..8f9ab0dde 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -52,7 +52,7 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =

From 187dcb18bfd87db63ad914d2ba04f0bd2dc0637d Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 9 Oct 2006 18:12:45 -0400
Subject: [PATCH 34/38] Potentially functional partially timed bandwidth
 limitted bus model.

src/mem/bus.cc:
    Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
    Put snooping back into recvTiming and not in it's own function.

--HG--
extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
---
 src/mem/bus.cc | 61 +++++++++++++++++++++++++++-----------------------
 src/mem/bus.hh |  9 --------
 2 files changed, 33 insertions(+), 37 deletions(-)

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index df85ee0d9..c288e34c0 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -118,25 +118,26 @@ Bus::recvTiming(Packet *pkt)
     DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
             pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
 
+    Port *pktPort = interfaces[pkt->getSrc()];
+
     short dest = pkt->getDest();
     if (dest == Packet::Broadcast) {
-        if ( timingSnoopPhase1(pkt) )
-        if (timingSnoop(pkt))
-        {
-            timingSnoopPhase2(pkt);
+        if (timingSnoop(pkt)) {
             pkt->flags |= SNOOP_COMMIT;
             bool success = timingSnoop(pkt);
             assert(success);
             if (pkt->flags & SATISFIED) {
                 //Cache-Cache transfer occuring
+                if (retryingPort) {
+                    retryList.pop_front();
+                    retryingPort = NULL;
+                }
                 return true;
             }
             port = findPort(pkt->getAddr(), pkt->getSrc());
-        }
-        else
-        {
+        } else {
             //Snoop didn't succeed
-            retryList.push_back(interfaces[pkt->getSrc()]);
+            addToRetryList(pktPort);
             return false;
         }
     } else {
@@ -144,6 +145,30 @@ Bus::recvTiming(Packet *pkt)
         assert(dest != pkt->getSrc()); // catch infinite loops
         port = interfaces[dest];
     }
+
+    // The packet will be sent. Figure out how long it occupies the bus.
+    int numCycles = 0;
+    // Requests need one cycle to send an address
+    if (pkt->isRequest())
+        numCycles++;
+    else if (pkt->isResponse() || pkt->hasData()) {
+        // If a packet has data, it needs ceil(size/width) cycles to send it
+        // We're using the "adding instead of dividing" trick again here
+        if (pkt->hasData()) {
+            int dataSize = pkt->getSize();
+            for (int transmitted = 0; transmitted < dataSize;
+                    transmitted += width) {
+                numCycles++;
+            }
+        } else {
+            // If the packet didn't have data, it must have been a response.
+            // Those use the bus for one cycle to send their data.
+            numCycles++;
+        }
+    }
+
+    occupyBus(numCycles);
+
     if (port->sendTiming(pkt))  {
         // Packet was successfully sent. Return true.
         // Also take care of retries
@@ -175,26 +200,6 @@ Bus::recvRetry(int id)
     }
 }
 
-Port *
-Bus::findDestPort(PacketPtr pkt, int id)
-{
-    Port * port = NULL;
-    short dest = pkt->getDest();
-
-    if (dest == Packet::Broadcast) {
-        if (timingSnoopPhase1(pkt)) {
-            timingSnoopPhase2(pkt);
-            port = findPort(pkt->getAddr(), pkt->getSrc());
-        }
-        //else, port stays NULL
-    } else {
-        assert(dest >= 0 && dest < interfaces.size());
-        assert(dest != pkt->getSrc()); // catch infinite loops
-        port = interfaces[dest];
-    }
-    return port;
-}
-
 Port *
 Bus::findPort(Addr addr, int id)
 {
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index f8a006911..c9b0a76a0 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -97,15 +97,6 @@ class Bus : public MemObject
      */
     Port *findPort(Addr addr, int id);
 
-    /** Finds the port a packet should be sent to. If the bus is blocked, no port
-     * is returned.
-     * @param pkt Packet to find a destination port for.
-     * @param id Id of the port this packet was received from
-     *           (to prevent loops)
-     */
-
-    Port *findDestPort(PacketPtr pkt, int id);
-
     /** Find all ports with a matching snoop range, except src port.  Keep in mind
      * that the ranges shouldn't overlap or you will get a double snoop to the same
      * interface.and the cache will assert out.

From 13ac9a419dcf2e1e0335bc65b20837e538a9beee Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 18:52:20 -0400
Subject: [PATCH 35/38] One step closet to having NACK's work.

src/cpu/memtest/memtest.cc:
    Fix functional return path
src/cpu/memtest/memtest.hh:
    Add snoop ranges in
src/mem/cache/base_cache.cc:
    Properly signal NACKED
src/mem/cache/cache_impl.hh:
    Catch nacked packet and panic for now

--HG--
extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
---
 src/cpu/memtest/memtest.cc  |  7 ++++---
 src/cpu/memtest/memtest.hh  |  2 +-
 src/mem/cache/base_cache.cc |  5 ++++-
 src/mem/cache/cache_impl.hh | 10 ++++++++--
 4 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 609a07a8e..127cad414 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -71,7 +71,8 @@ MemTest::CpuPort::recvAtomic(Packet *pkt)
 void
 MemTest::CpuPort::recvFunctional(Packet *pkt)
 {
-    memtest->completeRequest(pkt);
+    //Do nothing if we see one come through
+    return;
 }
 
 void
@@ -325,7 +326,7 @@ MemTest::tick()
     } else {
         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
     }
-    // bool probe = (random() % 2 == 1) && !req->isUncacheable();
+    //bool probe = (random() % 2 == 1) && !req->isUncacheable();
     bool probe = false;
 
     paddr &= ~((1 << access_size) - 1);
@@ -364,7 +365,7 @@ MemTest::tick()
 
         if (probe) {
             cachePort.sendFunctional(pkt);
-//	    completeRequest(pkt, result);
+            completeRequest(pkt);
         } else {
 //	    req->completionEvent = new MemCompleteEvent(req, result, this);
             if (!cachePort.sendTiming(pkt)) {
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 278012eba..87ecc6de3 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -113,7 +113,7 @@ class MemTest : public MemObject
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
             AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
     };
 
     CpuPort cachePort;
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 1a0f63d17..8e2f4d233 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -217,7 +217,10 @@ BaseCache::CacheEvent::process()
     }
     //Response
     //Know the packet to send
-    pkt->result = Packet::Success;
+    if (pkt->flags & NACKED_LINE)
+        pkt->result = Packet::Nacked;
+    else
+        pkt->result = Packet::Success;
     pkt->makeTimingResponse();
     if (!cachePort->drainList.empty()) {
         //Already blocked waiting for bus, just append
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index bde7ac04b..af12b9255 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -306,6 +306,13 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 {
     BlkType *blk = NULL;
     if (pkt->senderState) {
+        if (pkt->result == Packet::Nacked) {
+            pkt->reinitFromRequest();
+            panic("Unimplemented NACK of packet\n");
+        }
+        if (pkt->result == Packet::BadAddress) {
+            //Make the response a Bad address and send it
+        }
 //	MemDebug::cacheResponse(pkt);
         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
                 pkt->getAddr() & (((ULL(1))<<48)-1));
@@ -392,7 +399,6 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
                     assert(!(pkt->flags & SATISFIED));
                     pkt->flags |= SATISFIED;
                     pkt->flags |= NACKED_LINE;
-                    assert("Don't detect these on the other side yet\n");
                     respondToSnoop(pkt, curTick + hitLatency);
                     return;
                 }
@@ -406,7 +412,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
                     //@todo Make it so that a read to a pending read can't be exclusive now.
 
                     //Set the address so find match works
-                    assert("Don't have invalidates yet\n");
+                    panic("Don't have invalidates yet\n");
                     invalidatePkt->addrOverride(pkt->getAddr());
 
                     //Append the invalidate on

From e03b9c9939d7782198c023b23ed33cde131f48c5 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 19:15:24 -0400
Subject: [PATCH 36/38] Fix how upgrades work. Remove some dead code.

src/mem/cache/cache_impl.hh:
    Upgrades don't need a response.
    Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
    Upgrades don't require a response

--HG--
extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
---
 src/mem/cache/cache_impl.hh                   | 8 +++-----
 src/mem/cache/coherence/coherence_protocol.cc | 2 +-
 src/mem/packet.hh                             | 3 +--
 3 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index af12b9255..c3c1c0881 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -63,9 +63,8 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
         if (pkt->isWrite() && (pkt->req->isLocked())) {
             pkt->req->setScResult(1);
         }
-        if (!(pkt->flags & SATISFIED)) {
-            access(pkt);
-        }
+        access(pkt);
+
     }
     else
     {
@@ -204,9 +203,8 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
                     pkt->getAddr() & (((ULL(1))<<48)-1),
                     pkt->getAddr() & ~((Addr)blkSize - 1));
 
-            //@todo Should this return latency have the hit latency in it?
-//	    respond(pkt,curTick+lat);
             pkt->flags |= SATISFIED;
+            //Invalidates/Upgrades need no response if they get the bus
 //            return MA_HIT; //@todo, return values
             return true;
         }
diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc
index bcf3ce9c5..e28dda3dc 100644
--- a/src/mem/cache/coherence/coherence_protocol.cc
+++ b/src/mem/cache/coherence/coherence_protocol.cc
@@ -271,7 +271,7 @@ CoherenceProtocol::CoherenceProtocol(const string &name,
     }
 
     Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq;
-    Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeResp : Packet::ReadExResp;
+    Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp;
 
 //@todo add in hardware prefetch to this list
     if (protocol == "msi") {
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index be9bf5f57..9d37fe157 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -194,8 +194,7 @@ class Packet
         HardPFResp      = IsRead  | IsResponse | IsHWPrefetch | NeedsResponse,
         InvalidateReq   = IsInvalidate | IsRequest,
         WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
-        UpgradeReq      = IsInvalidate | IsRequest | NeedsResponse,
-        UpgradeResp     = IsInvalidate | IsResponse | NeedsResponse,
+        UpgradeReq      = IsInvalidate | IsRequest
         ReadExReq       = IsRead | IsInvalidate | IsRequest | NeedsResponse,
         ReadExResp      = IsRead | IsInvalidate | IsResponse | NeedsResponse
     };

From 9356bcda7b50ae8916eee2dfbad84ed3ea873c1e Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 19:20:28 -0400
Subject: [PATCH 37/38] Fix a typo preventing compilation

--HG--
extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
---
 src/mem/packet.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 9d37fe157..56c4caffe 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -194,7 +194,7 @@ class Packet
         HardPFResp      = IsRead  | IsResponse | IsHWPrefetch | NeedsResponse,
         InvalidateReq   = IsInvalidate | IsRequest,
         WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
-        UpgradeReq      = IsInvalidate | IsRequest
+        UpgradeReq      = IsInvalidate | IsRequest,
         ReadExReq       = IsRead | IsInvalidate | IsRequest | NeedsResponse,
         ReadExResp      = IsRead | IsInvalidate | IsResponse | NeedsResponse
     };

From 5448517da4cd13e3c8438850f04367d9614d686b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 9 Oct 2006 19:55:49 -0400
Subject: [PATCH 38/38] updated reference output

--HG--
extra : convert_revision : daf11630290c7a84d63bf37cafa44210861c4bf2
---
 .../ref/mips/linux/simple-atomic/config.ini   |  2 ++
 .../ref/mips/linux/simple-atomic/config.out   |  2 ++
 .../ref/mips/linux/simple-atomic/m5stats.txt  |  8 ++---
 .../ref/mips/linux/simple-atomic/stdout       |  6 ++--
 .../ref/mips/linux/simple-timing/config.ini   |  4 +++
 .../ref/mips/linux/simple-timing/config.out   |  4 +++
 .../ref/mips/linux/simple-timing/m5stats.txt  | 36 +++++++++----------
 .../ref/mips/linux/simple-timing/stdout       |  6 ++--
 8 files changed, 39 insertions(+), 29 deletions(-)

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index fa3ccdf1c..59cadaa12 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -91,6 +91,8 @@ uid=100
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
index 6ab9c098e..064f467da 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out
@@ -19,6 +19,8 @@ mem_mode=atomic
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 
 [system.cpu.workload]
 type=LiveProcess
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index f358a8e52..3b2a2730b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   2733                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147536                       # Number of bytes of host memory used
-host_seconds                                     2.07                       # Real time elapsed on the host
-host_tick_rate                                   2732                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  52255                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 148024                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                                  52038                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 4056e38ec..600b178b3 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:15:37
-M5 started Sun Oct  8 14:15:41 2006
+M5 compiled Oct  9 2006 19:28:25
+M5 started Mon Oct  9 19:28:56 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
 Exiting @ tick 5656 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index af7a1c895..8e1bb0388 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -194,6 +194,8 @@ mem_side=system.membus.port[1]
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
@@ -214,6 +216,8 @@ uid=100
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
index ead34bf39..d683d2355 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out
@@ -19,6 +19,8 @@ mem_mode=atomic
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 
 [system.cpu.dcache]
 type=BaseCache
@@ -95,6 +97,8 @@ function_trace_start=0
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
 
 [system.cpu.icache]
 type=BaseCache
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index ef08c56cd..ab86ba509 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 116093                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 158992                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                 174583                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  68704                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 166092                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
+host_tick_rate                                 103651                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
@@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses               2054                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency            3                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1922                       # number of overall hits
 system.cpu.dcache.overall_miss_latency            396                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.064265                       # miss rate for overall accesses
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses               5658                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency     2.993399                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency     1.993399                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5355                       # number of overall hits
 system.cpu.icache.overall_miss_latency            907                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.053552                       # miss rate for overall accesses
@@ -153,41 +153,39 @@ system.cpu.l2cache.ReadReq_misses                 433                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency          433                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995402                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            433                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReq_accesses                1                       # number of WriteReq accesses(hits+misses)
-system.cpu.l2cache.WriteReq_hits                    1                       # number of WriteReq hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.006928                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.004619                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                436                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                435                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency            866                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.993119                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.995402                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  433                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency          433                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.993119                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.995402                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             433                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               436                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses               435                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency            2                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     3                       # number of overall hits
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                     2                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency           866                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.993119                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.995402                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 433                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency          433                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.993119                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.995402                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            433                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -204,7 +202,7 @@ system.cpu.l2cache.replacements                     0                       # nu
 system.cpu.l2cache.sampled_refs                   433                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.l2cache.tagsinuse               226.406294                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 97b24e1ad..4acd2a2e5 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:15:37
-M5 started Sun Oct  8 14:15:43 2006
+M5 compiled Oct  9 2006 19:28:25
+M5 started Mon Oct  9 19:28:56 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
+command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Exiting @ tick 8579 because target called exit()