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ruby: moesi cmp token: cosmetic changes

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Updates copyright years, removes space at the end of lines, shortens
variable names.
This commit is contained in:
Nilay Vaish 2013-05-21 11:32:24 -05:00
parent e7ce518168
commit bd3d1955da
5 changed files with 85 additions and 97 deletions
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6
configs/ruby/MOESI_CMP_token.py
View file

@ -100,8 +100,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l1_cntrl = L1Cache_Controller(version = i, l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache, L1Icache = l1i_cache,
L1DcacheMemory = l1d_cache, L1Dcache = l1d_cache,
l2_select_num_bits = l2_bits, l2_select_num_bits = l2_bits,
N_tokens = n_tokens, N_tokens = n_tokens,
retry_threshold = \ retry_threshold = \
@ -147,7 +147,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_cntrl = L2Cache_Controller(version = i, l2_cntrl = L2Cache_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
L2cacheMemory = l2_cache, L2cache = l2_cache,
N_tokens = n_tokens, N_tokens = n_tokens,
ruby_system = ruby_system) ruby_system = ruby_system)

48
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -33,8 +33,8 @@
machine(L1Cache, "Token protocol") machine(L1Cache, "Token protocol")
: Sequencer * sequencer, : Sequencer * sequencer,
CacheMemory * L1IcacheMemory, CacheMemory * L1Icache,
CacheMemory * L1DcacheMemory, CacheMemory * L1Dcache,
int l2_select_num_bits, int l2_select_num_bits,
int N_tokens, int N_tokens,
@ -224,12 +224,12 @@ machine(L1Cache, "Token protocol")
} }
Entry getCacheEntry(Address addr), return_by_pointer="yes" { Entry getCacheEntry(Address addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr)); Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
if(is_valid(L1Dcache_entry)) { if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry; return L1Dcache_entry;
} }
Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr)); Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
return L1Icache_entry; return L1Icache_entry;
} }
@ -238,12 +238,12 @@ machine(L1Cache, "Token protocol")
} }
Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" { Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr)); Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
return L1Dcache_entry; return L1Dcache_entry;
} }
Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" { Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr)); Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
return L1Icache_entry; return L1Icache_entry;
} }
@ -271,7 +271,7 @@ machine(L1Cache, "Token protocol")
} }
void setState(TBE tbe, Entry cache_entry, Address addr, State state) { void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false); assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
if (is_valid(tbe)) { if (is_valid(tbe)) {
assert(state != State:I); assert(state != State:I);
@ -678,16 +678,16 @@ machine(L1Cache, "Token protocol")
L1Dcache_entry, tbe); L1Dcache_entry, tbe);
} }
if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { if (L1Icache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1 // L1 does't have the line, but we have space for it in the L1
trigger(mandatory_request_type_to_event(in_msg.Type), trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Icache_entry, tbe); in_msg.LineAddress, L1Icache_entry, tbe);
} else { } else {
// No room in the L1, so we need to make room // No room in the L1, so we need to make room
trigger(Event:L1_Replacement, trigger(Event:L1_Replacement,
L1IcacheMemory.cacheProbe(in_msg.LineAddress), L1Icache.cacheProbe(in_msg.LineAddress),
getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)), getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]); L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
} }
} }
} else { } else {
@ -709,16 +709,16 @@ machine(L1Cache, "Token protocol")
L1Icache_entry, tbe); L1Icache_entry, tbe);
} }
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1 // L1 does't have the line, but we have space for it in the L1
trigger(mandatory_request_type_to_event(in_msg.Type), trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Dcache_entry, tbe); in_msg.LineAddress, L1Dcache_entry, tbe);
} else { } else {
// No room in the L1, so we need to make room // No room in the L1, so we need to make room
trigger(Event:L1_Replacement, trigger(Event:L1_Replacement,
L1DcacheMemory.cacheProbe(in_msg.LineAddress), L1Dcache.cacheProbe(in_msg.LineAddress),
getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)), getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]); L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
} }
} }
} }
@ -1506,10 +1506,10 @@ machine(L1Cache, "Token protocol")
action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") { action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
assert(getTokens(cache_entry) == 0); assert(getTokens(cache_entry) == 0);
if (L1DcacheMemory.isTagPresent(address)) { if (L1Dcache.isTagPresent(address)) {
L1DcacheMemory.deallocate(address); L1Dcache.deallocate(address);
} else { } else {
L1IcacheMemory.deallocate(address); L1Icache.deallocate(address);
} }
unset_cache_entry(); unset_cache_entry();
} }
@ -1517,14 +1517,14 @@ machine(L1Cache, "Token protocol")
action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") { action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
if (is_valid(cache_entry)) { if (is_valid(cache_entry)) {
} else { } else {
set_cache_entry(L1DcacheMemory.allocate(address, new Entry)); set_cache_entry(L1Dcache.allocate(address, new Entry));
} }
} }
action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") { action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
if (is_valid(cache_entry)) { if (is_valid(cache_entry)) {
} else { } else {
set_cache_entry(L1IcacheMemory.allocate(address, new Entry)); set_cache_entry(L1Icache.allocate(address, new Entry));
} }
} }
@ -1536,19 +1536,19 @@ machine(L1Cache, "Token protocol")
} }
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") { action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
++L1IcacheMemory.demand_misses; ++L1Icache.demand_misses;
} }
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") { action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
++L1IcacheMemory.demand_hits; ++L1Icache.demand_hits;
} }
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") { action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
++L1DcacheMemory.demand_misses; ++L1Dcache.demand_misses;
} }
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") { action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
++L1DcacheMemory.demand_hits; ++L1Dcache.demand_hits;
} }
action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") { action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {

34
src/mem/protocol/MOESI_CMP_token-L2cache.sm
View file

@ -1,6 +1,5 @@
/* /*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -27,13 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
/*
* $Id$
*
*/
machine(L2Cache, "Token protocol") machine(L2Cache, "Token protocol")
: CacheMemory * L2cacheMemory, : CacheMemory * L2cache,
int N_tokens, int N_tokens,
Cycles l2_request_latency = 5, Cycles l2_request_latency = 5,
Cycles l2_response_latency = 5, Cycles l2_response_latency = 5,
@ -152,7 +146,7 @@ machine(L2Cache, "Token protocol")
void unset_cache_entry(); void unset_cache_entry();
Entry getCacheEntry(Address address), return_by_pointer="yes" { Entry getCacheEntry(Address address), return_by_pointer="yes" {
Entry cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address)); Entry cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
return cache_entry; return cache_entry;
} }
@ -411,7 +405,7 @@ machine(L2Cache, "Token protocol")
in_msg.Type == CoherenceResponseType:WB_OWNED || in_msg.Type == CoherenceResponseType:WB_OWNED ||
in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) { in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
if (L2cacheMemory.cacheAvail(in_msg.Address) || is_valid(cache_entry)) { if (L2cache.cacheAvail(in_msg.Address) || is_valid(cache_entry)) {
// either room is available or the block is already present // either room is available or the block is already present
@ -429,8 +423,8 @@ machine(L2Cache, "Token protocol")
} }
else { else {
trigger(Event:L2_Replacement, trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.Address), L2cache.cacheProbe(in_msg.Address),
getCacheEntry(L2cacheMemory.cacheProbe(in_msg.Address))); getCacheEntry(L2cache.cacheProbe(in_msg.Address)));
} }
} else if (in_msg.Type == CoherenceResponseType:INV) { } else if (in_msg.Type == CoherenceResponseType:INV) {
trigger(Event:L1_INV, in_msg.Address, cache_entry); trigger(Event:L1_INV, in_msg.Address, cache_entry);
@ -447,7 +441,7 @@ machine(L2Cache, "Token protocol")
} else if (in_msg.Type == CoherenceResponseType:WB_TOKENS || } else if (in_msg.Type == CoherenceResponseType:WB_TOKENS ||
in_msg.Type == CoherenceResponseType:WB_OWNED || in_msg.Type == CoherenceResponseType:WB_OWNED ||
in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) { in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
if (L2cacheMemory.cacheAvail(in_msg.Address) || is_valid(cache_entry)) { if (L2cache.cacheAvail(in_msg.Address) || is_valid(cache_entry)) {
// either room is available or the block is already present // either room is available or the block is already present
@ -466,8 +460,8 @@ machine(L2Cache, "Token protocol")
} }
else { else {
trigger(Event:L2_Replacement, trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.Address), L2cache.cacheProbe(in_msg.Address),
getCacheEntry(L2cacheMemory.cacheProbe(in_msg.Address))); getCacheEntry(L2cache.cacheProbe(in_msg.Address)));
} }
} else if (in_msg.Type == CoherenceResponseType:INV) { } else if (in_msg.Type == CoherenceResponseType:INV) {
trigger(Event:L1_INV, in_msg.Address, cache_entry); trigger(Event:L1_INV, in_msg.Address, cache_entry);
@ -905,7 +899,7 @@ machine(L2Cache, "Token protocol")
peek(L1requestNetwork_in, RequestMsg) { peek(L1requestNetwork_in, RequestMsg) {
if ((machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache) && if ((machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache) &&
(is_valid(cache_entry))) { (is_valid(cache_entry))) {
L2cacheMemory.setMRU(address); L2cache.setMRU(address);
} }
} }
} }
@ -957,20 +951,20 @@ machine(L2Cache, "Token protocol")
} }
action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") { action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
set_cache_entry(L2cacheMemory.allocate(address, new Entry)); set_cache_entry(L2cache.allocate(address, new Entry));
} }
action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") { action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
L2cacheMemory.deallocate(address); L2cache.deallocate(address);
unset_cache_entry(); unset_cache_entry();
} }
action(uu_profileMiss, "\um", desc="Profile the demand miss") { action(uu_profileMiss, "\um", desc="Profile the demand miss") {
++L2cacheMemory.demand_misses; ++L2cache.demand_misses;
} }
action(uu_profileHit, "\uh", desc="Profile the demand hit") { action(uu_profileHit, "\uh", desc="Profile the demand hit") {
++L2cacheMemory.demand_hits; ++L2cache.demand_hits;
} }
action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") { action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {

8
src/mem/protocol/MOESI_CMP_token-dir.sm
View file

@ -1,6 +1,5 @@
/* /*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -27,11 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
/*
* $Id$
*/
machine(Directory, "Token protocol") machine(Directory, "Token protocol")
: DirectoryMemory * directory, : DirectoryMemory * directory,
MemoryControl * memBuffer, MemoryControl * memBuffer,