SE/FS: Turn on the page table class in FS.
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6ba3ebae43
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7 changed files with 64 additions and 74 deletions
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@ -34,34 +34,14 @@
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#ifndef __ARCH_MIPS_PAGETABLE_H__
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#define __ARCH_MIPS_PAGETABLE_H__
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/utility.hh"
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#include "arch/mips/vtophys.hh"
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#include "config/full_system.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "sim/serialize.hh"
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namespace MipsISA {
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struct VAddr
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{
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static const int ImplBits = 43;
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static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
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static const Addr UnImplMask = ~ImplMask;
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VAddr(Addr a) : addr(a) {}
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Addr addr;
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operator Addr() const { return addr; }
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const VAddr &operator=(Addr a) { addr = a; return *this; }
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Addr vpn() const { return (addr & ImplMask) >> PageShift; }
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Addr page() const { return addr & Page_Mask; }
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Addr offset() const { return addr & PageOffset; }
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Addr level3() const
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{ return MipsISA::PteAddr(addr >> PageShift); }
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Addr level2() const
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{ return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
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Addr level1() const
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{ return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
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};
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// ITB/DTB page table entry
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@ -98,6 +78,33 @@ struct PTE
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
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struct TlbEntry
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{
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Addr _pageStart;
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TlbEntry() {}
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TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
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Addr pageStart()
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{
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return _pageStart;
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}
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void
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updateVaddr(Addr new_vaddr) {}
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void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(_pageStart);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(_pageStart);
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}
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};
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};
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#endif // __ARCH_MIPS_PAGETABLE_H__
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@ -55,33 +55,6 @@ class ThreadContext;
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simply create an ITLB and DTLB that will point to the real TLB */
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namespace MipsISA {
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// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
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struct TlbEntry
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{
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Addr _pageStart;
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TlbEntry() {}
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TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
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Addr pageStart()
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{
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return _pageStart;
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}
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void
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updateVaddr(Addr new_vaddr) {}
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void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(_pageStart);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(_pageStart);
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}
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};
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class TLB : public BaseTLB
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{
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protected:
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@ -46,12 +46,10 @@ Source('vport.cc')
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if env['TARGET_ISA'] != 'no':
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SimObject('PhysicalMemory.py')
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Source('dram.cc')
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Source('page_table.cc')
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Source('physical.cc')
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Source('translating_port.cc')
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if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
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Source('page_table.cc')
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DebugFlag('Bus')
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DebugFlag('BusAddrRanges')
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DebugFlag('BusBridge')
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@ -52,9 +52,15 @@
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using namespace std;
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using namespace TheISA;
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PageTable::PageTable(Process *_process, Addr _pageSize)
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: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
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process(_process)
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PageTable::PageTable(
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#if !FULL_SYSTEM
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Process *_process,
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#endif
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Addr _pageSize)
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: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize)))
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#if !FULL_SYSTEM
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, process(_process)
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#endif
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{
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assert(isPowerOf2(pageSize));
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pTableCache[0].vaddr = 0;
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@ -83,9 +89,11 @@ PageTable::allocate(Addr vaddr, int64_t size)
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vaddr);
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}
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#if !FULL_SYSTEM
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pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
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process->system->new_page());
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updateCache(vaddr, pTable[vaddr]);
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#endif
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}
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}
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@ -196,7 +204,9 @@ PageTable::serialize(std::ostream &os)
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PTableItr iter = pTable.begin();
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PTableItr end = pTable.end();
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while (iter != end) {
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#if !FULL_SYSTEM
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os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
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#endif
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paramOut(os, "vaddr", iter->first);
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iter->second.serialize(os);
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@ -212,17 +222,20 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion)
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{
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int i = 0, count;
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paramIn(cp, section, "ptable.size", count);
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Addr vaddr;
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TheISA::TlbEntry *entry;
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pTable.clear();
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while (i < count) {
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#if !FULL_SYSTEM
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TheISA::TlbEntry *entry;
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Addr vaddr;
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paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
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entry = new TheISA::TlbEntry();
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entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
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pTable[vaddr] = *entry;
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++i;
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#endif
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}
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}
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@ -42,11 +42,14 @@
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#include "arch/tlb.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "mem/request.hh"
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#include "sim/serialize.hh"
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#if !FULL_SYSTEM
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class Process;
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#endif
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/**
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* Page Table Declaration.
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@ -68,11 +71,17 @@ class PageTable
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const Addr pageSize;
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const Addr offsetMask;
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#if !FULL_SYSTEM
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Process *process;
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#endif
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public:
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PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
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PageTable(
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#if !FULL_SYSTEM
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Process *_process,
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#endif
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Addr _pageSize = TheISA::VMPageSize);
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~PageTable();
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@ -35,9 +35,7 @@
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#include "base/chunk_generator.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#if !FULL_SYSTEM
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#include "mem/page_table.hh"
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#endif
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#include "mem/port.hh"
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#include "mem/translating_port.hh"
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#if !FULL_SYSTEM
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@ -67,14 +65,12 @@ TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size)
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int prevSize = 0;
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for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
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#if !FULL_SYSTEM
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Addr paddr;
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if (!pTable->translate(gen.addr(),paddr))
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return false;
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Port::readBlob(paddr, p + prevSize, gen.size());
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#endif
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prevSize += gen.size();
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}
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@ -95,7 +91,6 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
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int prevSize = 0;
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for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
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#if !FULL_SYSTEM
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Addr paddr;
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if (!pTable->translate(gen.addr(), paddr)) {
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@ -104,9 +99,11 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
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VMPageSize);
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} else if (allocating == NextPage) {
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// check if we've accessed the next page on the stack
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#if !FULL_SYSTEM
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if (!process->fixupStackFault(gen.addr()))
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panic("Page table fault when accessing virtual address %#x "
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"during functional write\n", gen.addr());
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#endif
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} else {
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return false;
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}
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@ -114,7 +111,6 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
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}
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Port::writeBlob(paddr, p + prevSize, gen.size());
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#endif
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prevSize += gen.size();
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}
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@ -133,7 +129,6 @@ bool
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TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
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{
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for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
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#if !FULL_SYSTEM
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Addr paddr;
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if (!pTable->translate(gen.addr(), paddr)) {
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@ -146,7 +141,6 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
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}
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}
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Port::memsetBlob(paddr, val, gen.size());
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#endif
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}
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return true;
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@ -163,7 +157,6 @@ TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size)
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bool
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TranslatingPort::tryWriteString(Addr addr, const char *str)
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{
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#if !FULL_SYSTEM
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uint8_t c;
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Addr vaddr = addr;
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@ -178,7 +171,6 @@ TranslatingPort::tryWriteString(Addr addr, const char *str)
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Port::writeBlob(paddr, &c, 1);
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} while (c);
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#endif
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return true;
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}
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@ -192,7 +184,6 @@ TranslatingPort::writeString(Addr addr, const char *str)
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bool
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TranslatingPort::tryReadString(std::string &str, Addr addr)
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{
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#if !FULL_SYSTEM
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uint8_t c;
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Addr vaddr = addr;
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str += c;
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} while (c);
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#endif
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return true;
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}
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@ -35,8 +35,8 @@
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#include "config/full_system.hh"
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#include "mem/port.hh"
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#if !FULL_SYSTEM
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class PageTable;
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#if !FULL_SYSTEM
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class Process;
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#endif
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@ -50,8 +50,8 @@ class TranslatingPort : public FunctionalPort
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};
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private:
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#if !FULL_SYSTEM
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PageTable *pTable;
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#if !FULL_SYSTEM
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Process *process;
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#endif
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AllocType allocating;
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