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X86: Put the result used for flags in an intermediate variable.

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Using the destination register directly causes the ISA parser to treat it as a
source even if none of the original bits are used.
This commit is contained in:
Gabe Black 2011-02-13 17:45:12 -08:00
parent b046f3feb6
commit bce2be525d
3 changed files with 22 additions and 20 deletions
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3
src/arch/x86/insts/microregop.cc
View file

@ -50,9 +50,6 @@ namespace X86ISA
bool subtract) const bool subtract) const
{ {
DPRINTF(X86, "flagMask = %#x\n", flagMask); DPRINTF(X86, "flagMask = %#x\n", flagMask);
if (_destRegIdx[0] & IntFoldBit) {
_dest >>= 8;
}
uint64_t flags = oldFlags & ~flagMask; uint64_t flags = oldFlags & ~flagMask;
if(flagMask & (ECFBit | CFBit)) if(flagMask & (ECFBit | CFBit))
{ {

1
src/arch/x86/isa/includes.isa
View file

@ -114,6 +114,7 @@ output exec {{
#include "arch/x86/regs/misc.hh" #include "arch/x86/regs/misc.hh"
#include "arch/x86/tlb.hh" #include "arch/x86/tlb.hh"
#include "base/bigint.hh" #include "base/bigint.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh" #include "base/condcodes.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"

38
src/arch/x86/isa/microops/regop.isa
View file

@ -51,6 +51,8 @@ def template MicroRegOpExecute {{
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
IntReg result M5_VAR_USED;
if(%(cond_check)s) if(%(cond_check)s)
{ {
%(code)s; %(code)s;
@ -79,6 +81,8 @@ def template MicroRegOpImmExecute {{
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
IntReg result M5_VAR_USED;
if(%(cond_check)s) if(%(cond_check)s)
{ {
%(code)s; %(code)s;
@ -434,7 +438,7 @@ let {{
flag_code = ''' flag_code = '''
//Don't have genFlags handle the OF or CF bits //Don't have genFlags handle the OF or CF bits
uint64_t mask = CFBit | ECFBit | OFBit; uint64_t mask = CFBit | ECFBit | OFBit;
ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
//If a logic microop wants to set these, it wants to set them to 0. //If a logic microop wants to set these, it wants to set them to 0.
ccFlagBits &= ~(CFBit & ext); ccFlagBits &= ~(CFBit & ext);
ccFlagBits &= ~(ECFBit & ext); ccFlagBits &= ~(ECFBit & ext);
@ -444,12 +448,12 @@ let {{
class FlagRegOp(RegOp): class FlagRegOp(RegOp):
abstract = True abstract = True
flag_code = \ flag_code = \
"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
class SubRegOp(RegOp): class SubRegOp(RegOp):
abstract = True abstract = True
flag_code = \ flag_code = \
"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
class CondRegOp(RegOp): class CondRegOp(RegOp):
abstract = True abstract = True
@ -471,44 +475,44 @@ let {{
src1, src2, flags, dataSize) src1, src2, flags, dataSize)
class Add(FlagRegOp): class Add(FlagRegOp):
code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
big_code = 'DestReg = (psrc1 + op2) & mask(dataSize * 8);' big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
class Or(LogicRegOp): class Or(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
big_code = 'DestReg = (psrc1 | op2) & mask(dataSize * 8);' big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
class Adc(FlagRegOp): class Adc(FlagRegOp):
code = ''' code = '''
CCFlagBits flags = ccFlagBits; CCFlagBits flags = ccFlagBits;
DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
''' '''
big_code = ''' big_code = '''
CCFlagBits flags = ccFlagBits; CCFlagBits flags = ccFlagBits;
DestReg = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
''' '''
class Sbb(SubRegOp): class Sbb(SubRegOp):
code = ''' code = '''
CCFlagBits flags = ccFlagBits; CCFlagBits flags = ccFlagBits;
DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
''' '''
big_code = ''' big_code = '''
CCFlagBits flags = ccFlagBits; CCFlagBits flags = ccFlagBits;
DestReg = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
''' '''
class And(LogicRegOp): class And(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
big_code = 'DestReg = (psrc1 & op2) & mask(dataSize * 8)' big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
class Sub(SubRegOp): class Sub(SubRegOp):
code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
big_code = 'DestReg = (psrc1 - op2) & mask(dataSize * 8)' big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
class Xor(LogicRegOp): class Xor(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
big_code = 'DestReg = (psrc1 ^ op2) & mask(dataSize * 8)' big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
class Mul1s(WrRegOp): class Mul1s(WrRegOp):
code = ''' code = '''