Merge zizzer:/bk/m5
into zizzer.eecs.umich.edu:/.automount/zed/z/hsul/work/m5/pact05 --HG-- extra : convert_revision : e7ff23f6ac4e434d8b3117275df12fec03964a55
This commit is contained in:
commit
bc6baa4049
19 changed files with 163 additions and 91 deletions
|
@ -393,13 +393,11 @@ template <class T>
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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if (status() == DcacheMissStall) {
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if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
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Fault fault = xc->read(memReq,data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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return fault;
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}
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@ -428,21 +426,11 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
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// do functional access
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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}
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} else if(fault == No_Fault) {
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// do functional access
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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}
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if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
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@ -498,11 +486,6 @@ template <class T>
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Fault
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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@ -605,6 +588,8 @@ SimpleCPU::processCacheCompletion()
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case DcacheMissStall:
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if (memReq->cmd.isRead()) {
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curStaticInst->execute(this,traceData);
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if (traceData)
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traceData->finalize();
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}
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dcacheStallCycles += curTick - lastDcacheStall;
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_status = Running;
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@ -613,6 +598,8 @@ SimpleCPU::processCacheCompletion()
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case DcacheMissSwitch:
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if (memReq->cmd.isRead()) {
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curStaticInst->execute(this,traceData);
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if (traceData)
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traceData->finalize();
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}
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_status = SwitchedOut;
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sampler->signalSwitched();
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@ -785,8 +772,12 @@ SimpleCPU::tick()
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comLoadEventQueue[0]->serviceEvents(numLoad);
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}
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if (traceData)
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// If we have a dcache miss, then we can't finialize the instruction
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// trace yet because we want to populate it with the data later
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if (traceData &&
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!(status() == DcacheMissStall && memReq->cmd.isRead())) {
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traceData->finalize();
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}
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traceFunctions(xc->regs.pc);
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@ -139,25 +139,90 @@ class Singleton(type):
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#####################################################################
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class Proxy(object):
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def __init__(self, path = ()):
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def __init__(self, path):
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self._object = None
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self._path = path
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if path == 'any':
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self._path = None
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else:
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# path is a list of (attr,index) tuples
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self._path = [(path,None)]
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self._index = None
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self._multiplier = None
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def __getattr__(self, attr):
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return Proxy(self._path + (attr, ))
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if attr == '__bases__':
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return super(Proxy, self).__getattr__(self, attr)
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self._path.append((attr,None))
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return self
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def __setattr__(self, attr, value):
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if not attr.startswith('_'):
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raise AttributeError, 'cannot set attribute %s' % attr
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super(Proxy, self).__setattr__(attr, value)
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def _convert(self):
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obj = self._object
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for attr in self._path:
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obj = obj.__getattribute__(attr)
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return obj
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# support indexing on proxies (e.g., parent.cpu[0])
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def __getitem__(self, key):
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if not isinstance(key, int):
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raise TypeError, "Proxy object requires integer index"
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if self._path == None:
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raise IndexError, "Index applied to 'any' proxy"
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# replace index portion of last path element with new index
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self._path[-1] = (self._path[-1][0], key)
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return self
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Super = Proxy()
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# support multiplying proxies by constants
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def __mul__(self, other):
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if not isinstance(other, int):
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raise TypeError, "Proxy multiplier must be integer"
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if self._multiplier == None:
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self._multiplier = other
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else:
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# support chained multipliers
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self._multiplier *= other
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return self
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def _mulcheck(self, result):
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if self._multiplier == None:
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return result
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if not isinstance(result, int):
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raise TypeError, "Proxy with multiplier resolves to " \
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"non-integer value"
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return result * self._multiplier
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def unproxy(self, base, ptype):
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obj = base
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done = False
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while not done:
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if obj is None:
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raise AttributeError, \
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'Parent of %s type %s not found at path %s' \
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% (base.name, ptype, self._path)
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found, done = obj.find(ptype, self._path)
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if isinstance(found, Proxy):
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done = False
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obj = obj.parent
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return self._mulcheck(found)
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def getindex(obj, index):
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if index == None:
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return obj
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try:
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obj = obj[index]
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except TypeError:
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if index != 0:
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raise
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# if index is 0 and item is not subscriptable, just
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# use item itself (so cpu[0] works on uniprocessors)
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return obj
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getindex = staticmethod(getindex)
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class ProxyFactory(object):
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def __getattr__(self, attr):
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return Proxy(attr)
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# global object for handling parent.foo proxies
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parent = ProxyFactory()
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def isSubClass(value, cls):
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try:
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@ -643,50 +708,40 @@ class Node(object):
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if issubclass(child.realtype, realtype):
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if obj is not None:
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raise AttributeError, \
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'Super matched more than one: %s %s' % \
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'parent.any matched more than one: %s %s' % \
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(obj.path, child.path)
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obj = child
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return obj, obj is not None
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try:
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obj = self
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for node in path[:-1]:
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for (node,index) in path[:-1]:
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if obj.child_names.has_key(node):
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obj = obj.child_names[node]
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else:
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obj = obj.top_child_names[node]
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obj = Proxy.getindex(obj, index)
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last = path[-1]
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(last,index) = path[-1]
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if obj.child_names.has_key(last):
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value = obj.child_names[last]
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if issubclass(value.realtype, realtype):
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return value, True
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return Proxy.getindex(value, index), True
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elif obj.top_child_names.has_key(last):
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value = obj.top_child_names[last]
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return Proxy.getindex(value, index), True
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elif obj.param_names.has_key(last):
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value = obj.param_names[last]
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realtype._convert(value.value)
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return value.value, True
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return Proxy.getindex(value.value, index), True
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except KeyError:
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pass
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return None, False
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def unproxy(self, ptype, value):
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if not isinstance(value, Proxy):
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return value
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if value is None:
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raise AttributeError, 'Error while fixing up %s' % self.path
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obj = self
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done = False
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while not done:
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if obj is None:
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raise AttributeError, \
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'Parent of %s type %s not found at path %s' \
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% (self.name, ptype, value._path)
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found, done = obj.find(ptype, value._path)
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if isinstance(found, Proxy):
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done = False
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obj = obj.parent
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return found
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def unproxy(self, param, ptype):
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if not isinstance(param, Proxy):
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return param
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return param.unproxy(self, ptype)
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def fixup(self):
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self.all[self.path] = self
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@ -697,9 +752,9 @@ class Node(object):
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try:
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if isinstance(pval, (list, tuple)):
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param.value = [ self.unproxy(ptype, pv) for pv in pval ]
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param.value = [ self.unproxy(pv, ptype) for pv in pval ]
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else:
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param.value = self.unproxy(ptype, pval)
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param.value = self.unproxy(pval, ptype)
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except:
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print 'Error while fixing up %s:%s' % (self.path, param.name)
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raise
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@ -1337,7 +1392,7 @@ class SimObject(ConfigNode, ParamType):
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# 'from config import *' is invoked. Try to keep this reasonably
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# short to avoid polluting other namespaces.
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__all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam',
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'Super', 'Enum',
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'parent', 'Enum',
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'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
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'Int32', 'UInt32', 'Int64', 'UInt64',
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'Counter', 'Addr', 'Tick', 'Percent',
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@ -2,8 +2,8 @@ from Device import PioDevice
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simobj AlphaConsole(PioDevice):
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type = 'AlphaConsole'
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cpu = Param.BaseCPU(Super, "Processor")
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cpu = Param.BaseCPU(parent.any, "Processor")
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disk = Param.SimpleDisk("Simple Disk")
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num_cpus = Param.Int(1, "Number of CPUs")
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sim_console = Param.SimConsole(Super, "The Simulator Console")
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system = Param.BaseSystem(Super, "system object")
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sim_console = Param.SimConsole(parent.any, "The Simulator Console")
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system = Param.BaseSystem(parent.any, "system object")
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@ -8,7 +8,7 @@ simobj BaseCPU(SimObject):
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dtb = Param.AlphaDTB("Data TLB")
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itb = Param.AlphaITB("Instruction TLB")
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mem = Param.FunctionalMemory("memory")
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system = Param.BaseSystem(Super, "system object")
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system = Param.BaseSystem(parent.any, "system object")
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else:
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workload = VectorParam.Process("processes to run")
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@ -1,8 +1,8 @@
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simobj BaseSystem(SimObject):
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type = 'BaseSystem'
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abstract = True
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memctrl = Param.MemoryController(Super, "memory controller")
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physmem = Param.PhysicalMemory(Super, "phsyical memory")
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memctrl = Param.MemoryController(parent.any, "memory controller")
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physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
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kernel = Param.String("file that contains the kernel code")
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console = Param.String("file that contains the console code")
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pal = Param.String("file that contains palcode")
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|
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@ -14,7 +14,7 @@ simobj FooPioDevice(FunctionalMemory):
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type = 'PioDevice'
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abstract = True
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addr = Param.Addr("Device Address")
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mmu = Param.MemoryController(Super, "Memory Controller")
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mmu = Param.MemoryController(parent.any, "Memory Controller")
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io_bus = Param.Bus(NULL, "The IO Bus to attach to")
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pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
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@ -25,7 +25,7 @@ simobj FooDmaDevice(FooPioDevice):
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simobj PioDevice(FooPioDevice):
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type = 'PioDevice'
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abstract = True
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platform = Param.Platform(Super, "Platform")
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platform = Param.Platform(parent.any, "Platform")
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simobj DmaDevice(PioDevice):
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type = 'DmaDevice'
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|
|
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@ -49,8 +49,8 @@ simobj EtherDev(DmaDevice):
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intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(Super, "Physical Memory")
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tlaser = Param.Turbolaser(Super, "Turbolaser")
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physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
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tlaser = Param.Turbolaser(parent.any, "Turbolaser")
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simobj NSGigE(PciDevice):
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type = 'NSGigE'
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|
@ -73,7 +73,7 @@ simobj NSGigE(PciDevice):
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intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(Super, "Physical Memory")
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physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
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|
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simobj EtherDevInt(EtherInt):
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type = 'EtherDevInt'
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|
|
|
@ -7,7 +7,7 @@ simobj IdeDisk(SimObject):
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delay = Param.Tick(1, "Fixed disk delay in microseconds")
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driveID = Param.IdeID('master', "Drive ID")
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image = Param.DiskImage("Disk image")
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physmem = Param.PhysicalMemory(Super, "Physical memory")
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physmem = Param.PhysicalMemory(parent.any, "Physical memory")
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|
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simobj IdeController(PciDevice):
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type = 'IdeController'
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|
|
|
@ -1,3 +1,3 @@
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simobj IntrControl(SimObject):
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type = 'IntrControl'
|
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cpu = Param.BaseCPU(Super, "the cpu")
|
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cpu = Param.BaseCPU(parent.any, "the cpu")
|
||||
|
|
|
@ -47,5 +47,5 @@ simobj PciDevice(DmaDevice):
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pci_bus = Param.Int("PCI bus")
|
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pci_dev = Param.Int("PCI device number")
|
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pci_func = Param.Int("PCI function code")
|
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configdata = Param.PciConfigData(Super, "PCI Config data")
|
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configspace = Param.PciConfigAll(Super, "PCI Configspace")
|
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configdata = Param.PciConfigData(parent.any, "PCI Config data")
|
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configspace = Param.PciConfigAll(parent.any, "PCI Configspace")
|
||||
|
|
|
@ -4,4 +4,4 @@ simobj PhysicalMemory(FunctionalMemory):
|
|||
type = 'PhysicalMemory'
|
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range = Param.AddrRange("Device Address")
|
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file = Param.String('', "memory mapped file")
|
||||
mmu = Param.MemoryController(Super, "Memory Controller")
|
||||
mmu = Param.MemoryController(parent.any, "Memory Controller")
|
||||
|
|
|
@ -2,4 +2,4 @@ simobj Platform(SimObject):
|
|||
type = 'Platform'
|
||||
abstract = True
|
||||
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
|
||||
intrctrl = Param.IntrControl(Super, "interrupt controller")
|
||||
intrctrl = Param.IntrControl(parent.any, "interrupt controller")
|
||||
|
|
|
@ -5,7 +5,7 @@ simobj ConsoleListener(SimObject):
|
|||
simobj SimConsole(SimObject):
|
||||
type = 'SimConsole'
|
||||
append_name = Param.Bool(True, "append name() to filename")
|
||||
intr_control = Param.IntrControl(Super, "interrupt controller")
|
||||
intr_control = Param.IntrControl(parent.any, "interrupt controller")
|
||||
listener = Param.ConsoleListener("console listener")
|
||||
number = Param.Int(0, "console number")
|
||||
output = Param.String('console', "file to dump output to")
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
simobj SimpleDisk(SimObject):
|
||||
type = 'SimpleDisk'
|
||||
disk = Param.DiskImage("Disk Image")
|
||||
physmem = Param.PhysicalMemory(Super, "Physical Memory")
|
||||
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
|
||||
|
|
|
@ -4,12 +4,12 @@ from Platform import Platform
|
|||
simobj Tsunami(Platform):
|
||||
type = 'Tsunami'
|
||||
pciconfig = Param.PciConfigAll("PCI configuration")
|
||||
system = Param.BaseSystem(Super, "system")
|
||||
system = Param.BaseSystem(parent.any, "system")
|
||||
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
|
||||
|
||||
simobj TsunamiCChip(FooPioDevice):
|
||||
type = 'TsunamiCChip'
|
||||
tsunami = Param.Tsunami(Super, "Tsunami")
|
||||
tsunami = Param.Tsunami(parent.any, "Tsunami")
|
||||
|
||||
simobj TsunamiFake(FooPioDevice):
|
||||
type = 'TsunamiFake'
|
||||
|
@ -18,8 +18,8 @@ simobj TsunamiIO(FooPioDevice):
|
|||
type = 'TsunamiIO'
|
||||
time = Param.UInt64(1136073600,
|
||||
"System time to use (0 for actual time, default is 1/1/06)")
|
||||
tsunami = Param.Tsunami(Super, "Tsunami")
|
||||
tsunami = Param.Tsunami(parent.any, "Tsunami")
|
||||
|
||||
simobj TsunamiPChip(FooPioDevice):
|
||||
type = 'TsunamiPChip'
|
||||
tsunami = Param.Tsunami(Super, "Tsunami")
|
||||
tsunami = Param.Tsunami(parent.any, "Tsunami")
|
||||
|
|
|
@ -2,5 +2,5 @@ from Device import PioDevice
|
|||
|
||||
simobj Uart(PioDevice):
|
||||
type = 'Uart'
|
||||
console = Param.SimConsole(Super, "The console")
|
||||
console = Param.SimConsole(parent.any, "The console")
|
||||
size = Param.Addr(0x8, "Device size")
|
||||
|
|
|
@ -74,6 +74,12 @@ class SmartDict(dict):
|
|||
return other / self.convert(other)
|
||||
|
||||
|
||||
# __getitem__ uses dict.get() to return 'False' if the key is not
|
||||
# found (rather than raising KeyError). Note that this does *not*
|
||||
# set the key's value to 'False' in the dict, so that even after
|
||||
# we call env['foo'] we still get a meaningful answer from "'foo'
|
||||
# in env" (which calls dict.__contains__, which we do not
|
||||
# override).
|
||||
def __getitem__(self, key):
|
||||
return self.Proxy(dict.get(self, key, 'False'))
|
||||
|
||||
|
|
|
@ -61,14 +61,29 @@ namespace Stats {
|
|||
//
|
||||
// SimObject constructor: used to maintain static simObjectList
|
||||
//
|
||||
SimObject::SimObject(const string &_name)
|
||||
: objName(_name)
|
||||
SimObject::SimObject(Params *p)
|
||||
: _params(p)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
doDebugBreak = false;
|
||||
#endif
|
||||
|
||||
doRecordEvent = !Stats::event_ignore.match(_name);
|
||||
doRecordEvent = !Stats::event_ignore.match(name());
|
||||
simObjectList.push_back(this);
|
||||
}
|
||||
|
||||
//
|
||||
// SimObject constructor: used to maintain static simObjectList
|
||||
//
|
||||
SimObject::SimObject(const string &_name)
|
||||
: _params(new Params)
|
||||
{
|
||||
_params->name = _name;
|
||||
#ifdef DEBUG
|
||||
doDebugBreak = false;
|
||||
#endif
|
||||
|
||||
doRecordEvent = !Stats::event_ignore.match(name());
|
||||
simObjectList.push_back(this);
|
||||
}
|
||||
|
||||
|
|
|
@ -48,8 +48,16 @@
|
|||
*/
|
||||
class SimObject : public Serializable, protected StartupCallback
|
||||
{
|
||||
public:
|
||||
struct Params {
|
||||
std::string name;
|
||||
};
|
||||
|
||||
protected:
|
||||
std::string objName;
|
||||
Params *_params;
|
||||
|
||||
public:
|
||||
const Params *params() const { return _params; }
|
||||
|
||||
private:
|
||||
friend class Serializer;
|
||||
|
@ -60,15 +68,12 @@ class SimObject : public Serializable, protected StartupCallback
|
|||
static SimObjectList simObjectList;
|
||||
|
||||
public:
|
||||
|
||||
// for Params struct
|
||||
#include "simobj/param/SimObject.hh"
|
||||
|
||||
SimObject(Params *_params);
|
||||
SimObject(const std::string &_name);
|
||||
|
||||
virtual ~SimObject() {}
|
||||
|
||||
virtual const std::string name() const { return objName; }
|
||||
virtual const std::string name() const { return params()->name; }
|
||||
|
||||
// initialization pass of all objects.
|
||||
// Gets invoked after construction, before unserialize.
|
||||
|
|
Loading…
Reference in a new issue