Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 037fe9ee54da7e11c2bd07388b9f79cda9abef4c
This commit is contained in:
commit
bc3d009aba
13 changed files with 224 additions and 111 deletions
|
@ -475,10 +475,6 @@ for build_path in build_paths:
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|||
env.ParseConfig(mysql_config_libs)
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env.ParseConfig(mysql_config_include)
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# Check if the Checker is being used. If so append it to env['CPU_MODELS']
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if env['USE_CHECKER']:
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env['CPU_MODELS'].append('CheckerCPU')
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# Save sticky option settings back to current options file
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sticky_opts.Save(current_opts_file, env)
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|
|
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@ -128,6 +128,11 @@ isa_desc_gen_files = Split('decoder.cc decoder.hh')
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isa_desc_gen_files += [CpuModel.dict[cpu].filename
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for cpu in env['CPU_MODELS']]
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# Also include the CheckerCPU as one of the models if it is being
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# enabled via command line.
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if env['USE_CHECKER']:
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isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
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# The emitter patches up the sources & targets to include the
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# autogenerated files as targets and isa parser itself as a source.
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def isa_desc_emitter(target, source, env):
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|
|
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@ -68,6 +68,13 @@ mem_comp_sig_template = '''
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virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; };
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'''
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# Generate a temporary CPU list, including the CheckerCPU if
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# it's enabled. This isn't used for anything else other than StaticInst
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# headers.
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temp_cpu_list = env['CPU_MODELS']
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if env['USE_CHECKER']:
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temp_cpu_list.append('CheckerCPU')
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# Generate header.
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def gen_cpu_exec_signatures(target, source, env):
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f = open(str(target[0]), 'w')
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@ -75,7 +82,7 @@ def gen_cpu_exec_signatures(target, source, env):
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#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
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#define __CPU_STATIC_INST_EXEC_SIGS_HH__
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'''
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for cpu in env['CPU_MODELS']:
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for cpu in temp_cpu_list:
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xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
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print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
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print >> f, '''
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@ -85,12 +92,14 @@ def gen_cpu_exec_signatures(target, source, env):
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# Generate string that gets printed when header is rebuilt
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def gen_sigs_string(target, source, env):
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return "Generating static_inst_exec_sigs.hh: " \
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+ ', '.join(env['CPU_MODELS'])
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+ ', '.join(temp_cpu_list)
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# Add command to generate header to environment.
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env.Command('static_inst_exec_sigs.hh', models_db,
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Action(gen_cpu_exec_signatures, gen_sigs_string,
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varlist = ['CPU_MODELS']))
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varlist = temp_cpu_list))
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env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
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# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
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# and one of these are not being used.
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@ -122,11 +131,11 @@ if 'FastCPU' in env['CPU_MODELS']:
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if 'AlphaO3CPU' in env['CPU_MODELS']:
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sources += Split('''
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base_dyn_inst.cc
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o3/2bit_local_pred.cc
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o3/alpha_dyn_inst.cc
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o3/alpha_cpu.cc
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o3/alpha_cpu_builder.cc
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o3/base_dyn_inst.cc
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o3/bpred_unit.cc
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o3/btb.cc
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o3/commit.cc
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|
@ -148,8 +157,8 @@ if 'AlphaO3CPU' in env['CPU_MODELS']:
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|||
o3/store_set.cc
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o3/tournament_pred.cc
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''')
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if 'CheckerCPU' in env['CPU_MODELS']:
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sources += Split('checker/o3_builder.cc')
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if env['USE_CHECKER']:
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sources += Split('o3/checker_builder.cc')
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if 'OzoneSimpleCPU' in env['CPU_MODELS']:
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sources += Split('''
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|
@ -161,18 +170,19 @@ if 'OzoneSimpleCPU' in env['CPU_MODELS']:
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ozone/inst_queue.cc
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ozone/rename_table.cc
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''')
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if 'CheckerCPU' in env['CPU_MODELS']:
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sources += Split('checker/ozone_builder.cc')
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if 'OzoneCPU' in env['CPU_MODELS']:
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sources += Split('''
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ozone/base_dyn_inst.cc
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ozone/bpred_unit.cc
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ozone/lsq_unit.cc
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ozone/lw_back_end.cc
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ozone/lw_lsq.cc
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''')
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if env['USE_CHECKER']:
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sources += Split('ozone/checker_builder.cc')
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if 'CheckerCPU' in env['CPU_MODELS']:
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sources += Split('checker/cpu.cc')
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if env['USE_CHECKER']:
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checker_supports = False
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for i in CheckerSupportedCPUList:
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if i in env['CPU_MODELS']:
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|
|
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@ -41,10 +41,6 @@
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#include "mem/request.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "cpu/o3/alpha_cpu.hh"
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//#include "cpu/ozone/simple_impl.hh"
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//#include "cpu/ozone/ozone_impl.hh"
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using namespace std;
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using namespace TheISA;
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@ -301,25 +297,3 @@ BaseDynInst<Impl>::eaSrcsReady()
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return true;
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}
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// Forward declaration
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template class BaseDynInst<AlphaSimpleImpl>;
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template <>
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int
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BaseDynInst<AlphaSimpleImpl>::instcount = 0;
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/*
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// Forward declaration
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template class BaseDynInst<SimpleImpl>;
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template <>
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int
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BaseDynInst<SimpleImpl>::instcount = 0;
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// Forward declaration
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template class BaseDynInst<OzoneImpl>;
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template <>
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int
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BaseDynInst<OzoneImpl>::instcount = 0;
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*/
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@ -43,16 +43,10 @@
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "cpu/o3/alpha_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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//#include "cpu/ozone/dyn_inst.hh"
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//#include "cpu/ozone/ozone_impl.hh"
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//#include "cpu/ozone/simple_impl.hh"
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#if FULL_SYSTEM
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#include "sim/system.hh"
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#include "arch/vtophys.hh"
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#include "kern/kernel_stats.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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@ -826,9 +820,3 @@ Checker<DynInstPtr>::dumpInsts()
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}
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}
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//template
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//class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
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// Manually instantiate checker
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template
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class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
|
40
src/cpu/o3/base_dyn_inst.cc
Normal file
40
src/cpu/o3/base_dyn_inst.cc
Normal file
|
@ -0,0 +1,40 @@
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|||
/*
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||||
* Copyright (c) 2006 The Regents of The University of Michigan
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||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
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#include "cpu/base_dyn_inst_impl.hh"
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#include "cpu/o3/alpha_cpu.hh"
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#include "cpu/o3/alpha_impl.hh"
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||||
// Explicit instantiation
|
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template class BaseDynInst<AlphaSimpleImpl>;
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template <>
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int
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BaseDynInst<AlphaSimpleImpl>::instcount = 0;
|
|
@ -31,9 +31,5 @@
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#include "cpu/o3/bpred_unit_impl.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "cpu/o3/alpha_dyn_inst.hh"
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//#include "cpu/ozone/ozone_impl.hh"
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//#include "cpu/ozone/simple_impl.hh"
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template class BPredUnit<AlphaSimpleImpl>;
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//template class BPredUnit<OzoneImpl>;
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//template class BPredUnit<SimpleImpl>;
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|
|
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@ -30,7 +30,7 @@
|
|||
|
||||
#include <string>
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#include "cpu/checker/cpu.hh"
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#include "cpu/checker/cpu_impl.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/alpha_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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|
@ -40,6 +40,9 @@
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|||
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class MemObject;
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template
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class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
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/**
|
||||
* Specific non-templated derived class used for SimObject configuration.
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||||
*/
|
36
src/cpu/ozone/bpred_unit.cc
Normal file
36
src/cpu/ozone/bpred_unit.cc
Normal file
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#include "cpu/o3/bpred_unit_impl.hh"
|
||||
#include "cpu/ozone/ozone_impl.hh"
|
||||
#include "cpu/ozone/simple_impl.hh"
|
||||
|
||||
template class BPredUnit<OzoneImpl>;
|
||||
template class BPredUnit<SimpleImpl>;
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
#include <string>
|
||||
|
||||
#include "cpu/checker/cpu.hh"
|
||||
#include "cpu/checker/cpu_impl.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "cpu/ozone/dyn_inst.hh"
|
||||
#include "cpu/ozone/ozone_impl.hh"
|
||||
|
@ -39,6 +39,9 @@
|
|||
#include "sim/process.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
template
|
||||
class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
|
||||
|
||||
/**
|
||||
* Specific non-templated derived class used for SimObject configuration.
|
||||
*/
|
39
src/cpu/ozone/ozone_base_dyn_inst.cc
Normal file
39
src/cpu/ozone/ozone_base_dyn_inst.cc
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#include "cpu/base_dyn_inst_impl.hh"
|
||||
#include "cpu/ozone/ozone_impl.hh"
|
||||
|
||||
// Explicit instantiation
|
||||
template class BaseDynInst<OzoneImpl>;
|
||||
|
||||
template <>
|
||||
int
|
||||
BaseDynInst<OzoneImpl>::instcount = 0;
|
39
src/cpu/ozone/simple_base_dyn_inst.cc
Normal file
39
src/cpu/ozone/simple_base_dyn_inst.cc
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#include "cpu/base_dyn_inst_impl.hh"
|
||||
#include "cpu/ozone/simple_impl.hh"
|
||||
|
||||
// Explicit instantiation
|
||||
template class BaseDynInst<SimpleImpl>;
|
||||
|
||||
template <>
|
||||
int
|
||||
BaseDynInst<SimpleImpl>::instcount = 0;
|
|
@ -84,32 +84,32 @@ def setTraceStart(option, opt_str, value, parser):
|
|||
def setTraceFile(option, opt_str, value, parser):
|
||||
objects.Trace.file = value
|
||||
|
||||
def usePCSymbol(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.pc_symbol = value
|
||||
def noPCSymbol(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.pc_symbol = False
|
||||
|
||||
def printCycle(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_cycle = value
|
||||
def noPrintCycle(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_cycle = False
|
||||
|
||||
def printOp(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_opclass = value
|
||||
def noPrintOpclass(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_opclass = False
|
||||
|
||||
def printThread(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_thread = value
|
||||
def noPrintThread(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_thread = False
|
||||
|
||||
def printEA(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_effaddr = value
|
||||
def noPrintEA(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_effaddr = False
|
||||
|
||||
def printData(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_data = value
|
||||
def noPrintData(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_data = False
|
||||
|
||||
def printFetchseq(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_fetchseq = value
|
||||
objects.ExecutionTrace.print_fetchseq = True
|
||||
|
||||
def printCpseq(option, opt_str, value, parser):
|
||||
objects.ExecutionTrace.print_cpseq = value
|
||||
objects.ExecutionTrace.print_cpseq = True
|
||||
|
||||
def dumpOnExit(option, opt_str, value, parser):
|
||||
objects.Trace.dump_on_exit = value
|
||||
objects.Trace.dump_on_exit = True
|
||||
|
||||
def debugBreak(option, opt_str, value, parser):
|
||||
objects.Debug.break_cycles = value
|
||||
|
@ -131,47 +131,31 @@ standardOptions = [
|
|||
callback=setTraceStart),
|
||||
optparse.make_option("--tracefile", type="string", action="callback",
|
||||
callback=setTraceFile),
|
||||
optparse.make_option("--pcsymbol", type="choice", choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
action="callback", callback=usePCSymbol,
|
||||
help="Use PC symbols in trace output"),
|
||||
optparse.make_option("--printcycle", type="choice", choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
action="callback", callback=printCycle,
|
||||
help="Print cycle numbers in trace output"),
|
||||
optparse.make_option("--printopclass", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
action="callback", callback=printOp,
|
||||
help="Print cycle numbers in trace output"),
|
||||
optparse.make_option("--printthread", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
action="callback", callback=printThread,
|
||||
help="Print thread number in trace output"),
|
||||
optparse.make_option("--printeffaddr", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
action="callback", callback=printEA,
|
||||
help="Print effective address in trace output"),
|
||||
optparse.make_option("--printdata", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
action="callback", callback=printData,
|
||||
help="Print result data in trace output"),
|
||||
optparse.make_option("--printfetchseq", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
optparse.make_option("--nopcsymbol",
|
||||
action="callback", callback=noPCSymbol,
|
||||
help="Disable PC symbols in trace output"),
|
||||
optparse.make_option("--noprintcycle",
|
||||
action="callback", callback=noPrintCycle,
|
||||
help="Don't print cycle numbers in trace output"),
|
||||
optparse.make_option("--noprintopclass",
|
||||
action="callback", callback=noPrintOpclass,
|
||||
help="Don't print op class type in trace output"),
|
||||
optparse.make_option("--noprintthread",
|
||||
action="callback", callback=noPrintThread,
|
||||
help="Don't print thread number in trace output"),
|
||||
optparse.make_option("--noprinteffaddr",
|
||||
action="callback", callback=noPrintEA,
|
||||
help="Don't print effective address in trace output"),
|
||||
optparse.make_option("--noprintdata",
|
||||
action="callback", callback=noPrintData,
|
||||
help="Don't print result data in trace output"),
|
||||
optparse.make_option("--printfetchseq",
|
||||
action="callback", callback=printFetchseq,
|
||||
help="Print fetch sequence numbers in trace output"),
|
||||
optparse.make_option("--printcpseq", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
optparse.make_option("--printcpseq",
|
||||
action="callback", callback=printCpseq,
|
||||
help="Print correct path sequence numbers in trace output"),
|
||||
optparse.make_option("--dumponexit", type="choice",
|
||||
choices=TrueOrFalse,
|
||||
default="True", metavar=TorF,
|
||||
optparse.make_option("--dumponexit",
|
||||
action="callback", callback=dumpOnExit,
|
||||
help="Dump trace buffer on exit"),
|
||||
optparse.make_option("--debugbreak", type="int", metavar="CYCLE",
|
||||
|
|
Loading…
Reference in a new issue