X86: Flesh out register indexing constants.
--HG-- extra : convert_revision : 56eedc076bbb7962c3976599a15ed93c7cb154c0
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6204d00940
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@ -100,7 +100,8 @@ namespace X86ISA
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{
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{
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std::string getFloatRegName(RegIndex);
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std::string getFloatRegName(RegIndex);
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const int NumFloatArchRegs = NumMMXRegs + NumXMMRegs;
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//Each 128 bit xmm register is broken into two effective 64 bit registers.
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const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs;
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const int NumFloatRegs = NumFloatArchRegs;
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const int NumFloatRegs = NumFloatArchRegs;
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class FloatRegFile
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class FloatRegFile
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@ -115,6 +116,7 @@ namespace X86ISA
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{
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{
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uint64_t q[NumFloatRegs];
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uint64_t q[NumFloatRegs];
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double d[NumFloatRegs];
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double d[NumFloatRegs];
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float f[NumFloatRegs][2];
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};
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};
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public:
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public:
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@ -107,6 +107,6 @@ def operands {{
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'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
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'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
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'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
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'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
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'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
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'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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}};
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}};
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@ -58,6 +58,7 @@
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#ifndef __ARCH_X86_MISCREGS_HH__
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#ifndef __ARCH_X86_MISCREGS_HH__
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#define __ARCH_X86_MISCREGS_HH__
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#define __ARCH_X86_MISCREGS_HH__
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#include "arch/x86/x86_traits.hh"
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#include "base/bitunion.hh"
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#include "base/bitunion.hh"
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namespace X86ISA
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namespace X86ISA
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@ -97,7 +98,7 @@ namespace X86ISA
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MISCREG_CR15,
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MISCREG_CR15,
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// Debug registers
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// Debug registers
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MISCREG_DR_BASE,
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MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
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MISCREG_DR0 = MISCREG_DR_BASE,
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MISCREG_DR0 = MISCREG_DR_BASE,
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MISCREG_DR1,
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MISCREG_DR1,
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MISCREG_DR2,
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MISCREG_DR2,
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@ -108,7 +109,7 @@ namespace X86ISA
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MISCREG_DR7,
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MISCREG_DR7,
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// Flags register
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// Flags register
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MISCREG_RFLAGS,
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MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
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// Segment selectors
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// Segment selectors
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MISCREG_SEG_SEL_BASE,
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MISCREG_SEG_SEL_BASE,
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@ -120,7 +121,7 @@ namespace X86ISA
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MISCREG_GS,
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MISCREG_GS,
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// Hidden segment base field
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// Hidden segment base field
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MISCREG_SEG_BASE_BASE,
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MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
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MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
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MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
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MISCREG_CS_BASE,
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MISCREG_CS_BASE,
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MISCREG_SS_BASE,
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MISCREG_SS_BASE,
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@ -129,7 +130,7 @@ namespace X86ISA
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MISCREG_GS_BASE,
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MISCREG_GS_BASE,
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// Hidden segment limit field
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// Hidden segment limit field
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MISCREG_SEG_LIMIT_BASE,
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MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
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MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
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MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
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MISCREG_CS_LIMIT,
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MISCREG_CS_LIMIT,
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MISCREG_SS_LIMIT,
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MISCREG_SS_LIMIT,
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@ -138,7 +139,7 @@ namespace X86ISA
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MISCREG_GS_LIMIT,
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MISCREG_GS_LIMIT,
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// Hidden segment limit attributes
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// Hidden segment limit attributes
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MISCREG_SEG_ATTR_BASE,
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MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
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MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
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MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
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MISCREG_CS_ATTR,
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MISCREG_CS_ATTR,
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MISCREG_SS_ATTR,
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MISCREG_SS_ATTR,
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@ -147,34 +148,94 @@ namespace X86ISA
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MISCREG_GS_ATTR,
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MISCREG_GS_ATTR,
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// System segment selectors
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// System segment selectors
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MISCREG_SYSSEG_SEL_BASE,
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MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
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MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
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MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
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MISCREG_TR,
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MISCREG_TR,
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// Hidden system segment base field
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// Hidden system segment base field
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MISCREG_SYSSEG_BASE_BASE,
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MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
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MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
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MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
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MISCREG_TR_BASE,
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MISCREG_TR_BASE,
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MISCREG_GDTR_BASE,
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MISCREG_GDTR_BASE,
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MISCREG_IDTR_BASE,
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MISCREG_IDTR_BASE,
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// Hidden system segment limit field
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// Hidden system segment limit field
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MISCREG_SYSSEG_LIMIT_BASE,
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MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
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MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
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MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
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MISCREG_TR_LIMIT,
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MISCREG_TR_LIMIT,
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MISCREG_GDTR_LIMIT,
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MISCREG_GDTR_LIMIT,
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MISCREG_IDTR_LIMIT,
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MISCREG_IDTR_LIMIT,
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// Hidden system segment attribute field
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// Hidden system segment attribute field
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MISCREG_SYSSEG_ATTR_BASE,
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MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
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MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
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MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
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MISCREG_TR_ATTR,
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MISCREG_TR_ATTR,
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//XXX Add "Model-Specific Registers"
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//XXX Add "Model-Specific Registers"
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NUM_MISCREGS
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NUM_MISCREGS = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments
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};
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};
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static inline MiscRegIndex
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MISCREG_CR(int index)
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{
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return (MiscRegIndex)(MISCREG_CR_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_DR(int index)
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{
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return (MiscRegIndex)(MISCREG_DR_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SEG_SEL(int index)
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{
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return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SEG_BASE(int index)
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{
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return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SEG_LIMIT(int index)
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{
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return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SEG_ATTR(int index)
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{
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return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SYSSEG_SEL(int index)
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{
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return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SYSSEG_BASE(int index)
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{
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return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SYSSEG_LIMIT(int index)
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{
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return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SYSSEG_ATTR(int index)
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{
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return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
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}
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/**
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/**
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* A type to describe the condition code bits of the RFLAGS register,
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* A type to describe the condition code bits of the RFLAGS register,
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* plus two flags, EZF and ECF, which are only visible to microcode.
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* plus two flags, EZF and ECF, which are only visible to microcode.
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@ -65,6 +65,12 @@ namespace X86ISA
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const int NumMMXRegs = 8;
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const int NumMMXRegs = 8;
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const int NumXMMRegs = 16;
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const int NumXMMRegs = 16;
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const int NumCRegs = 16;
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const int NumDRegs = 8;
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const int NumSegments = 6;
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const int NumSysSegments = 4;
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}
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}
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#endif //__ARCH_X86_X86TRAITS_HH__
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#endif //__ARCH_X86_X86TRAITS_HH__
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