sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Merge ktlim@zizzer:/bk/newmem

Browse source 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress

--HG--
extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
This commit is contained in:
Kevin Lim 2006-12-12 17:55:50 -05:00
commit bc05f5982e
1 changed files with 14 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
src/cpu/o3/iew_impl.hh
View file

@ -514,6 +514,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
toCommit->squash[tid] = true; toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->nextPC[tid] = inst->readNextPC(); toCommit->nextPC[tid] = inst->readNextPC();
toCommit->branchMispredict[tid] = false;
toCommit->includeSquashInst[tid] = false; toCommit->includeSquashInst[tid] = false;
@ -530,6 +531,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
toCommit->squash[tid] = true; toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->nextPC[tid] = inst->readPC(); toCommit->nextPC[tid] = inst->readPC();
toCommit->branchMispredict[tid] = false;
// Must include the broadcasted SN in the squash. // Must include the broadcasted SN in the squash.
toCommit->includeSquashInst[tid] = true; toCommit->includeSquashInst[tid] = true;
@ -1291,7 +1293,8 @@ DefaultIEW<Impl>::executeInsts()
} else if (fault != NoFault) { } else if (fault != NoFault) {
// If the instruction faulted, then we need to send it along to commit // If the instruction faulted, then we need to send it along to commit
// without the instruction completing. // without the instruction completing.
DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum); DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
fault->name(), inst->seqNum);
// Send this instruction to commit, also make sure iew stage // Send this instruction to commit, also make sure iew stage
// realizes there is activity. // realizes there is activity.
@ -1328,7 +1331,8 @@ DefaultIEW<Impl>::executeInsts()
// instruction first, so the branch resolution order will be correct. // instruction first, so the branch resolution order will be correct.
unsigned tid = inst->threadNumber; unsigned tid = inst->threadNumber;
if (!fetchRedirect[tid]) { if (!fetchRedirect[tid] ||
toCommit->squashedSeqNum[tid] > inst->seqNum) {
if (inst->mispredicted()) { if (inst->mispredicted()) {
fetchRedirect[tid] = true; fetchRedirect[tid] = true;
@ -1350,8 +1354,6 @@ DefaultIEW<Impl>::executeInsts()
predictedNotTakenIncorrect++; predictedNotTakenIncorrect++;
} }
} else if (ldstQueue.violation(tid)) { } else if (ldstQueue.violation(tid)) {
fetchRedirect[tid] = true;
// If there was an ordering violation, then get the // If there was an ordering violation, then get the
// DynInst that caused the violation. Note that this // DynInst that caused the violation. Note that this
// clears the violation signal. // clears the violation signal.
@ -1362,6 +1364,14 @@ DefaultIEW<Impl>::executeInsts()
"%#x, inst PC: %#x. Addr is: %#x.\n", "%#x, inst PC: %#x. Addr is: %#x.\n",
violator->readPC(), inst->readPC(), inst->physEffAddr); violator->readPC(), inst->readPC(), inst->physEffAddr);
// Ensure the violating instruction is older than
// current squash
if (fetchRedirect[tid] &&
violator->seqNum >= toCommit->squashedSeqNum[tid])
continue;
fetchRedirect[tid] = true;
// Tell the instruction queue that a violation has occured. // Tell the instruction queue that a violation has occured.
instQueue.violation(inst, violator); instQueue.violation(inst, violator);