ARM: Implement the SRS instruction.
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@ -110,7 +110,7 @@ SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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ss << "!";
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ss << "!";
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}
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}
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ss << ", #";
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ss << ", #";
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switch (mode) {
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switch (regMode) {
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case MODE_USER:
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case MODE_USER:
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ss << "user";
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ss << "user";
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break;
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break;
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@ -38,9 +38,9 @@
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// Authors: Gabe Black
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// Authors: Gabe Black
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let {{
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let {{
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def loadStoreBaseWork(name, Name, imm, swp, rfe, codeBlobs, memFlags,
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def loadStoreBaseWork(name, Name, imm, swp, rfe, srs, codeBlobs,
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instFlags, double, strex, base = 'Memory',
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memFlags, instFlags, double, strex,
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execTemplateBase = ''):
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base = 'Memory', execTemplateBase = ''):
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# Make sure flags are in lists (convert to lists if not).
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# Make sure flags are in lists (convert to lists if not).
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memFlags = makeList(memFlags)
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memFlags = makeList(memFlags)
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instFlags = makeList(instFlags)
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instFlags = makeList(instFlags)
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@ -66,6 +66,9 @@ let {{
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elif rfe:
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elif rfe:
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declareTemplate = RfeDeclare
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declareTemplate = RfeDeclare
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constructTemplate = RfeConstructor
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constructTemplate = RfeConstructor
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elif srs:
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declareTemplate = SrsDeclare
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constructTemplate = SrsConstructor
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elif imm:
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elif imm:
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if double:
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if double:
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declareTemplate = LoadStoreDImmDeclare
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declareTemplate = LoadStoreDImmDeclare
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@ -101,26 +104,35 @@ let {{
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"memacc_code": accCode,
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"memacc_code": accCode,
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"postacc_code": postAccCode,
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"postacc_code": postAccCode,
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"predicate_test": predicateTest }
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"predicate_test": predicateTest }
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return loadStoreBaseWork(name, Name, imm, False, False, codeBlobs,
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return loadStoreBaseWork(name, Name, imm, False, False, False,
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memFlags, instFlags, double, strex, base,
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codeBlobs, memFlags, instFlags, double,
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execTemplateBase)
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strex, base, execTemplateBase)
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def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
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def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
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codeBlobs = { "ea_code": eaCode,
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codeBlobs = { "ea_code": eaCode,
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"memacc_code": accCode,
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"memacc_code": accCode,
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"predicate_test": predicateTest }
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"predicate_test": predicateTest }
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return loadStoreBaseWork(name, Name, False, False, True, codeBlobs,
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return loadStoreBaseWork(name, Name, False, False, True, False,
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memFlags, instFlags, False, False,
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codeBlobs, memFlags, instFlags, False, False,
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'RfeOp', 'Load')
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'RfeOp', 'Load')
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def SrsBase(name, Name, eaCode, accCode, memFlags, instFlags):
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codeBlobs = { "ea_code": eaCode,
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"memacc_code": accCode,
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"postacc_code": "",
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"predicate_test": predicateTest }
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return loadStoreBaseWork(name, Name, False, False, False, True,
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codeBlobs, memFlags, instFlags, False, False,
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'SrsOp', 'Store')
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def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
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def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
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instFlags):
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instFlags):
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codeBlobs = { "ea_code": eaCode,
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codeBlobs = { "ea_code": eaCode,
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"preacc_code": preAccCode,
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"preacc_code": preAccCode,
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"postacc_code": postAccCode,
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"postacc_code": postAccCode,
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"predicate_test": predicateTest }
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"predicate_test": predicateTest }
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return loadStoreBaseWork(name, Name, False, True, False, codeBlobs,
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return loadStoreBaseWork(name, Name, False, True, False, False,
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memFlags, instFlags, False, False,
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codeBlobs, memFlags, instFlags, False, False,
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'Swap', 'Swap')
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'Swap', 'Swap')
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def memClassName(base, post, add, writeback, \
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def memClassName(base, post, add, writeback, \
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@ -116,6 +116,40 @@ let {{
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memFlags, [], base, strex=strex,
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memFlags, [], base, strex=strex,
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execTemplateBase = execTemplateBase)
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execTemplateBase = execTemplateBase)
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def buildSrsStore(mnem, post, add, writeback):
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name = mnem
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Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
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offset = 0
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if post != add:
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offset += 4
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if not add:
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offset -= 8
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eaCode = "EA = SpMode + %d;" % offset
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wbDiff = -8
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if add:
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wbDiff = 8
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accCode = '''
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CPSR cpsr = Cpsr;
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Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
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((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
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'''
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if writeback:
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accCode += "SpMode = SpMode + %s;\n" % wbDiff
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global header_output, decoder_output, exec_output
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(newHeader,
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newDecoder,
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newExec) = SrsBase(name, Name, eaCode, accCode,
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["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [])
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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def buildRegStore(mnem, post, add, writeback, \
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def buildRegStore(mnem, post, add, writeback, \
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size=4, sign=False, user=False, strex=False):
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size=4, sign=False, user=False, strex=False):
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name = mnem
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name = mnem
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@ -241,6 +275,16 @@ let {{
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buildDoubleImmStore(mnem, False, False, False)
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buildDoubleImmStore(mnem, False, False, False)
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buildDoubleRegStore(mnem, False, False, False)
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buildDoubleRegStore(mnem, False, False, False)
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def buildSrsStores(mnem):
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buildSrsStore(mnem, True, True, True)
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buildSrsStore(mnem, True, True, False)
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buildSrsStore(mnem, True, False, True)
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buildSrsStore(mnem, True, False, False)
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buildSrsStore(mnem, False, True, True)
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buildSrsStore(mnem, False, True, False)
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buildSrsStore(mnem, False, False, True)
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buildSrsStore(mnem, False, False, False)
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buildStores("str")
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buildStores("str")
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buildStores("strt", user=True)
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buildStores("strt", user=True)
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buildStores("strb", size=1)
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buildStores("strb", size=1)
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@ -248,6 +292,8 @@ let {{
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buildStores("strh", size=2)
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buildStores("strh", size=2)
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buildStores("strht", size=2, user=True)
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buildStores("strht", size=2, user=True)
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buildSrsStores("srs")
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buildDoubleStores("strd")
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buildDoubleStores("strd")
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buildImmStore("strex", False, True, False, size=4, strex=True)
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buildImmStore("strex", False, True, False, size=4, strex=True)
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