ruby: rename MESI_CMP_directory to MESI_Two_Level

This is because the next patch introduces a three level hierarchy.

--HG--
rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level
rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py
rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm
rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm
rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm
rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm
rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm
rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
This commit is contained in:
Nilay Vaish 2014-01-04 00:03:33 -06:00
parent 9ec59e8b69
commit bb6d7d402b
38 changed files with 23 additions and 23 deletions

View file

@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MESI_CMP_directory' PROTOCOL = 'MESI_Two_Level'

View file

@ -1,3 +1,3 @@
TARGET_ISA = 'x86' TARGET_ISA = 'x86'
CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU' CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
PROTOCOL = 'MESI_CMP_directory' PROTOCOL = 'MESI_Two_Level'

View file

@ -50,8 +50,8 @@ def define_options(parser):
def create_system(options, system, piobus, dma_ports, ruby_system): def create_system(options, system, piobus, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
panic("This script requires the MESI_CMP_directory protocol to be built.") fatal("This script requires the MESI_Two_Level protocol to be built.")
cpu_sequencers = [] cpu_sequencers = []

View file

@ -1,7 +0,0 @@
protocol "MESI_CMP_directory";
include "RubySlicc_interfaces.slicc";
include "MESI_CMP_directory-msg.sm";
include "MESI_CMP_directory-L1cache.sm";
include "MESI_CMP_directory-L2cache.sm";
include "MESI_CMP_directory-dir.sm";
include "MESI_CMP_directory-dma.sm";

View file

@ -34,7 +34,7 @@
// Copied here by aep 12/14/07 // Copied here by aep 12/14/07
machine(Directory, "MESI_CMP_filter_directory protocol") machine(Directory, "MESI Two Level directory protocol")
: DirectoryMemory * directory, : DirectoryMemory * directory,
MemoryControl * memBuffer, MemoryControl * memBuffer,
Cycles to_mem_ctrl_latency = 1, Cycles to_mem_ctrl_latency = 1,

View file

@ -0,0 +1,7 @@
protocol "MESI_Two_Level";
include "RubySlicc_interfaces.slicc";
include "MESI_Two_Level-msg.sm";
include "MESI_Two_Level-L1cache.sm";
include "MESI_Two_Level-L2cache.sm";
include "MESI_Two_Level-dir.sm";
include "MESI_Two_Level-dma.sm";

View file

@ -33,7 +33,7 @@ import os
Import('*') Import('*')
all_protocols.extend([ all_protocols.extend([
'MESI_CMP_directory', 'MESI_Two_Level',
'MI_example', 'MI_example',
'MOESI_CMP_directory', 'MOESI_CMP_directory',
'MOESI_CMP_token', 'MOESI_CMP_token',

View file

@ -41,14 +41,14 @@ add_option('-v', '--verbose', action='store_true', default=False,
help='echo commands before executing') help='echo commands before executing')
add_option('--builds', add_option('--builds',
default='ALPHA,ALPHA_MOESI_hammer,' \ default='ALPHA,ALPHA_MOESI_hammer,' \
'ALPHA_MESI_CMP_directory,' \ 'ALPHA_MESI_Two_Level,' \
'ALPHA_MOESI_CMP_directory,' \ 'ALPHA_MOESI_CMP_directory,' \
'ALPHA_MOESI_CMP_token,' \ 'ALPHA_MOESI_CMP_token,' \
'MIPS,' \ 'MIPS,' \
'NULL,' \ 'NULL,' \
'POWER,' \ 'POWER,' \
'SPARC,' \ 'SPARC,' \
'X86,X86_MESI_CMP_directory,' \ 'X86,X86_MESI_Two_Level,' \
'ARM', 'ARM',
help="comma-separated build targets to test (default: '%default')") help="comma-separated build targets to test (default: '%default')")
add_option('--modes', add_option('--modes',