ruby: rename MESI_CMP_directory to MESI_Two_Level
This is because the next patch introduces a three level hierarchy. --HG-- rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
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38 changed files with 23 additions and 23 deletions
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@ -1,3 +1,3 @@
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SS_COMPATIBLE_FP = 1
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MESI_CMP_directory'
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PROTOCOL = 'MESI_Two_Level'
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@ -1,3 +1,3 @@
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TARGET_ISA = 'x86'
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TARGET_ISA = 'x86'
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CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
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CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
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PROTOCOL = 'MESI_CMP_directory'
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PROTOCOL = 'MESI_Two_Level'
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@ -50,8 +50,8 @@ def define_options(parser):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
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if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
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panic("This script requires the MESI_CMP_directory protocol to be built.")
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fatal("This script requires the MESI_Two_Level protocol to be built.")
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cpu_sequencers = []
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cpu_sequencers = []
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@ -1,7 +0,0 @@
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protocol "MESI_CMP_directory";
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include "RubySlicc_interfaces.slicc";
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include "MESI_CMP_directory-msg.sm";
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include "MESI_CMP_directory-L1cache.sm";
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include "MESI_CMP_directory-L2cache.sm";
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include "MESI_CMP_directory-dir.sm";
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include "MESI_CMP_directory-dma.sm";
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@ -34,7 +34,7 @@
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// Copied here by aep 12/14/07
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// Copied here by aep 12/14/07
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machine(Directory, "MESI_CMP_filter_directory protocol")
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machine(Directory, "MESI Two Level directory protocol")
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: DirectoryMemory * directory,
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: DirectoryMemory * directory,
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MemoryControl * memBuffer,
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MemoryControl * memBuffer,
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Cycles to_mem_ctrl_latency = 1,
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Cycles to_mem_ctrl_latency = 1,
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7
src/mem/protocol/MESI_Two_Level.slicc
Normal file
7
src/mem/protocol/MESI_Two_Level.slicc
Normal file
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@ -0,0 +1,7 @@
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protocol "MESI_Two_Level";
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include "RubySlicc_interfaces.slicc";
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include "MESI_Two_Level-msg.sm";
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include "MESI_Two_Level-L1cache.sm";
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include "MESI_Two_Level-L2cache.sm";
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include "MESI_Two_Level-dir.sm";
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include "MESI_Two_Level-dma.sm";
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@ -33,7 +33,7 @@ import os
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Import('*')
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Import('*')
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all_protocols.extend([
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all_protocols.extend([
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'MESI_CMP_directory',
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'MESI_Two_Level',
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'MI_example',
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'MI_example',
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'MOESI_CMP_directory',
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'MOESI_CMP_directory',
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'MOESI_CMP_token',
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'MOESI_CMP_token',
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@ -41,14 +41,14 @@ add_option('-v', '--verbose', action='store_true', default=False,
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help='echo commands before executing')
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help='echo commands before executing')
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add_option('--builds',
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add_option('--builds',
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default='ALPHA,ALPHA_MOESI_hammer,' \
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default='ALPHA,ALPHA_MOESI_hammer,' \
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'ALPHA_MESI_CMP_directory,' \
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'ALPHA_MESI_Two_Level,' \
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'ALPHA_MOESI_CMP_directory,' \
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'ALPHA_MOESI_CMP_directory,' \
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'ALPHA_MOESI_CMP_token,' \
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'ALPHA_MOESI_CMP_token,' \
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'MIPS,' \
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'MIPS,' \
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'NULL,' \
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'NULL,' \
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'POWER,' \
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'POWER,' \
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'SPARC,' \
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'SPARC,' \
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'X86,X86_MESI_CMP_directory,' \
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'X86,X86_MESI_Two_Level,' \
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'ARM',
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'ARM',
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help="comma-separated build targets to test (default: '%default')")
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help="comma-separated build targets to test (default: '%default')")
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add_option('--modes',
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add_option('--modes',
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