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ARM: When an instruction is intentionally undefined, fault on it.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:09 -05:00
parent 61a5e71be7
commit bb0d390105
2 changed files with 8 additions and 8 deletions
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10
src/arch/arm/isa/decoder/thumb.isa
View file

@ -102,7 +102,7 @@
0x3: WarnUnimpl::Advanced_SIMD(); 0x3: WarnUnimpl::Advanced_SIMD();
default: decode LTCOPROC { default: decode LTCOPROC {
0xa, 0xb: decode HTOPCODE_9_4 { 0xa, 0xb: decode HTOPCODE_9_4 {
0x00: WarnUnimpl::undefined(); 0x00: Unknown::undefined();
0x04: WarnUnimpl::mcrr(); // mcrr2 0x04: WarnUnimpl::mcrr(); // mcrr2
0x05: WarnUnimpl::mrrc(); // mrrc2 0x05: WarnUnimpl::mrrc(); // mrrc2
0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
@ -116,7 +116,7 @@
} }
} }
default: decode HTOPCODE_9_5 { default: decode HTOPCODE_9_5 {
0x00: WarnUnimpl::undefined(); 0x00: Unknown::undefined();
0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
@ -142,7 +142,7 @@
0x0: LoadByteMemoryHints::loadByteMemoryHints(); 0x0: LoadByteMemoryHints::loadByteMemoryHints();
0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints(); 0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
0x2: Thumb32LoadWord::thumb32LoadWord(); 0x2: Thumb32LoadWord::thumb32LoadWord();
0x3: WarnUnimpl::undefined(); 0x3: Unknown::undefined();
} }
} }
0x1: decode HTOPCODE_8_7 { 0x1: decode HTOPCODE_8_7 {
@ -170,7 +170,7 @@
0x3: WarnUnimpl::Advanced_SIMD(); 0x3: WarnUnimpl::Advanced_SIMD();
default: decode LTCOPROC { default: decode LTCOPROC {
0xa, 0xb: decode HTOPCODE_9_4 { 0xa, 0xb: decode HTOPCODE_9_4 {
0x00: WarnUnimpl::undefined(); 0x00: Unknown::undefined();
0x04: WarnUnimpl::mcrr(); // mcrr2 0x04: WarnUnimpl::mcrr(); // mcrr2
0x05: WarnUnimpl::mrrc(); // mrrc2 0x05: WarnUnimpl::mrrc(); // mrrc2
0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
@ -184,7 +184,7 @@
} }
} }
default: decode HTOPCODE_9_5 { default: decode HTOPCODE_9_5 {
0x00: WarnUnimpl::undefined(); 0x00: Unknown::undefined();
0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:

6
src/arch/arm/isa/formats/branch.isa
View file

@ -104,7 +104,7 @@ def format Thumb16CondBranchAndSvc() {{
return new Svc(machInst); return new Svc(machInst);
} else { } else {
// This space will not be allocated in the future. // This space will not be allocated in the future.
return new WarnUnimplemented("unimplemented", machInst); return new Unknown(machInst);
} }
''' '''
}}; }};
@ -124,8 +124,8 @@ def format Thumb32BranchesAndMiscCtrl() {{
case 0x0: case 0x0:
if (op == 127) { if (op == 127) {
if (op1 & 0x2) { if (op1 & 0x2) {
// Permanentl undefined. // Permanently undefined.
return new WarnUnimplemented("undefined", machInst); return new Unknown(machInst);
} else { } else {
return new WarnUnimplemented("smc", machInst); return new WarnUnimplemented("smc", machInst);
} }