X86: Make instructions use pick, and implement/adjust some multiplication microops and instructions.
--HG-- extra : convert_revision : 5c56f6819ee07d936b388b3d1810a3b73db84f9c
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2 changed files with 184 additions and 43 deletions
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@ -55,6 +55,100 @@
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microcode = '''
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microcode = '''
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#
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# Byte version of one operand unsigned multiply.
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#
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def macroop MUL_B_R
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{
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mul1u rax, rax, reg, dataSize="2"
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};
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def macroop MUL_B_M
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{
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ld t1, ds, [scale, index, base], disp
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mul1u rax, rax, t1, dataSize="2"
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};
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def macroop MUL_B_P
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{
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rdip t7
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ld t1, ds, [scale, index, base], disp
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mul1u rax, rax, t1, dataSize="2"
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};
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#
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# One operand unsigned multiply.
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#
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def macroop MUL_R
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{
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muleh rdx, rax, reg
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mulel rax, rax, reg
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};
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def macroop MUL_M
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{
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ld t1, ds, [scale, index, base], disp
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muleh rdx, rax, t1
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mulel rax, rax, t1
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};
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def macroop MUL_P
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{
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rdip t7
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ld t1, ds, [scale, index, base], disp
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muleh rdx, rax, t1
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mulel rax, rax, t1
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};
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#
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# Byte version of one operand signed multiply.
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#
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def macroop IMUL_B_R
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{
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mul1s rax, rax, reg, dataSize="2"
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};
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def macroop IMUL_B_M
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{
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ld t1, ds, [scale, index, base], disp
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mul1s rax, rax, t1, dataSize="2"
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};
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def macroop IMUL_B_P
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{
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rdip t7
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ld t1, ds, [scale, index, base], disp
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mul1s rax, rax, t1, dataSize="2"
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};
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#
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# One operand signed multiply.
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#
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def macroop IMUL_R
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{
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muleh rdx, rax, reg
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mulel rax, rax, reg
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};
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def macroop IMUL_M
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{
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ld t1, ds, [scale, index, base], disp
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muleh rdx, rax, t1
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mulel rax, rax, t1
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};
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def macroop IMUL_P
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{
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rdip t7
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ld t1, ds, [scale, index, base], disp
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muleh rdx, rax, t1
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mulel rax, rax, t1
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};
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#
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#
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# Two operand signed multiply. These should set the CF and OF flags if the
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# Two operand signed multiply. These should set the CF and OF flags if the
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# result is too large for the destination register
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# result is too large for the destination register
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@ -62,33 +156,37 @@ microcode = '''
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def macroop IMUL_R_R
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def macroop IMUL_R_R
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{
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{
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mul1s reg, reg, regm
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mulel reg, reg, regm
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};
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};
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def macroop IMUL_R_M
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def macroop IMUL_R_M
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{
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{
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ld t1, ds, [scale, index, base], disp
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ld t1, ds, [scale, index, base], disp
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mul1s reg, reg, t1
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mulel reg, reg, t1
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};
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};
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def macroop IMUL_R_P
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def macroop IMUL_R_P
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{
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{
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rdip t7
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rdip t7
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ld t1, ds, [scale, index, base], disp
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ld t1, ds, [scale, index, base], disp
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mul1s reg, reg, t1
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mulel reg, reg, t1
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};
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};
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#
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# Three operand signed multiply.
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#
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def macroop IMUL_R_R_I
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def macroop IMUL_R_R_I
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{
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{
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limm t1, imm
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limm t1, imm
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mul1s reg, regm, t1
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mulel reg, regm, t1
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};
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};
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def macroop IMUL_R_M_I
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def macroop IMUL_R_M_I
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{
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{
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limm t1, imm
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limm t1, imm
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ld t2, ds, [scale, index, base], disp
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ld t2, ds, [scale, index, base], disp
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mul1s reg, t2, t1
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mulel reg, t2, t1
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};
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};
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def macroop IMUL_R_P_I
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def macroop IMUL_R_P_I
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@ -96,7 +194,7 @@ def macroop IMUL_R_P_I
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rdip t7
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rdip t7
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limm t1, imm
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limm t1, imm
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ld t2, ds, [0, t0, t7]
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ld t2, ds, [0, t0, t7]
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mul1s reg, t2, t1
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mulel reg, t2, t1
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};
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};
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'''
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'''
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#let {{
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#let {{
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@ -65,6 +65,7 @@ def template MicroRegOpExecute {{
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{
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{
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Fault fault = NoFault;
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Fault fault = NoFault;
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DPRINTF(X86, "The data size is %d\n", dataSize);
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%(op_decl)s;
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%(op_decl)s;
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%(op_rd)s;
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%(op_rd)s;
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@ -327,18 +328,26 @@ let {{
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checkCCFlagBits = "checkCondition(ccFlagBits)"
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checkCCFlagBits = "checkCondition(ccFlagBits)"
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genCCFlagBits = \
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genCCFlagBits = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, op2);"
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, src1, op2);"
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genCCFlagBitsSub = \
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genCCFlagBitsSub = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, ~op2, true);"
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, src1, ~op2, true);"
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genCCFlagBitsLogic = '''
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genCCFlagBitsLogic = '''
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//Don't have genFlags handle the OF or CF bits
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//Don't have genFlags handle the OF or CF bits
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uint64_t mask = CFBit | OFBit;
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uint64_t mask = CFBit | OFBit;
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ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, SrcReg1, op2);
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ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, src1, op2);
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//If a logic microop wants to set these, it wants to set them to 0.
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//If a logic microop wants to set these, it wants to set them to 0.
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ccFlagBits &= ~(CFBit & ext);
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ccFlagBits &= ~(CFBit & ext);
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ccFlagBits &= ~(OFBit & ext);
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ccFlagBits &= ~(OFBit & ext);
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'''
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'''
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regPick = '''
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IntReg src1 = pick(SrcReg1, 0, dataSize);
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IntReg src2 = pick(SrcReg2, 1, dataSize);
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'''
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immPick = '''
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IntReg src1 = pick(SrcReg1, 0, dataSize);
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'''
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# This creates a python representations of a microop which are a cross
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# This creates a python representations of a microop which are a cross
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# product of reg/immediate and flag/no flag versions.
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# product of reg/immediate and flag/no flag versions.
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@ -351,8 +360,8 @@ let {{
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# of the code, one with an integer operand, and one with an immediate
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = matcher.sub("SrcReg2", code)
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regCode = regPick + matcher.sub("src2", code)
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immCode = matcher.sub("imm8", code)
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immCode = immPick + matcher.sub("imm8", code)
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if not cc:
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if not cc:
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condCode = "true"
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condCode = "true"
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@ -360,7 +369,7 @@ let {{
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flagCode = ""
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flagCode = ""
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condCode = checkCCFlagBits
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condCode = checkCCFlagBits
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regFlagCode = matcher.sub("SrcReg2", flagCode)
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regFlagCode = matcher.sub("src2", flagCode)
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immFlagCode = matcher.sub("imm8", flagCode)
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immFlagCode = matcher.sub("imm8", flagCode)
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class RegOpChild(RegOp):
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class RegOpChild(RegOp):
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@ -374,8 +383,9 @@ let {{
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microopClasses[name] = RegOpChild
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
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setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
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setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp",
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flagCode=regFlagCode, condCheck=condCode, elseCode=elseCode);
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regCode, flagCode=regFlagCode,
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condCheck=condCode, elseCode=elseCode);
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class RegOpChildImm(RegOpImm):
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class RegOpChildImm(RegOpImm):
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mnemonic = name + 'i'
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mnemonic = name + 'i'
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microopClasses[name + 'i'] = RegOpChildImm
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microopClasses[name + 'i'] = RegOpChildImm
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setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
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setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
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setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
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setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
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flagCode=immFlagCode, condCheck=condCode, elseCode=elseCode);
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immCode, flagCode=immFlagCode,
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condCheck=condCode, elseCode=elseCode);
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# This has it's own function because Wr ops have implicit destinations
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# This has it's own function because Wr ops have implicit destinations
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def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
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def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
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# of the code, one with an integer operand, and one with an immediate
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = matcher.sub("SrcReg2", code)
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regCode = regPick + matcher.sub("src2", code)
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immCode = matcher.sub("imm8", code)
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immCode = immPick + matcher.sub("imm8", code)
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class RegOpChild(RegOp):
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class RegOpChild(RegOp):
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mnemonic = name
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mnemonic = name
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@ -445,6 +456,7 @@ let {{
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def defineMicroRegOpImm(mnemonic, code):
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def defineMicroRegOpImm(mnemonic, code):
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Name = mnemonic
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Name = mnemonic
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name = mnemonic.lower()
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name = mnemonic.lower()
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code = immPick + code
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class RegOpChild(RegOpImm):
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class RegOpChild(RegOpImm):
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def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
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def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
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setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
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setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, src1 + op2, dataSize)')
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)',
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defineMicroRegOp('Or', '''
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DPRINTF(X86, "src1 = %#x\\n", src1);
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DPRINTF(X86, "op2 = %#x\\n", op2);
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DestReg = merge(DestReg, src1 | op2, dataSize);
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''',
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flagCode = genCCFlagBitsLogic)
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOp('Adc', '''
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defineMicroRegOp('Adc', '''
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CCFlagBits flags = ccFlagBits;
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, SrcReg1 + op2 + flags.CF, dataSize);
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DestReg = merge(DestReg, src1 + op2 + flags.CF, dataSize);
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''')
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''')
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defineMicroRegOp('Sbb', '''
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defineMicroRegOp('Sbb', '''
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CCFlagBits flags = ccFlagBits;
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, SrcReg1 - op2 - flags.CF, dataSize);
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DestReg = merge(DestReg, src1 - op2 - flags.CF, dataSize);
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''', flagCode = genCCFlagBitsSub)
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''', flagCode = genCCFlagBitsSub)
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defineMicroRegOp('And', \
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defineMicroRegOp('And', \
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'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', \
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'DestReg = merge(DestReg, src1 & op2, dataSize)', \
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flagCode = genCCFlagBitsLogic)
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOp('Sub', \
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defineMicroRegOp('Sub', \
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'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', \
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'DestReg = merge(DestReg, src1 - op2, dataSize)', \
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flagCode = genCCFlagBitsSub)
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flagCode = genCCFlagBitsSub)
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defineMicroRegOp('Xor', \
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defineMicroRegOp('Xor', \
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'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', \
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'DestReg = merge(DestReg, src1 ^ op2, dataSize)', \
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flagCode = genCCFlagBitsLogic)
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOp('Mul1s', \
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defineMicroRegOp('Mul1s', '''
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'DestReg = merge(DestReg, DestReg * op2, dataSize)')
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int signPos = (dataSize * 8) / 2 - 1;
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
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IntReg srcVal1 = src1 | (-bits(src1, signPos) << signPos);
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IntReg srcVal2 = op2 | (-bits(src1, signPos) << signPos);
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DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
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''')
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defineMicroRegOp('Mul1u', '''
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int halfSize = (dataSize * 8) / 2;
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IntReg srcVal1 = src1 & mask(halfSize);
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IntReg srcVal2 = op2 & mask(halfSize);
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DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
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''')
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defineMicroRegOp('Mulel', \
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'DestReg = merge(DestReg, src1 * op2, dataSize)')
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defineMicroRegOp('Muleh', '''
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int halfSize = (dataSize * 8) / 2;
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uint64_t src1_h = src1 >> halfSize;
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uint64_t src1_l = src1 & mask(halfSize);
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uint64_t src2_h = op2 >> halfSize;
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uint64_t src2_l = op2 & mask(halfSize);
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uint64_t result =
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((src1_l * src2_h) >> halfSize) +
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((src1_h * src2_l) >> halfSize) +
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src1_h * src2_h;
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DestReg = merge(DestReg, result, dataSize);
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''')
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#
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# HACK HACK HACK HACK - Put src1 in here but make it inert to shut up gcc.
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#
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, src1 * 0 + op2, dataSize)',
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elseCode='DestReg=DestReg;', cc=True)
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elseCode='DestReg=DestReg;', cc=True)
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# Shift instructions
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# Shift instructions
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defineMicroRegOp('Sll', '''
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defineMicroRegOp('Sll', '''
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
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DestReg = merge(DestReg, src1 << shiftAmt, dataSize);
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''')
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''')
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defineMicroRegOp('Srl', '''
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defineMicroRegOp('Srl', '''
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||||
|
@ -492,7 +535,7 @@ let {{
|
||||||
// is not defined in the C/C++ standard, we have to mask them out
|
// is not defined in the C/C++ standard, we have to mask them out
|
||||||
// to be sure they're zero.
|
// to be sure they're zero.
|
||||||
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
|
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
|
||||||
DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
|
DestReg = merge(DestReg, (src1 >> shiftAmt) & logicalMask, dataSize);
|
||||||
''')
|
''')
|
||||||
defineMicroRegOp('Sra', '''
|
defineMicroRegOp('Sra', '''
|
||||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||||
|
@ -501,15 +544,15 @@ let {{
|
||||||
// them manually to be sure.
|
// them manually to be sure.
|
||||||
uint64_t arithMask =
|
uint64_t arithMask =
|
||||||
-bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
|
-bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
|
||||||
DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) | arithMask, dataSize);
|
DestReg = merge(DestReg, (src1 >> shiftAmt) | arithMask, dataSize);
|
||||||
''')
|
''')
|
||||||
defineMicroRegOp('Ror', '''
|
defineMicroRegOp('Ror', '''
|
||||||
uint8_t shiftAmt =
|
uint8_t shiftAmt =
|
||||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||||
if(shiftAmt)
|
if(shiftAmt)
|
||||||
{
|
{
|
||||||
uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
|
uint64_t top = src1 << (dataSize * 8 - shiftAmt);
|
||||||
uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt);
|
uint64_t bottom = bits(src1, dataSize * 8, shiftAmt);
|
||||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
@ -523,8 +566,8 @@ let {{
|
||||||
CCFlagBits flags = ccFlagBits;
|
CCFlagBits flags = ccFlagBits;
|
||||||
uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
|
uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
|
||||||
if(shiftAmt > 1)
|
if(shiftAmt > 1)
|
||||||
top |= SrcReg1 << (dataSize * 8 - shiftAmt - 1);
|
top |= src1 << (dataSize * 8 - shiftAmt - 1);
|
||||||
uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt);
|
uint64_t bottom = bits(src1, dataSize * 8, shiftAmt);
|
||||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
@ -535,9 +578,9 @@ let {{
|
||||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||||
if(shiftAmt)
|
if(shiftAmt)
|
||||||
{
|
{
|
||||||
uint64_t top = SrcReg1 << shiftAmt;
|
uint64_t top = src1 << shiftAmt;
|
||||||
uint64_t bottom =
|
uint64_t bottom =
|
||||||
bits(SrcReg1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
|
bits(src1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
|
||||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
@ -549,11 +592,11 @@ let {{
|
||||||
if(shiftAmt)
|
if(shiftAmt)
|
||||||
{
|
{
|
||||||
CCFlagBits flags = ccFlagBits;
|
CCFlagBits flags = ccFlagBits;
|
||||||
uint64_t top = SrcReg1 << shiftAmt;
|
uint64_t top = src1 << shiftAmt;
|
||||||
uint64_t bottom = flags.CF << (shiftAmt - 1);
|
uint64_t bottom = flags.CF << (shiftAmt - 1);
|
||||||
if(shiftAmt > 1)
|
if(shiftAmt > 1)
|
||||||
bottom |=
|
bottom |=
|
||||||
bits(SrcReg1, dataSize * 8 - 1,
|
bits(src1, dataSize * 8 - 1,
|
||||||
dataSize * 8 - shiftAmt + 1);
|
dataSize * 8 - shiftAmt + 1);
|
||||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||||
}
|
}
|
||||||
|
@ -561,15 +604,15 @@ let {{
|
||||||
DestReg = DestReg;
|
DestReg = DestReg;
|
||||||
''')
|
''')
|
||||||
|
|
||||||
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
|
defineMicroRegOpWr('Wrip', 'RIP = src1 + op2', elseCode="RIP = RIP;")
|
||||||
|
|
||||||
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
|
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
|
||||||
|
|
||||||
defineMicroRegOpImm('Sext', '''
|
defineMicroRegOpImm('Sext', '''
|
||||||
IntReg val = SrcReg1;
|
IntReg val = src1;
|
||||||
int sign_bit = bits(val, imm8-1, imm8-1);
|
int sign_bit = bits(val, imm8-1, imm8-1);
|
||||||
val = sign_bit ? (val | ~mask(imm8)) : val;
|
val = sign_bit ? (val | ~mask(imm8)) : val;
|
||||||
DestReg = merge(DestReg, val, dataSize);''')
|
DestReg = merge(DestReg, val, dataSize);''')
|
||||||
|
|
||||||
defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
|
defineMicroRegOpImm('Zext', 'DestReg = bits(src1, imm8-1, 0);')
|
||||||
}};
|
}};
|
||||||
|
|
Loading…
Reference in a new issue