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Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.

Browse source 
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used.  These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
    Add in option USE_CHECKER to allow for not compiling in checker code.  The checker is enabled through this option instead of through the CPU_MODELS list.  However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
    Name change for DetailedCPU to DetailedO3CPU.  Also include option for max tick.
src/base/traceflags.py:
    Add in O3CPU trace flag.
src/cpu/SConscript:
    Rename AlphaFullCPU to AlphaO3CPU.

    Only include checker sources if they're necessary.  Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
    Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
    Also #ifdef the checker code so it doesn't need to be included if it's not selected.

--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
This commit is contained in:
Kevin Lim 2006-06-16 17:08:47 -04:00
parent 720e6c4145
commit baba18ab92
39 changed files with 272 additions and 212 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
SConstruct
View file

@ -260,8 +260,8 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
# Define the universe of supported CPU models # Define the universe of supported CPU models
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU', env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
'FullCPU', 'AlphaFullCPU', 'FullCPU', 'AlphaO3CPU',
'OzoneSimpleCPU', 'OzoneCPU', 'CheckerCPU'] 'OzoneSimpleCPU', 'OzoneCPU']
# Sticky options get saved in the options file so they persist from # Sticky options get saved in the options file so they persist from
# one invocation to the next (unless overridden, in which case the new # one invocation to the next (unless overridden, in which case the new
@ -289,6 +289,7 @@ sticky_opts.AddOptions(
False), False),
BoolOption('USE_MYSQL', 'Use MySQL for stats output', have_mysql), BoolOption('USE_MYSQL', 'Use MySQL for stats output', have_mysql),
BoolOption('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv), BoolOption('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv),
BoolOption('USE_CHECKER', 'Use checker for detailed CPU models', False),
('CC', 'C compiler', os.environ.get('CC', env['CC'])), ('CC', 'C compiler', os.environ.get('CC', env['CC'])),
('CXX', 'C++ compiler', os.environ.get('CXX', env['CXX'])), ('CXX', 'C++ compiler', os.environ.get('CXX', env['CXX'])),
BoolOption('BATCH', 'Use batch pool for build and tests', False), BoolOption('BATCH', 'Use batch pool for build and tests', False),
@ -303,7 +304,8 @@ nonsticky_opts.AddOptions(
# These options get exported to #defines in config/*.hh (see m5/SConscript). # These options get exported to #defines in config/*.hh (see m5/SConscript).
env.ExportOptions = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \ env.ExportOptions = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \
'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP'] 'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP', \
'USE_CHECKER']
# Define a handy 'no-op' action # Define a handy 'no-op' action
def no_action(target, source, env): def no_action(target, source, env):
@ -470,6 +472,10 @@ for build_path in build_paths:
env.ParseConfig(mysql_config_libs) env.ParseConfig(mysql_config_libs)
env.ParseConfig(mysql_config_include) env.ParseConfig(mysql_config_include)
# Check if the Checker is being used. If so append it to env['CPU_MODELS']
if env['USE_CHECKER']:
env['CPU_MODELS'].append('CheckerCPU')
# Save sticky option settings back to current options file # Save sticky option settings back to current options file
sticky_opts.Save(current_opts_file, env) sticky_opts.Save(current_opts_file, env)

8
configs/test/test.py
View file

@ -14,6 +14,7 @@ parser = optparse.OptionParser(option_list=m5.standardOptions)
parser.add_option("-c", "--cmd", default="hello") parser.add_option("-c", "--cmd", default="hello")
parser.add_option("-t", "--timing", action="store_true") parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-f", "--full", action="store_true") parser.add_option("-f", "--full", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
(options, args) = parser.parse_args() (options, args) = parser.parse_args()
@ -34,7 +35,7 @@ mem = PhysicalMemory()
if options.timing: if options.timing:
cpu = TimingSimpleCPU() cpu = TimingSimpleCPU()
elif options.full: elif options.full:
cpu = DetailedCPU() cpu = DetailedO3CPU()
else: else:
cpu = AtomicSimpleCPU() cpu = AtomicSimpleCPU()
cpu.workload = process cpu.workload = process
@ -48,7 +49,10 @@ root = Root(system = system)
m5.instantiate(root) m5.instantiate(root)
# simulate until program terminates # simulate until program terminates
exit_event = m5.simulate() if options.maxtick:
exit_event = m5.simulate(options.maxtick)
else:
exit_event = m5.simulate()
print 'Exiting @', m5.curTick(), 'because', exit_event.getCause() print 'Exiting @', m5.curTick(), 'because', exit_event.getCause()

1
src/base/traceflags.py
View file

@ -115,6 +115,7 @@ baseFlags = [
'MSHR', 'MSHR',
'Mbox', 'Mbox',
'MemDepUnit', 'MemDepUnit',
'O3CPU',
'OzoneCPU', 'OzoneCPU',
'FE', 'FE',
'IBE', 'IBE',

25
src/cpu/SConscript
View file

@ -92,6 +92,10 @@ env.Command('static_inst_exec_sigs.hh', models_db,
Action(gen_cpu_exec_signatures, gen_sigs_string, Action(gen_cpu_exec_signatures, gen_sigs_string,
varlist = ['CPU_MODELS'])) varlist = ['CPU_MODELS']))
# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
# and one of these are not being used.
CheckerSupportedCPUList = ['AlphaO3CPU', 'OzoneCPU']
################################################################# #################################################################
# #
# Include CPU-model-specific files based on set of models # Include CPU-model-specific files based on set of models
@ -116,7 +120,7 @@ if need_simple_base:
if 'FastCPU' in env['CPU_MODELS']: if 'FastCPU' in env['CPU_MODELS']:
sources += Split('fast/cpu.cc') sources += Split('fast/cpu.cc')
if 'AlphaFullCPU' in env['CPU_MODELS']: if 'AlphaO3CPU' in env['CPU_MODELS']:
sources += Split(''' sources += Split('''
base_dyn_inst.cc base_dyn_inst.cc
o3/2bit_local_pred.cc o3/2bit_local_pred.cc
@ -144,6 +148,8 @@ if 'AlphaFullCPU' in env['CPU_MODELS']:
o3/store_set.cc o3/store_set.cc
o3/tournament_pred.cc o3/tournament_pred.cc
''') ''')
if 'CheckerCPU' in env['CPU_MODELS']:
sources += Split('checker/o3_builder.cc')
if 'OzoneSimpleCPU' in env['CPU_MODELS']: if 'OzoneSimpleCPU' in env['CPU_MODELS']:
sources += Split(''' sources += Split('''
@ -155,6 +161,8 @@ if 'OzoneSimpleCPU' in env['CPU_MODELS']:
ozone/inst_queue.cc ozone/inst_queue.cc
ozone/rename_table.cc ozone/rename_table.cc
''') ''')
if 'CheckerCPU' in env['CPU_MODELS']:
sources += Split('checker/ozone_builder.cc')
if 'OzoneCPU' in env['CPU_MODELS']: if 'OzoneCPU' in env['CPU_MODELS']:
sources += Split(''' sources += Split('''
@ -164,10 +172,17 @@ if 'OzoneCPU' in env['CPU_MODELS']:
''') ''')
if 'CheckerCPU' in env['CPU_MODELS']: if 'CheckerCPU' in env['CPU_MODELS']:
sources += Split(''' sources += Split('checker/cpu.cc')
checker/cpu.cc checker_supports = False
checker/o3_cpu_builder.cc for i in CheckerSupportedCPUList:
''') if i in env['CPU_MODELS']:
checker_supports = True
if not checker_supports:
print "Checker only supports CPU models %s, please " \
"set USE_CHECKER=False or use one of those CPU models" \
% CheckerSupportedCPUList
Exit(1)
# FullCPU sources are included from m5/SConscript since they're not # FullCPU sources are included from m5/SConscript since they're not
# below this point in the file hierarchy. # below this point in the file hierarchy.

4
src/cpu/base_dyn_inst.cc
View file

@ -71,8 +71,8 @@ my_hash_t thishash;
template <class Impl> template <class Impl>
BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC, BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num, Addr pred_PC, InstSeqNum seq_num,
FullCPU *cpu) ImplCPU *cpu)
: staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/ : staticInst(machInst), traceData(NULL), cpu(cpu)
{ {
seqNum = seq_num; seqNum = seq_num;

10
src/cpu/base_dyn_inst.hh
View file

@ -59,8 +59,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
{ {
public: public:
// Typedef for the CPU. // Typedef for the CPU.
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::CPUType ImplCPU;
typedef typename FullCPU::ImplState ImplState; typedef typename ImplCPU::ImplState ImplState;
// Binary machine instruction type. // Binary machine instruction type.
typedef TheISA::MachInst MachInst; typedef TheISA::MachInst MachInst;
@ -165,8 +165,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** How many source registers are ready. */ /** How many source registers are ready. */
unsigned readyRegs; unsigned readyRegs;
/** Pointer to the FullCPU object. */ /** Pointer to the Impl's CPU object. */
FullCPU *cpu; ImplCPU *cpu;
/** Pointer to the thread state. */ /** Pointer to the thread state. */
ImplState *thread; ImplState *thread;
@ -239,7 +239,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
* @param cpu Pointer to the instruction's CPU. * @param cpu Pointer to the instruction's CPU.
*/ */
BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
FullCPU *cpu); ImplCPU *cpu);
/** BaseDynInst constructor given a StaticInst pointer. /** BaseDynInst constructor given a StaticInst pointer.
* @param _staticInst The StaticInst for this BaseDynInst. * @param _staticInst The StaticInst for this BaseDynInst.

0
src/cpu/checker/o3_cpu_builder.cc → src/cpu/checker/o3_builder.cc
View file

0
src/cpu/checker/cpu_builder.cc → src/cpu/checker/ozone_builder.cc
View file

2
src/cpu/cpu_models.py
View file

@ -67,7 +67,7 @@ CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
CpuModel('FullCPU', 'full_cpu_exec.cc', CpuModel('FullCPU', 'full_cpu_exec.cc',
'#include "encumbered/cpu/full/dyn_inst.hh"', '#include "encumbered/cpu/full/dyn_inst.hh"',
{ 'CPU_exec_context': 'DynInst' }) { 'CPU_exec_context': 'DynInst' })
CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc', CpuModel('AlphaO3CPU', 'alpha_o3_exec.cc',
'#include "cpu/o3/alpha_dyn_inst.hh"', '#include "cpu/o3/alpha_dyn_inst.hh"',
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' }) { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc', CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',

4
src/cpu/o3/alpha_cpu.cc
View file

@ -32,7 +32,7 @@
#include "cpu/o3/alpha_cpu_impl.hh" #include "cpu/o3/alpha_cpu_impl.hh"
#include "cpu/o3/alpha_dyn_inst.hh" #include "cpu/o3/alpha_dyn_inst.hh"
// Force instantiation of AlphaFullCPU for all the implemntations that are // Force instantiation of AlphaO3CPU for all the implemntations that are
// needed. Consider merging this and alpha_dyn_inst.cc, and maybe all // needed. Consider merging this and alpha_dyn_inst.cc, and maybe all
// classes that depend on a certain impl, into one file (alpha_impl.cc?). // classes that depend on a certain impl, into one file (alpha_impl.cc?).
template class AlphaFullCPU<AlphaSimpleImpl>; template class AlphaO3CPU<AlphaSimpleImpl>;

14
src/cpu/o3/alpha_cpu.hh
View file

@ -44,7 +44,7 @@ namespace Kernel {
class TranslatingPort; class TranslatingPort;
/** /**
* AlphaFullCPU class. Derives from the FullO3CPU class, and * AlphaO3CPU class. Derives from the FullO3CPU class, and
* implements all ISA and implementation specific functions of the * implements all ISA and implementation specific functions of the
* CPU. This is the CPU class that is used for the SimObjects, and is * CPU. This is the CPU class that is used for the SimObjects, and is
* what is given to the DynInsts. Most of its state exists in the * what is given to the DynInsts. Most of its state exists in the
@ -52,7 +52,7 @@ class TranslatingPort;
* functionality. * functionality.
*/ */
template <class Impl> template <class Impl>
class AlphaFullCPU : public FullO3CPU<Impl> class AlphaO3CPU : public FullO3CPU<Impl>
{ {
protected: protected:
typedef TheISA::IntReg IntReg; typedef TheISA::IntReg IntReg;
@ -67,17 +67,17 @@ class AlphaFullCPU : public FullO3CPU<Impl>
typedef O3ThreadState<Impl> Thread; typedef O3ThreadState<Impl> Thread;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
/** Constructs an AlphaFullCPU with the given parameters. */ /** Constructs an AlphaO3CPU with the given parameters. */
AlphaFullCPU(Params *params); AlphaO3CPU(Params *params);
/** /**
* Derived ThreadContext class for use with the AlphaFullCPU. It * Derived ThreadContext class for use with the AlphaO3CPU. It
* provides the interface for any external objects to access a * provides the interface for any external objects to access a
* single thread's state and some general CPU state. Any time * single thread's state and some general CPU state. Any time
* external objects try to update state through this interface, * external objects try to update state through this interface,
* the CPU will create an event to squash all in-flight * the CPU will create an event to squash all in-flight
* instructions in order to ensure state is maintained correctly. * instructions in order to ensure state is maintained correctly.
* It must be defined specifically for the AlphaFullCPU because * It must be defined specifically for the AlphaO3CPU because
* not all architectural state is located within the O3ThreadState * not all architectural state is located within the O3ThreadState
* (such as the commit PC, and registers), and specific actions * (such as the commit PC, and registers), and specific actions
* must be taken when using this interface (such as squashing all * must be taken when using this interface (such as squashing all
@ -87,7 +87,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
{ {
public: public:
/** Pointer to the CPU. */ /** Pointer to the CPU. */
AlphaFullCPU<Impl> *cpu; AlphaO3CPU<Impl> *cpu;
/** Pointer to the thread state that this TC corrseponds to. */ /** Pointer to the thread state that this TC corrseponds to. */
O3ThreadState<Impl> *thread; O3ThreadState<Impl> *thread;

22
src/cpu/o3/alpha_cpu_builder.cc
View file

@ -37,15 +37,15 @@
#include "cpu/o3/fu_pool.hh" #include "cpu/o3/fu_pool.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl> class DerivAlphaO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
{ {
public: public:
DerivAlphaFullCPU(AlphaSimpleParams *p) DerivAlphaO3CPU(AlphaSimpleParams *p)
: AlphaFullCPU<AlphaSimpleImpl>(p) : AlphaO3CPU<AlphaSimpleImpl>(p)
{ } { }
}; };
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
Param<int> clock; Param<int> clock;
Param<int> numThreads; Param<int> numThreads;
@ -144,9 +144,9 @@ Param<bool> defer_registration;
Param<bool> function_trace; Param<bool> function_trace;
Param<Tick> function_trace_start; Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
INIT_PARAM(clock, "clock speed"), INIT_PARAM(clock, "clock speed"),
INIT_PARAM(numThreads, "number of HW thread contexts"), INIT_PARAM(numThreads, "number of HW thread contexts"),
@ -261,11 +261,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(function_trace, "Enable function trace"), INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace") INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) END_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
CREATE_SIM_OBJECT(DerivAlphaFullCPU) CREATE_SIM_OBJECT(DerivAlphaO3CPU)
{ {
DerivAlphaFullCPU *cpu; DerivAlphaO3CPU *cpu;
#if FULL_SYSTEM #if FULL_SYSTEM
// Full-system only supports a single thread for the moment. // Full-system only supports a single thread for the moment.
@ -386,10 +386,10 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
params->functionTrace = function_trace; params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start; params->functionTraceStart = function_trace_start;
cpu = new DerivAlphaFullCPU(params); cpu = new DerivAlphaO3CPU(params);
return cpu; return cpu;
} }
REGISTER_SIM_OBJECT("DerivAlphaFullCPU", DerivAlphaFullCPU) REGISTER_SIM_OBJECT("DerivAlphaO3CPU", DerivAlphaO3CPU)

140
src/cpu/o3/alpha_cpu_impl.hh
View file

@ -28,6 +28,8 @@
* Authors: Kevin Lim * Authors: Kevin Lim
*/ */
#include "config/use_checker.hh"
#include "arch/alpha/faults.hh" #include "arch/alpha/faults.hh"
#include "base/cprintf.hh" #include "base/cprintf.hh"
#include "base/statistics.hh" #include "base/statistics.hh"
@ -53,14 +55,14 @@
using namespace TheISA; using namespace TheISA;
template <class Impl> template <class Impl>
AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
#if FULL_SYSTEM #if FULL_SYSTEM
: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb) : FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
#else #else
: FullO3CPU<Impl>(params) : FullO3CPU<Impl>(params)
#endif #endif
{ {
DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n"); DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
// Setup any thread state. // Setup any thread state.
this->thread.resize(this->numThreads); this->thread.resize(this->numThreads);
@ -73,7 +75,7 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
this->thread[i]->setStatus(ThreadContext::Suspended); this->thread[i]->setStatus(ThreadContext::Suspended);
#else #else
if (i < params->workload.size()) { if (i < params->workload.size()) {
DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x", DPRINTF(O3CPU, "Workload[%i] process is %#x",
i, this->thread[i]); i, this->thread[i]);
this->thread[i] = new Thread(this, i, params->workload[i], this->thread[i] = new Thread(this, i, params->workload[i],
i, params->mem); i, params->mem);
@ -110,14 +112,16 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
// Setup the TC that will serve as the interface to the threads/CPU. // Setup the TC that will serve as the interface to the threads/CPU.
AlphaTC *alpha_tc = new AlphaTC; AlphaTC *alpha_tc = new AlphaTC;
tc = alpha_tc;
// If we're using a checker, then the TC should be the // If we're using a checker, then the TC should be the
// CheckerThreadContext. // CheckerThreadContext.
#if USE_CHECKER
if (params->checker) { if (params->checker) {
tc = new CheckerThreadContext<AlphaTC>( tc = new CheckerThreadContext<AlphaTC>(
alpha_tc, this->checker); alpha_tc, this->checker);
} else {
tc = alpha_tc;
} }
#endif
alpha_tc->cpu = this; alpha_tc->cpu = this;
alpha_tc->thread = this->thread[i]; alpha_tc->thread = this->thread[i];
@ -172,7 +176,7 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::regStats() AlphaO3CPU<Impl>::regStats()
{ {
// Register stats for everything that has stats. // Register stats for everything that has stats.
this->fullCPURegStats(); this->fullCPURegStats();
@ -186,7 +190,7 @@ AlphaFullCPU<Impl>::regStats()
#if FULL_SYSTEM #if FULL_SYSTEM
template <class Impl> template <class Impl>
VirtualPort * VirtualPort *
AlphaFullCPU<Impl>::AlphaTC::getVirtPort(ThreadContext *src_tc) AlphaO3CPU<Impl>::AlphaTC::getVirtPort(ThreadContext *src_tc)
{ {
if (!src_tc) if (!src_tc)
return thread->getVirtPort(); return thread->getVirtPort();
@ -203,7 +207,7 @@ AlphaFullCPU<Impl>::AlphaTC::getVirtPort(ThreadContext *src_tc)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile() AlphaO3CPU<Impl>::AlphaTC::dumpFuncProfile()
{ {
// Currently not supported // Currently not supported
} }
@ -211,7 +215,7 @@ AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile()
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context) AlphaO3CPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
{ {
// some things should already be set up // some things should already be set up
#if FULL_SYSTEM #if FULL_SYSTEM
@ -253,7 +257,7 @@ AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
#if FULL_SYSTEM #if FULL_SYSTEM
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::delVirtPort(VirtualPort *vp) AlphaO3CPU<Impl>::AlphaTC::delVirtPort(VirtualPort *vp)
{ {
delete vp->getPeer(); delete vp->getPeer();
delete vp; delete vp;
@ -262,9 +266,9 @@ AlphaFullCPU<Impl>::AlphaTC::delVirtPort(VirtualPort *vp)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::activate(int delay) AlphaO3CPU<Impl>::AlphaTC::activate(int delay)
{ {
DPRINTF(FullCPU, "Calling activate on AlphaTC\n"); DPRINTF(O3CPU, "Calling activate on AlphaTC\n");
if (thread->status() == ThreadContext::Active) if (thread->status() == ThreadContext::Active)
return; return;
@ -286,9 +290,9 @@ AlphaFullCPU<Impl>::AlphaTC::activate(int delay)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::suspend() AlphaO3CPU<Impl>::AlphaTC::suspend()
{ {
DPRINTF(FullCPU, "Calling suspend on AlphaTC\n"); DPRINTF(O3CPU, "Calling suspend on AlphaTC\n");
if (thread->status() == ThreadContext::Suspended) if (thread->status() == ThreadContext::Suspended)
return; return;
@ -312,9 +316,9 @@ AlphaFullCPU<Impl>::AlphaTC::suspend()
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::deallocate() AlphaO3CPU<Impl>::AlphaTC::deallocate()
{ {
DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n"); DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n");
if (thread->status() == ThreadContext::Unallocated) if (thread->status() == ThreadContext::Unallocated)
return; return;
@ -325,9 +329,9 @@ AlphaFullCPU<Impl>::AlphaTC::deallocate()
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::halt() AlphaO3CPU<Impl>::AlphaTC::halt()
{ {
DPRINTF(FullCPU, "Calling halt on AlphaTC\n"); DPRINTF(O3CPU, "Calling halt on AlphaTC\n");
if (thread->status() == ThreadContext::Halted) if (thread->status() == ThreadContext::Halted)
return; return;
@ -338,7 +342,7 @@ AlphaFullCPU<Impl>::AlphaTC::halt()
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::regStats(const std::string &name) AlphaO3CPU<Impl>::AlphaTC::regStats(const std::string &name)
{ {
#if FULL_SYSTEM #if FULL_SYSTEM
thread->kernelStats = new Kernel::Statistics(cpu->system); thread->kernelStats = new Kernel::Statistics(cpu->system);
@ -348,7 +352,7 @@ AlphaFullCPU<Impl>::AlphaTC::regStats(const std::string &name)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::serialize(std::ostream &os) AlphaO3CPU<Impl>::AlphaTC::serialize(std::ostream &os)
{ {
#if FULL_SYSTEM #if FULL_SYSTEM
if (thread->kernelStats) if (thread->kernelStats)
@ -359,7 +363,7 @@ AlphaFullCPU<Impl>::AlphaTC::serialize(std::ostream &os)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string &section) AlphaO3CPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string &section)
{ {
#if FULL_SYSTEM #if FULL_SYSTEM
if (thread->kernelStats) if (thread->kernelStats)
@ -371,46 +375,46 @@ AlphaFullCPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string &sect
#if FULL_SYSTEM #if FULL_SYSTEM
template <class Impl> template <class Impl>
EndQuiesceEvent * EndQuiesceEvent *
AlphaFullCPU<Impl>::AlphaTC::getQuiesceEvent() AlphaO3CPU<Impl>::AlphaTC::getQuiesceEvent()
{ {
return thread->quiesceEvent; return thread->quiesceEvent;
} }
template <class Impl> template <class Impl>
Tick Tick
AlphaFullCPU<Impl>::AlphaTC::readLastActivate() AlphaO3CPU<Impl>::AlphaTC::readLastActivate()
{ {
return thread->lastActivate; return thread->lastActivate;
} }
template <class Impl> template <class Impl>
Tick Tick
AlphaFullCPU<Impl>::AlphaTC::readLastSuspend() AlphaO3CPU<Impl>::AlphaTC::readLastSuspend()
{ {
return thread->lastSuspend; return thread->lastSuspend;
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::profileClear() AlphaO3CPU<Impl>::AlphaTC::profileClear()
{} {}
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::profileSample() AlphaO3CPU<Impl>::AlphaTC::profileSample()
{} {}
#endif #endif
template <class Impl> template <class Impl>
TheISA::MachInst TheISA::MachInst
AlphaFullCPU<Impl>::AlphaTC:: getInst() AlphaO3CPU<Impl>::AlphaTC:: getInst()
{ {
return thread->getInst(); return thread->getInst();
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc) AlphaO3CPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
{ {
// This function will mess things up unless the ROB is empty and // This function will mess things up unless the ROB is empty and
// there are no instructions in the pipeline. // there are no instructions in the pipeline.
@ -421,7 +425,7 @@ AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
renamed_reg = cpu->renameMap[tid].lookup(i); renamed_reg = cpu->renameMap[tid].lookup(i);
DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, " DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
"now has data %lli.\n", "now has data %lli.\n",
renamed_reg, cpu->readIntReg(renamed_reg), renamed_reg, cpu->readIntReg(renamed_reg),
tc->readIntReg(i)); tc->readIntReg(i));
@ -449,19 +453,19 @@ AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::clearArchRegs() AlphaO3CPU<Impl>::AlphaTC::clearArchRegs()
{} {}
template <class Impl> template <class Impl>
uint64_t uint64_t
AlphaFullCPU<Impl>::AlphaTC::readIntReg(int reg_idx) AlphaO3CPU<Impl>::AlphaTC::readIntReg(int reg_idx)
{ {
return cpu->readArchIntReg(reg_idx, thread->readTid()); return cpu->readArchIntReg(reg_idx, thread->readTid());
} }
template <class Impl> template <class Impl>
FloatReg FloatReg
AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width) AlphaO3CPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width)
{ {
switch(width) { switch(width) {
case 32: case 32:
@ -476,14 +480,14 @@ AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width)
template <class Impl> template <class Impl>
FloatReg FloatReg
AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx) AlphaO3CPU<Impl>::AlphaTC::readFloatReg(int reg_idx)
{ {
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
} }
template <class Impl> template <class Impl>
FloatRegBits FloatRegBits
AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width) AlphaO3CPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width)
{ {
DPRINTF(Fault, "Reading floatint register through the TC!\n"); DPRINTF(Fault, "Reading floatint register through the TC!\n");
return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
@ -491,14 +495,14 @@ AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width)
template <class Impl> template <class Impl>
FloatRegBits FloatRegBits
AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx) AlphaO3CPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx)
{ {
return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val) AlphaO3CPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val)
{ {
cpu->setArchIntReg(reg_idx, val, thread->readTid()); cpu->setArchIntReg(reg_idx, val, thread->readTid());
@ -510,7 +514,7 @@ AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) AlphaO3CPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width)
{ {
switch(width) { switch(width) {
case 32: case 32:
@ -529,7 +533,7 @@ AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val) AlphaO3CPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val)
{ {
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
@ -540,7 +544,7 @@ AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, AlphaO3CPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val,
int width) int width)
{ {
DPRINTF(Fault, "Setting floatint register through the TC!\n"); DPRINTF(Fault, "Setting floatint register through the TC!\n");
@ -554,7 +558,7 @@ AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val,
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) AlphaO3CPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val)
{ {
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
@ -566,7 +570,7 @@ AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val) AlphaO3CPU<Impl>::AlphaTC::setPC(uint64_t val)
{ {
cpu->setPC(val, thread->readTid()); cpu->setPC(val, thread->readTid());
@ -578,7 +582,7 @@ AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val) AlphaO3CPU<Impl>::AlphaTC::setNextPC(uint64_t val)
{ {
cpu->setNextPC(val, thread->readTid()); cpu->setNextPC(val, thread->readTid());
@ -590,7 +594,7 @@ AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val)
template <class Impl> template <class Impl>
Fault Fault
AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) AlphaO3CPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val)
{ {
Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
@ -604,8 +608,8 @@ AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val)
template <class Impl> template <class Impl>
Fault Fault
AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg, AlphaO3CPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg,
const MiscReg &val) const MiscReg &val)
{ {
Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
thread->readTid()); thread->readTid());
@ -622,21 +626,21 @@ AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg,
template <class Impl> template <class Impl>
TheISA::IntReg TheISA::IntReg
AlphaFullCPU<Impl>::AlphaTC::getSyscallArg(int i) AlphaO3CPU<Impl>::AlphaTC::getSyscallArg(int i)
{ {
return cpu->getSyscallArg(i, thread->readTid()); return cpu->getSyscallArg(i, thread->readTid());
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val) AlphaO3CPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val)
{ {
cpu->setSyscallArg(i, val, thread->readTid()); cpu->setSyscallArg(i, val, thread->readTid());
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value) AlphaO3CPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value)
{ {
cpu->setSyscallReturn(return_value, thread->readTid()); cpu->setSyscallReturn(return_value, thread->readTid());
} }
@ -645,37 +649,37 @@ AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value)
template <class Impl> template <class Impl>
MiscReg MiscReg
AlphaFullCPU<Impl>::readMiscReg(int misc_reg, unsigned tid) AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
{ {
return this->regFile.readMiscReg(misc_reg, tid); return this->regFile.readMiscReg(misc_reg, tid);
} }
template <class Impl> template <class Impl>
MiscReg MiscReg
AlphaFullCPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault, AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
unsigned tid) unsigned tid)
{ {
return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
} }
template <class Impl> template <class Impl>
Fault Fault
AlphaFullCPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
{ {
return this->regFile.setMiscReg(misc_reg, val, tid); return this->regFile.setMiscReg(misc_reg, val, tid);
} }
template <class Impl> template <class Impl>
Fault Fault
AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
unsigned tid) unsigned tid)
{ {
return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::squashFromTC(unsigned tid) AlphaO3CPU<Impl>::squashFromTC(unsigned tid)
{ {
this->thread[tid]->inSyscall = true; this->thread[tid]->inSyscall = true;
this->commit.generateTCEvent(tid); this->commit.generateTCEvent(tid);
@ -685,7 +689,7 @@ AlphaFullCPU<Impl>::squashFromTC(unsigned tid)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::post_interrupt(int int_num, int index) AlphaO3CPU<Impl>::post_interrupt(int int_num, int index)
{ {
BaseCPU::post_interrupt(int_num, index); BaseCPU::post_interrupt(int_num, index);
@ -697,21 +701,21 @@ AlphaFullCPU<Impl>::post_interrupt(int int_num, int index)
template <class Impl> template <class Impl>
int int
AlphaFullCPU<Impl>::readIntrFlag() AlphaO3CPU<Impl>::readIntrFlag()
{ {
return this->regFile.readIntrFlag(); return this->regFile.readIntrFlag();
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::setIntrFlag(int val) AlphaO3CPU<Impl>::setIntrFlag(int val)
{ {
this->regFile.setIntrFlag(val); this->regFile.setIntrFlag(val);
} }
template <class Impl> template <class Impl>
Fault Fault
AlphaFullCPU<Impl>::hwrei(unsigned tid) AlphaO3CPU<Impl>::hwrei(unsigned tid)
{ {
// Need to clear the lock flag upon returning from an interrupt. // Need to clear the lock flag upon returning from an interrupt.
this->lockFlag = false; this->lockFlag = false;
@ -726,7 +730,7 @@ AlphaFullCPU<Impl>::hwrei(unsigned tid)
template <class Impl> template <class Impl>
bool bool
AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid) AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
{ {
if (this->thread[tid]->kernelStats) if (this->thread[tid]->kernelStats)
this->thread[tid]->kernelStats->callpal(palFunc, this->thread[tid]->kernelStats->callpal(palFunc,
@ -751,7 +755,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid) AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
{ {
// Pass the thread's TC into the invoke method. // Pass the thread's TC into the invoke method.
fault->invoke(this->threadContexts[tid]); fault->invoke(this->threadContexts[tid]);
@ -759,7 +763,7 @@ AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::processInterrupts() AlphaO3CPU<Impl>::processInterrupts()
{ {
// Check for interrupts here. For now can copy the code that // Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0 // exists within isa_fullsys_traits.hh. Also assume that thread 0
@ -805,10 +809,12 @@ AlphaFullCPU<Impl>::processInterrupts()
this->setMiscReg(IPR_ISR, summary, 0); this->setMiscReg(IPR_ISR, summary, 0);
this->setMiscReg(IPR_INTID, ipl, 0); this->setMiscReg(IPR_INTID, ipl, 0);
// Checker needs to know these two registers were updated. // Checker needs to know these two registers were updated.
#if USE_CHECKER
if (this->checker) { if (this->checker) {
this->checker->threadBase()->setMiscReg(IPR_ISR, summary); this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
} }
#endif
this->trap(Fault(new InterruptFault), 0); this->trap(Fault(new InterruptFault), 0);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
this->readMiscReg(IPR_IPLR, 0), ipl, summary); this->readMiscReg(IPR_IPLR, 0), ipl, summary);
@ -821,9 +827,9 @@ AlphaFullCPU<Impl>::processInterrupts()
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::syscall(int64_t callnum, int tid) AlphaO3CPU<Impl>::syscall(int64_t callnum, int tid)
{ {
DPRINTF(FullCPU, "AlphaFullCPU: [tid:%i] Executing syscall().\n\n", tid); DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
DPRINTF(Activity,"Activity: syscall() called.\n"); DPRINTF(Activity,"Activity: syscall() called.\n");
@ -841,21 +847,21 @@ AlphaFullCPU<Impl>::syscall(int64_t callnum, int tid)
template <class Impl> template <class Impl>
TheISA::IntReg TheISA::IntReg
AlphaFullCPU<Impl>::getSyscallArg(int i, int tid) AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
{ {
return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::setSyscallArg(int i, IntReg val, int tid) AlphaO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
{ {
this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
} }
template <class Impl> template <class Impl>
void void
AlphaFullCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
{ {
// check for error condition. Alpha syscall convention is to // check for error condition. Alpha syscall convention is to
// indicate success/failure in reg a3 (r19) and put the // indicate success/failure in reg a3 (r19) and put the

4
src/cpu/o3/alpha_dyn_inst.hh
View file

@ -51,7 +51,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
{ {
public: public:
/** Typedef for the CPU. */ /** Typedef for the CPU. */
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
/** Binary machine instruction type. */ /** Binary machine instruction type. */
typedef TheISA::MachInst MachInst; typedef TheISA::MachInst MachInst;
@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
public: public:
/** BaseDynInst constructor given a binary instruction. */ /** BaseDynInst constructor given a binary instruction. */
AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
FullCPU *cpu); O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */ /** BaseDynInst constructor given a static inst pointer. */
AlphaDynInst(StaticInstPtr &_staticInst); AlphaDynInst(StaticInstPtr &_staticInst);

2
src/cpu/o3/alpha_dyn_inst_impl.hh
View file

@ -32,7 +32,7 @@
template <class Impl> template <class Impl>
AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
InstSeqNum seq_num, FullCPU *cpu) InstSeqNum seq_num, O3CPU *cpu)
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu) : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
{ {
initVars(); initVars();

14
src/cpu/o3/alpha_impl.hh
View file

@ -41,12 +41,12 @@ template <class Impl>
class AlphaDynInst; class AlphaDynInst;
template <class Impl> template <class Impl>
class AlphaFullCPU; class AlphaO3CPU;
/** Implementation specific struct that defines several key types to the /** Implementation specific struct that defines several key types to the
* CPU, the stages within the CPU, the time buffers, and the DynInst. * CPU, the stages within the CPU, the time buffers, and the DynInst.
* The struct defines the ISA, the CPU policy, the specific DynInst, the * The struct defines the ISA, the CPU policy, the specific DynInst, the
* specific FullCPU, and all of the structs from the time buffers to do * specific O3CPU, and all of the structs from the time buffers to do
* communication. * communication.
* This is one of the key things that must be defined for each hardware * This is one of the key things that must be defined for each hardware
* specific CPU implementation. * specific CPU implementation.
@ -67,8 +67,14 @@ struct AlphaSimpleImpl
*/ */
typedef RefCountingPtr<DynInst> DynInstPtr; typedef RefCountingPtr<DynInst> DynInstPtr;
/** The FullCPU type to be used. */ /** The O3CPU type to be used. */
typedef AlphaFullCPU<AlphaSimpleImpl> FullCPU; typedef AlphaO3CPU<AlphaSimpleImpl> O3CPU;
/** Same typedef, but for CPUType. BaseDynInst may not always use
* an O3 CPU, so it's clearer to call it CPUType instead in that
* case.
*/
typedef O3CPU CPUType;
/** The Params to be passed to each stage. */ /** The Params to be passed to each stage. */
typedef AlphaSimpleParams Params; typedef AlphaSimpleParams Params;

4
src/cpu/o3/alpha_params.hh
View file

@ -42,12 +42,12 @@ class Process;
class System; class System;
/** /**
* This file defines the parameters that will be used for the AlphaFullCPU. * This file defines the parameters that will be used for the AlphaO3CPU.
* This must be defined externally so that the Impl can have a params class * This must be defined externally so that the Impl can have a params class
* defined that it can pass to all of the individual stages. * defined that it can pass to all of the individual stages.
*/ */
class AlphaSimpleParams : public BaseFullCPU::Params class AlphaSimpleParams : public BaseO3CPU::Params
{ {
public: public:

8
src/cpu/o3/commit.hh
View file

@ -67,7 +67,7 @@ class DefaultCommit
{ {
public: public:
// Typedefs from the Impl. // Typedefs from the Impl.
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
typedef typename Impl::CPUPol CPUPol; typedef typename Impl::CPUPol CPUPol;
@ -145,7 +145,7 @@ class DefaultCommit
void regStats(); void regStats();
/** Sets the CPU pointer. */ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets the list of threads. */ /** Sets the list of threads. */
void setThreads(std::vector<Thread *> &threads); void setThreads(std::vector<Thread *> &threads);
@ -317,8 +317,8 @@ class DefaultCommit
ROB *rob; ROB *rob;
private: private:
/** Pointer to FullCPU. */ /** Pointer to O3CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Vector of all of the threads. */ /** Vector of all of the threads. */
std::vector<Thread *> thread; std::vector<Thread *> thread;

15
src/cpu/o3/commit_impl.hh
View file

@ -28,6 +28,9 @@
* Authors: Kevin Lim * Authors: Kevin Lim
*/ */
#include "config/full_system.hh"
#include "config/use_checker.hh"
#include <algorithm> #include <algorithm>
#include <string> #include <string>
@ -219,14 +222,14 @@ DefaultCommit<Impl>::regStats()
template <class Impl> template <class Impl>
void void
DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
cpu = cpu_ptr; cpu = cpu_ptr;
// Commit must broadcast the number of free entries it has at the start of // Commit must broadcast the number of free entries it has at the start of
// the simulation, so it starts as active. // the simulation, so it starts as active.
cpu->activateStage(FullCPU::CommitIdx); cpu->activateStage(O3CPU::CommitIdx);
trapLatency = cpu->cycles(trapLatency); trapLatency = cpu->cycles(trapLatency);
fetchTrapLatency = cpu->cycles(fetchTrapLatency); fetchTrapLatency = cpu->cycles(fetchTrapLatency);
@ -395,10 +398,10 @@ DefaultCommit<Impl>::updateStatus()
if (_nextStatus == Inactive && _status == Active) { if (_nextStatus == Inactive && _status == Active) {
DPRINTF(Activity, "Deactivating stage.\n"); DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(FullCPU::CommitIdx); cpu->deactivateStage(O3CPU::CommitIdx);
} else if (_nextStatus == Active && _status == Inactive) { } else if (_nextStatus == Active && _status == Inactive) {
DPRINTF(Activity, "Activating stage.\n"); DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(FullCPU::CommitIdx); cpu->activateStage(O3CPU::CommitIdx);
} }
_status = _nextStatus; _status = _nextStatus;
@ -972,11 +975,13 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
head_inst->setCompleted(); head_inst->setCompleted();
} }
#if USE_CHECKER
// Use checker prior to updating anything due to traps or PC // Use checker prior to updating anything due to traps or PC
// based events. // based events.
if (cpu->checker) { if (cpu->checker) {
cpu->checker->verify(head_inst); cpu->checker->verify(head_inst);
} }
#endif
// Check if the instruction caused a fault. If so, trap. // Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault(); Fault inst_fault = head_inst->getFault();
@ -992,9 +997,11 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
return false; return false;
} }
#if USE_CHECKER
if (cpu->checker && head_inst->isStore()) { if (cpu->checker && head_inst->isStore()) {
cpu->checker->verify(head_inst); cpu->checker->verify(head_inst);
} }
#endif
assert(!thread[tid]->inSyscall); assert(!thread[tid]->inSyscall);

65
src/cpu/o3/cpu.cc
View file

@ -29,6 +29,7 @@
*/ */
#include "config/full_system.hh" #include "config/full_system.hh"
#include "config/use_checker.hh"
#if FULL_SYSTEM #if FULL_SYSTEM
#include "sim/system.hh" #include "sim/system.hh"
@ -50,13 +51,13 @@
using namespace std; using namespace std;
using namespace TheISA; using namespace TheISA;
BaseFullCPU::BaseFullCPU(Params *params) BaseO3CPU::BaseO3CPU(Params *params)
: BaseCPU(params), cpu_id(0) : BaseCPU(params), cpu_id(0)
{ {
} }
void void
BaseFullCPU::regStats() BaseO3CPU::regStats()
{ {
BaseCPU::regStats(); BaseCPU::regStats();
} }
@ -83,7 +84,7 @@ FullO3CPU<Impl>::TickEvent::description()
template <class Impl> template <class Impl>
FullO3CPU<Impl>::FullO3CPU(Params *params) FullO3CPU<Impl>::FullO3CPU(Params *params)
: BaseFullCPU(params), : BaseO3CPU(params),
tickEvent(this), tickEvent(this),
removeInstsThisCycle(false), removeInstsThisCycle(false),
fetch(params), fetch(params),
@ -131,6 +132,9 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
{ {
_status = Idle; _status = Idle;
checker = NULL;
#if USE_CHECKER
if (params->checker) { if (params->checker) {
BaseCPU *temp_checker = params->checker; BaseCPU *temp_checker = params->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
@ -138,9 +142,8 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
#if FULL_SYSTEM #if FULL_SYSTEM
checker->setSystem(params->system); checker->setSystem(params->system);
#endif #endif
} else {
checker = NULL;
} }
#endif
#if !FULL_SYSTEM #if !FULL_SYSTEM
thread.resize(number_of_threads); thread.resize(number_of_threads);
@ -261,9 +264,9 @@ template <class Impl>
void void
FullO3CPU<Impl>::fullCPURegStats() FullO3CPU<Impl>::fullCPURegStats()
{ {
BaseFullCPU::regStats(); BaseO3CPU::regStats();
// Register any of the FullCPU's stats here. // Register any of the O3CPU's stats here.
timesIdled timesIdled
.name(name() + ".timesIdled") .name(name() + ".timesIdled")
.desc("Number of times that the entire CPU went into an idle state and" .desc("Number of times that the entire CPU went into an idle state and"
@ -319,7 +322,7 @@ template <class Impl>
void void
FullO3CPU<Impl>::tick() FullO3CPU<Impl>::tick()
{ {
DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
++numCycles; ++numCycles;
@ -418,7 +421,7 @@ template <class Impl>
void void
FullO3CPU<Impl>::insertThread(unsigned tid) FullO3CPU<Impl>::insertThread(unsigned tid)
{ {
DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
// Will change now that the PC and thread state is internal to the CPU // Will change now that the PC and thread state is internal to the CPU
// and not in the ThreadContext. // and not in the ThreadContext.
#if 0 #if 0
@ -465,7 +468,7 @@ template <class Impl>
void void
FullO3CPU<Impl>::removeThread(unsigned tid) FullO3CPU<Impl>::removeThread(unsigned tid)
{ {
DPRINTF(FullCPU,"[tid:%i] Removing thread data"); DPRINTF(O3CPU,"[tid:%i] Removing thread data");
#if 0 #if 0
//Unbind Int Regs from Rename Map //Unbind Int Regs from Rename Map
for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
@ -511,37 +514,37 @@ template <class Impl>
void void
FullO3CPU<Impl>::activateWhenReady(int tid) FullO3CPU<Impl>::activateWhenReady(int tid)
{ {
DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming" DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
"(e.g. PhysRegs/ROB/IQ/LSQ) \n", "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
tid); tid);
bool ready = true; bool ready = true;
if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
"Phys. Int. Regs.\n", "Phys. Int. Regs.\n",
tid); tid);
ready = false; ready = false;
} else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
"Phys. Float. Regs.\n", "Phys. Float. Regs.\n",
tid); tid);
ready = false; ready = false;
} else if (commit.rob->numFreeEntries() >= } else if (commit.rob->numFreeEntries() >=
commit.rob->entryAmount(activeThreads.size() + 1)) { commit.rob->entryAmount(activeThreads.size() + 1)) {
DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
"ROB entries.\n", "ROB entries.\n",
tid); tid);
ready = false; ready = false;
} else if (iew.instQueue.numFreeEntries() >= } else if (iew.instQueue.numFreeEntries() >=
iew.instQueue.entryAmount(activeThreads.size() + 1)) { iew.instQueue.entryAmount(activeThreads.size() + 1)) {
DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
"IQ entries.\n", "IQ entries.\n",
tid); tid);
ready = false; ready = false;
} else if (iew.ldstQueue.numFreeEntries() >= } else if (iew.ldstQueue.numFreeEntries() >=
iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
"LSQ entries.\n", "LSQ entries.\n",
tid); tid);
ready = false; ready = false;
@ -575,7 +578,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
if (isActive == activeThreads.end()) { if (isActive == activeThreads.end()) {
//May Need to Re-code this if the delay variable is the //May Need to Re-code this if the delay variable is the
//delay needed for thread to activate //delay needed for thread to activate
DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
tid); tid);
activeThreads.push_back(tid); activeThreads.push_back(tid);
@ -597,7 +600,7 @@ template <class Impl>
void void
FullO3CPU<Impl>::suspendContext(int tid) FullO3CPU<Impl>::suspendContext(int tid)
{ {
DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid); DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
unscheduleTickEvent(); unscheduleTickEvent();
_status = Idle; _status = Idle;
/* /*
@ -606,7 +609,7 @@ FullO3CPU<Impl>::suspendContext(int tid)
activeThreads.begin(), activeThreads.end(), tid); activeThreads.begin(), activeThreads.end(), tid);
if (isActive != activeThreads.end()) { if (isActive != activeThreads.end()) {
DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
tid); tid);
activeThreads.erase(isActive); activeThreads.erase(isActive);
} }
@ -617,14 +620,14 @@ template <class Impl>
void void
FullO3CPU<Impl>::deallocateContext(int tid) FullO3CPU<Impl>::deallocateContext(int tid)
{ {
DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid); DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
/* /*
//Remove From Active List, if Active //Remove From Active List, if Active
list<unsigned>::iterator isActive = find( list<unsigned>::iterator isActive = find(
activeThreads.begin(), activeThreads.end(), tid); activeThreads.begin(), activeThreads.end(), tid);
if (isActive != activeThreads.end()) { if (isActive != activeThreads.end()) {
DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
tid); tid);
activeThreads.erase(isActive); activeThreads.erase(isActive);
@ -637,14 +640,14 @@ template <class Impl>
void void
FullO3CPU<Impl>::haltContext(int tid) FullO3CPU<Impl>::haltContext(int tid)
{ {
DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid); DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
/* /*
//Remove From Active List, if Active //Remove From Active List, if Active
list<unsigned>::iterator isActive = find( list<unsigned>::iterator isActive = find(
activeThreads.begin(), activeThreads.end(), tid); activeThreads.begin(), activeThreads.end(), tid);
if (isActive != activeThreads.end()) { if (isActive != activeThreads.end()) {
DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
tid); tid);
activeThreads.erase(isActive); activeThreads.erase(isActive);
@ -730,7 +733,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
if (isActive == activeThreads.end()) { if (isActive == activeThreads.end()) {
//May Need to Re-code this if the delay variable is the delay //May Need to Re-code this if the delay variable is the delay
//needed for thread to activate //needed for thread to activate
DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
tid); tid);
activeThreads.push_back(tid); activeThreads.push_back(tid);
@ -958,7 +961,7 @@ template <class Impl>
void void
FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
{ {
DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x " DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
"[sn:%lli]\n", "[sn:%lli]\n",
inst->threadNumber, inst->readPC(), inst->seqNum); inst->threadNumber, inst->readPC(), inst->seqNum);
@ -972,7 +975,7 @@ template <class Impl>
void void
FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
{ {
DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction" DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
" list.\n", tid); " list.\n", tid);
ListIt end_it; ListIt end_it;
@ -982,12 +985,12 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
if (instList.empty()) { if (instList.empty()) {
return; return;
} else if (rob.isEmpty(/*tid*/)) { } else if (rob.isEmpty(/*tid*/)) {
DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n"); DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
end_it = instList.begin(); end_it = instList.begin();
rob_empty = true; rob_empty = true;
} else { } else {
end_it = (rob.readTailInst(tid))->getInstListIt(); end_it = (rob.readTailInst(tid))->getInstListIt();
DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n"); DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
} }
removeInstsThisCycle = true; removeInstsThisCycle = true;
@ -1026,7 +1029,7 @@ FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
inst_iter--; inst_iter--;
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " DPRINTF(O3CPU, "Deleting instructions from instruction "
"list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
tid, seq_num, (*inst_iter)->seqNum); tid, seq_num, (*inst_iter)->seqNum);
@ -1048,7 +1051,7 @@ inline void
FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
{ {
if ((*instIt)->threadNumber == tid) { if ((*instIt)->threadNumber == tid) {
DPRINTF(FullCPU, "FullCPU: Squashing instruction, " DPRINTF(O3CPU, "Squashing instruction, "
"[tid:%i] [sn:%lli] PC %#x\n", "[tid:%i] [sn:%lli] PC %#x\n",
(*instIt)->threadNumber, (*instIt)->threadNumber,
(*instIt)->seqNum, (*instIt)->seqNum,
@ -1069,7 +1072,7 @@ void
FullO3CPU<Impl>::cleanUpRemovedInsts() FullO3CPU<Impl>::cleanUpRemovedInsts()
{ {
while (!removeList.empty()) { while (!removeList.empty()) {
DPRINTF(FullCPU, "FullCPU: Removing instruction, " DPRINTF(O3CPU, "Removing instruction, "
"[tid:%i] [sn:%lli] PC %#x\n", "[tid:%i] [sn:%lli] PC %#x\n",
(*removeList.front())->threadNumber, (*removeList.front())->threadNumber,
(*removeList.front())->seqNum, (*removeList.front())->seqNum,

6
src/cpu/o3/cpu.hh
View file

@ -56,13 +56,13 @@ class ThreadContext;
class MemObject; class MemObject;
class Process; class Process;
class BaseFullCPU : public BaseCPU class BaseO3CPU : public BaseCPU
{ {
//Stuff that's pretty ISA independent will go here. //Stuff that's pretty ISA independent will go here.
public: public:
typedef BaseCPU::Params Params; typedef BaseCPU::Params Params;
BaseFullCPU(Params *params); BaseO3CPU(Params *params);
void regStats(); void regStats();
@ -78,7 +78,7 @@ class BaseFullCPU : public BaseCPU
* tick() function for the CPU is defined here. * tick() function for the CPU is defined here.
*/ */
template <class Impl> template <class Impl>
class FullO3CPU : public BaseFullCPU class FullO3CPU : public BaseO3CPU
{ {
public: public:
typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatReg FloatReg;

6
src/cpu/o3/decode.hh
View file

@ -48,7 +48,7 @@ class DefaultDecode
{ {
private: private:
// Typedefs from the Impl. // Typedefs from the Impl.
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
typedef typename Impl::CPUPol CPUPol; typedef typename Impl::CPUPol CPUPol;
@ -95,7 +95,7 @@ class DefaultDecode
void regStats(); void regStats();
/** Sets CPU pointer. */ /** Sets CPU pointer. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets the main backwards communication time buffer pointer. */ /** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
@ -189,7 +189,7 @@ class DefaultDecode
private: private:
// Interfaces to objects outside of decode. // Interfaces to objects outside of decode.
/** CPU interface. */ /** CPU interface. */
FullCPU *cpu; O3CPU *cpu;
/** Time buffer interface. */ /** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer; TimeBuffer<TimeStruct> *timeBuffer;

6
src/cpu/o3/decode_impl.hh
View file

@ -112,7 +112,7 @@ DefaultDecode<Impl>::regStats()
template<class Impl> template<class Impl>
void void
DefaultDecode<Impl>::setCPU(FullCPU *cpu_ptr) DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
DPRINTF(Decode, "Setting CPU pointer.\n"); DPRINTF(Decode, "Setting CPU pointer.\n");
cpu = cpu_ptr; cpu = cpu_ptr;
@ -427,7 +427,7 @@ DefaultDecode<Impl>::updateStatus()
DPRINTF(Activity, "Activating stage.\n"); DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(FullCPU::DecodeIdx); cpu->activateStage(O3CPU::DecodeIdx);
} }
} else { } else {
// If it's not unblocking, then decode will not have any internal // If it's not unblocking, then decode will not have any internal
@ -436,7 +436,7 @@ DefaultDecode<Impl>::updateStatus()
_status = Inactive; _status = Inactive;
DPRINTF(Activity, "Deactivating stage.\n"); DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(FullCPU::DecodeIdx); cpu->deactivateStage(O3CPU::DecodeIdx);
} }
} }
} }

8
src/cpu/o3/fetch.hh
View file

@ -57,7 +57,7 @@ class DefaultFetch
typedef typename Impl::CPUPol CPUPol; typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInst DynInst;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
/** Typedefs from the CPU policy. */ /** Typedefs from the CPU policy. */
@ -164,7 +164,7 @@ class DefaultFetch
void regStats(); void regStats();
/** Sets CPU pointer. */ /** Sets CPU pointer. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets the main backwards communication time buffer pointer. */ /** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
@ -296,8 +296,8 @@ class DefaultFetch
int branchCount(); int branchCount();
private: private:
/** Pointer to the FullCPU. */ /** Pointer to the O3CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Time buffer interface. */ /** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer; TimeBuffer<TimeStruct> *timeBuffer;

14
src/cpu/o3/fetch_impl.hh
View file

@ -28,6 +28,8 @@
* Authors: Kevin Lim * Authors: Kevin Lim
*/ */
#include "config/use_checker.hh"
#include "arch/isa_traits.hh" #include "arch/isa_traits.hh"
#include "arch/utility.hh" #include "arch/utility.hh"
#include "cpu/checker/cpu.hh" #include "cpu/checker/cpu.hh"
@ -268,7 +270,7 @@ DefaultFetch<Impl>::regStats()
template<class Impl> template<class Impl>
void void
DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr) DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
DPRINTF(Fetch, "Setting the CPU pointer.\n"); DPRINTF(Fetch, "Setting the CPU pointer.\n");
cpu = cpu_ptr; cpu = cpu_ptr;
@ -280,9 +282,11 @@ DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
icachePort->setPeer(mem_dport); icachePort->setPeer(mem_dport);
mem_dport->setPeer(icachePort); mem_dport->setPeer(icachePort);
#if USE_CHECKER
if (cpu->checker) { if (cpu->checker) {
cpu->checker->setIcachePort(icachePort); cpu->checker->setIcachePort(icachePort);
} }
#endif
// Fetch needs to start fetching instructions at the very beginning, // Fetch needs to start fetching instructions at the very beginning,
// so it must start up in active state. // so it must start up in active state.
@ -430,7 +434,7 @@ DefaultFetch<Impl>::switchToActive()
if (_status == Inactive) { if (_status == Inactive) {
DPRINTF(Activity, "Activating stage.\n"); DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(FullCPU::FetchIdx); cpu->activateStage(O3CPU::FetchIdx);
_status = Active; _status = Active;
} }
@ -443,7 +447,7 @@ DefaultFetch<Impl>::switchToInactive()
if (_status == Active) { if (_status == Active) {
DPRINTF(Activity, "Deactivating stage.\n"); DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(FullCPU::FetchIdx); cpu->deactivateStage(O3CPU::FetchIdx);
_status = Inactive; _status = Inactive;
} }
@ -662,7 +666,7 @@ DefaultFetch<Impl>::updateFetchStatus()
"completion\n",tid); "completion\n",tid);
} }
cpu->activateStage(FullCPU::FetchIdx); cpu->activateStage(O3CPU::FetchIdx);
} }
return Active; return Active;
@ -673,7 +677,7 @@ DefaultFetch<Impl>::updateFetchStatus()
if (_status == Active) { if (_status == Active) {
DPRINTF(Activity, "Deactivating stage.\n"); DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(FullCPU::FetchIdx); cpu->deactivateStage(O3CPU::FetchIdx);
} }
return Inactive; return Inactive;

8
src/cpu/o3/iew.hh
View file

@ -68,7 +68,7 @@ class DefaultIEW
//Typedefs from Impl //Typedefs from Impl
typedef typename Impl::CPUPol CPUPol; typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
typedef typename CPUPol::IQ IQ; typedef typename CPUPol::IQ IQ;
@ -80,7 +80,7 @@ class DefaultIEW
typedef typename CPUPol::RenameStruct RenameStruct; typedef typename CPUPol::RenameStruct RenameStruct;
typedef typename CPUPol::IssueStruct IssueStruct; typedef typename CPUPol::IssueStruct IssueStruct;
friend class Impl::FullCPU; friend class Impl::O3CPU;
friend class CPUPol::IQ; friend class CPUPol::IQ;
public: public:
@ -126,7 +126,7 @@ class DefaultIEW
void initStage(); void initStage();
/** Sets CPU pointer for IEW, IQ, and LSQ. */ /** Sets CPU pointer for IEW, IQ, and LSQ. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets main time buffer used for backwards communication. */ /** Sets main time buffer used for backwards communication. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
@ -331,7 +331,7 @@ class DefaultIEW
private: private:
/** CPU pointer. */ /** CPU pointer. */
FullCPU *cpu; O3CPU *cpu;
/** Records if IEW has written to the time buffer this cycle, so that the /** Records if IEW has written to the time buffer this cycle, so that the
* CPU can deschedule itself if there is no activity. * CPU can deschedule itself if there is no activity.

8
src/cpu/o3/iew_impl.hh
View file

@ -276,7 +276,7 @@ DefaultIEW<Impl>::initStage()
template<class Impl> template<class Impl>
void void
DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
DPRINTF(IEW, "Setting CPU pointer.\n"); DPRINTF(IEW, "Setting CPU pointer.\n");
cpu = cpu_ptr; cpu = cpu_ptr;
@ -284,7 +284,7 @@ DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
instQueue.setCPU(cpu_ptr); instQueue.setCPU(cpu_ptr);
ldstQueue.setCPU(cpu_ptr); ldstQueue.setCPU(cpu_ptr);
cpu->activateStage(FullCPU::IEWIdx); cpu->activateStage(O3CPU::IEWIdx);
} }
template<class Impl> template<class Impl>
@ -857,7 +857,7 @@ inline void
DefaultIEW<Impl>::activateStage() DefaultIEW<Impl>::activateStage()
{ {
DPRINTF(Activity, "Activating stage.\n"); DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(FullCPU::IEWIdx); cpu->activateStage(O3CPU::IEWIdx);
} }
template <class Impl> template <class Impl>
@ -865,7 +865,7 @@ inline void
DefaultIEW<Impl>::deactivateStage() DefaultIEW<Impl>::deactivateStage()
{ {
DPRINTF(Activity, "Deactivating stage.\n"); DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(FullCPU::IEWIdx); cpu->deactivateStage(O3CPU::IEWIdx);
} }
template<class Impl> template<class Impl>

8
src/cpu/o3/inst_queue.hh
View file

@ -68,7 +68,7 @@ class InstructionQueue
{ {
public: public:
//Typedefs from the Impl. //Typedefs from the Impl.
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
@ -80,7 +80,7 @@ class InstructionQueue
// Typedef of iterator through the list of instructions. // Typedef of iterator through the list of instructions.
typedef typename std::list<DynInstPtr>::iterator ListIt; typedef typename std::list<DynInstPtr>::iterator ListIt;
friend class Impl::FullCPU; friend class Impl::O3CPU;
/** FU completion event class. */ /** FU completion event class. */
class FUCompletion : public Event { class FUCompletion : public Event {
@ -125,7 +125,7 @@ class InstructionQueue
void resetState(); void resetState();
/** Sets CPU pointer. */ /** Sets CPU pointer. */
void setCPU(FullCPU *_cpu) { cpu = _cpu; } void setCPU(O3CPU *_cpu) { cpu = _cpu; }
/** Sets active threads list. */ /** Sets active threads list. */
void setActiveThreads(std::list<unsigned> *at_ptr); void setActiveThreads(std::list<unsigned> *at_ptr);
@ -252,7 +252,7 @@ class InstructionQueue
///////////////////////// /////////////////////////
/** Pointer to the CPU. */ /** Pointer to the CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Cache interface. */ /** Cache interface. */
MemInterface *dcacheInterface; MemInterface *dcacheInterface;

6
src/cpu/o3/lsq.hh
View file

@ -44,7 +44,7 @@ template <class Impl>
class LSQ { class LSQ {
public: public:
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::CPUPol::IEW IEW; typedef typename Impl::CPUPol::IEW IEW;
typedef typename Impl::CPUPol::LSQUnit LSQUnit; typedef typename Impl::CPUPol::LSQUnit LSQUnit;
@ -68,7 +68,7 @@ class LSQ {
/** Sets the pointer to the list of active threads. */ /** Sets the pointer to the list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr); void setActiveThreads(std::list<unsigned> *at_ptr);
/** Sets the CPU pointer. */ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets the IEW stage pointer. */ /** Sets the IEW stage pointer. */
void setIEW(IEW *iew_ptr); void setIEW(IEW *iew_ptr);
/** Switches out the LSQ. */ /** Switches out the LSQ. */
@ -275,7 +275,7 @@ class LSQ {
LSQUnit thread[Impl::MaxThreads]; LSQUnit thread[Impl::MaxThreads];
/** The CPU pointer. */ /** The CPU pointer. */
FullCPU *cpu; O3CPU *cpu;
/** The IEW stage pointer. */ /** The IEW stage pointer. */
IEW *iewStage; IEW *iewStage;

2
src/cpu/o3/lsq_impl.hh
View file

@ -126,7 +126,7 @@ LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
template<class Impl> template<class Impl>
void void
LSQ<Impl>::setCPU(FullCPU *cpu_ptr) LSQ<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
cpu = cpu_ptr; cpu = cpu_ptr;

10
src/cpu/o3/lsq_unit.hh
View file

@ -61,7 +61,7 @@ class LSQUnit {
typedef TheISA::IntReg IntReg; typedef TheISA::IntReg IntReg;
public: public:
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::CPUPol::IEW IEW; typedef typename Impl::CPUPol::IEW IEW;
typedef typename Impl::CPUPol::IssueStruct IssueStruct; typedef typename Impl::CPUPol::IssueStruct IssueStruct;
@ -81,7 +81,7 @@ class LSQUnit {
void regStats(); void regStats();
/** Sets the CPU pointer. */ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets the IEW stage pointer. */ /** Sets the IEW stage pointer. */
void setIEW(IEW *iew_ptr) void setIEW(IEW *iew_ptr)
@ -232,7 +232,7 @@ class LSQUnit {
private: private:
/** Pointer to the CPU. */ /** Pointer to the CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Pointer to the IEW stage. */ /** Pointer to the IEW stage. */
IEW *iewStage; IEW *iewStage;
@ -249,13 +249,13 @@ class LSQUnit {
{ {
protected: protected:
/** Pointer to CPU. */ /** Pointer to CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Pointer to LSQ. */ /** Pointer to LSQ. */
LSQUnit *lsq; LSQUnit *lsq;
public: public:
/** Default constructor. */ /** Default constructor. */
DcachePort(FullCPU *_cpu, LSQUnit *_lsq) DcachePort(O3CPU *_cpu, LSQUnit *_lsq)
: Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq) : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
{ } { }

10
src/cpu/o3/lsq_unit_impl.hh
View file

@ -29,6 +29,8 @@
* Korey Sewell * Korey Sewell
*/ */
#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh" #include "cpu/checker/cpu.hh"
#include "cpu/o3/lsq_unit.hh" #include "cpu/o3/lsq_unit.hh"
#include "base/str.hh" #include "base/str.hh"
@ -171,7 +173,7 @@ LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
template<class Impl> template<class Impl>
void void
LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
cpu = cpu_ptr; cpu = cpu_ptr;
dcachePort = new DcachePort(cpu, this); dcachePort = new DcachePort(cpu, this);
@ -180,9 +182,11 @@ LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
dcachePort->setPeer(mem_dport); dcachePort->setPeer(mem_dport);
mem_dport->setPeer(dcachePort); mem_dport->setPeer(dcachePort);
#if USE_CHECKER
if (cpu->checker) { if (cpu->checker) {
cpu->checker->setDcachePort(dcachePort); cpu->checker->setDcachePort(dcachePort);
} }
#endif
} }
template<class Impl> template<class Impl>
@ -788,9 +792,11 @@ LSQUnit<Impl>::storePostSend(Packet *pkt)
// only works so long as the checker doesn't try to // only works so long as the checker doesn't try to
// verify the value in memory for stores. // verify the value in memory for stores.
storeQueue[storeWBIdx].inst->setCompleted(); storeQueue[storeWBIdx].inst->setCompleted();
#if USE_CHECKER
if (cpu->checker) { if (cpu->checker) {
cpu->checker->verify(storeQueue[storeWBIdx].inst); cpu->checker->verify(storeQueue[storeWBIdx].inst);
} }
#endif
} }
if (pkt->result != Packet::Success) { if (pkt->result != Packet::Success) {
@ -884,9 +890,11 @@ LSQUnit<Impl>::completeStore(int store_idx)
// Tell the checker we've completed this instruction. Some stores // Tell the checker we've completed this instruction. Some stores
// may get reported twice to the checker, but the checker can // may get reported twice to the checker, but the checker can
// handle that case. // handle that case.
#if USE_CHECKER
if (cpu->checker) { if (cpu->checker) {
cpu->checker->verify(storeQueue[store_idx].inst); cpu->checker->verify(storeQueue[store_idx].inst);
} }
#endif
} }
template <class Impl> template <class Impl>

6
src/cpu/o3/regfile.hh
View file

@ -72,7 +72,7 @@ class PhysRegFile
// Will make these registers public for now, but they probably should // Will make these registers public for now, but they probably should
// be private eventually with some accessor functions. // be private eventually with some accessor functions.
public: public:
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
/** /**
* Constructs a physical register file with the specified amount of * Constructs a physical register file with the specified amount of
@ -278,11 +278,11 @@ class PhysRegFile
private: private:
/** CPU pointer. */ /** CPU pointer. */
FullCPU *cpu; O3CPU *cpu;
public: public:
/** Sets the CPU pointer. */ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
/** Number of physical integer registers. */ /** Number of physical integer registers. */
unsigned numPhysicalIntRegs; unsigned numPhysicalIntRegs;

6
src/cpu/o3/rename.hh
View file

@ -55,7 +55,7 @@ class DefaultRename
// Typedefs from the Impl. // Typedefs from the Impl.
typedef typename Impl::CPUPol CPUPol; typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::Params Params; typedef typename Impl::Params Params;
// Typedefs from the CPUPol // Typedefs from the CPUPol
@ -115,7 +115,7 @@ class DefaultRename
void regStats(); void regStats();
/** Sets CPU pointer. */ /** Sets CPU pointer. */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets the main backwards communication time buffer pointer. */ /** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
@ -291,7 +291,7 @@ class DefaultRename
std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
/** Pointer to CPU. */ /** Pointer to CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Pointer to main time buffer used for backwards communication. */ /** Pointer to main time buffer used for backwards communication. */
TimeBuffer<TimeStruct> *timeBuffer; TimeBuffer<TimeStruct> *timeBuffer;

6
src/cpu/o3/rename_impl.hh
View file

@ -162,7 +162,7 @@ DefaultRename<Impl>::regStats()
template <class Impl> template <class Impl>
void void
DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
DPRINTF(Rename, "Setting CPU pointer.\n"); DPRINTF(Rename, "Setting CPU pointer.\n");
cpu = cpu_ptr; cpu = cpu_ptr;
@ -755,7 +755,7 @@ DefaultRename<Impl>::updateStatus()
DPRINTF(Activity, "Activating stage.\n"); DPRINTF(Activity, "Activating stage.\n");
cpu->activateStage(FullCPU::RenameIdx); cpu->activateStage(O3CPU::RenameIdx);
} }
} else { } else {
// If it's not unblocking, then rename will not have any internal // If it's not unblocking, then rename will not have any internal
@ -764,7 +764,7 @@ DefaultRename<Impl>::updateStatus()
_status = Inactive; _status = Inactive;
DPRINTF(Activity, "Deactivating stage.\n"); DPRINTF(Activity, "Deactivating stage.\n");
cpu->deactivateStage(FullCPU::RenameIdx); cpu->deactivateStage(O3CPU::RenameIdx);
} }
} }
} }

6
src/cpu/o3/rob.hh
View file

@ -45,7 +45,7 @@ class ROB
typedef TheISA::RegIndex RegIndex; typedef TheISA::RegIndex RegIndex;
public: public:
//Typedefs from the Impl. //Typedefs from the Impl.
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
@ -90,7 +90,7 @@ class ROB
* is created within. * is created within.
* @param cpu_ptr Pointer to the implementation specific full CPU object. * @param cpu_ptr Pointer to the implementation specific full CPU object.
*/ */
void setCPU(FullCPU *cpu_ptr); void setCPU(O3CPU *cpu_ptr);
/** Sets pointer to the list of active threads. /** Sets pointer to the list of active threads.
* @param at_ptr Pointer to the list of active threads. * @param at_ptr Pointer to the list of active threads.
@ -257,7 +257,7 @@ class ROB
private: private:
/** Pointer to the CPU. */ /** Pointer to the CPU. */
FullCPU *cpu; O3CPU *cpu;
/** Active Threads in CPU */ /** Active Threads in CPU */
std::list<unsigned>* activeThreads; std::list<unsigned>* activeThreads;

2
src/cpu/o3/rob_impl.hh
View file

@ -100,7 +100,7 @@ ROB<Impl>::name() const
template <class Impl> template <class Impl>
void void
ROB<Impl>::setCPU(FullCPU *cpu_ptr) ROB<Impl>::setCPU(O3CPU *cpu_ptr)
{ {
cpu = cpu_ptr; cpu = cpu_ptr;

8
src/cpu/o3/thread_state.hh
View file

@ -58,11 +58,11 @@ class Process;
template <class Impl> template <class Impl>
struct O3ThreadState : public ThreadState { struct O3ThreadState : public ThreadState {
typedef ThreadContext::Status Status; typedef ThreadContext::Status Status;
typedef typename Impl::FullCPU FullCPU; typedef typename Impl::O3CPU O3CPU;
private: private:
/** Pointer to the CPU. */ /** Pointer to the CPU. */
FullCPU *cpu; O3CPU *cpu;
public: public:
/** Whether or not the thread is currently in syscall mode, and /** Whether or not the thread is currently in syscall mode, and
* thus able to be externally updated without squashing. * thus able to be externally updated without squashing.
@ -75,12 +75,12 @@ struct O3ThreadState : public ThreadState {
bool trapPending; bool trapPending;
#if FULL_SYSTEM #if FULL_SYSTEM
O3ThreadState(FullCPU *_cpu, int _thread_num) O3ThreadState(O3CPU *_cpu, int _thread_num)
: ThreadState(-1, _thread_num), : ThreadState(-1, _thread_num),
inSyscall(0), trapPending(0) inSyscall(0), trapPending(0)
{ } { }
#else #else
O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid, O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid,
MemObject *mem) MemObject *mem)
: ThreadState(-1, _thread_num, mem, _process, _asid), : ThreadState(-1, _thread_num, mem, _process, _asid),
cpu(_cpu), inSyscall(0), trapPending(0) cpu(_cpu), inSyscall(0), trapPending(0)

4
src/python/m5/objects/AlphaFullCPU.py → src/python/m5/objects/AlphaO3CPU.py
View file

@ -2,8 +2,8 @@ from m5 import build_env
from m5.config import * from m5.config import *
from BaseCPU import BaseCPU from BaseCPU import BaseCPU
class DerivAlphaFullCPU(BaseCPU): class DerivAlphaO3CPU(BaseCPU):
type = 'DerivAlphaFullCPU' type = 'DerivAlphaO3CPU'
activity = Param.Unsigned("Initial count") activity = Param.Unsigned("Initial count")
numThreads = Param.Unsigned("number of HW thread contexts") numThreads = Param.Unsigned("number of HW thread contexts")