Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
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@ -122,6 +122,7 @@ baseFlags = [
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'MSHR',
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'Mbox',
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'MemDepUnit',
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'MemoryAccess',
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'O3CPU',
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'OzoneCPU',
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'OzoneLSQ',
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5
src/mem/cache/cache_impl.hh
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5
src/mem/cache/cache_impl.hh
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@ -389,6 +389,11 @@ template<class TagStore, class Buffering, class Coherence>
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void
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Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
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{
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if (pkt->req->isUncacheable()) {
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//Can't get a hit on an uncacheable address
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//Revisit this for multi level coherence
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return;
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}
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Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
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BlkType *blk = tags->findBlock(pkt);
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MSHR *mshr = missQueue->findMSHR(blk_addr);
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2
src/mem/cache/miss/miss_queue.cc
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2
src/mem/cache/miss/miss_queue.cc
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@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
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MSHR*
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MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
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{
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MSHR* mshr = mq.allocate(pkt, blkSize);
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MSHR* mshr = mq.allocate(pkt, size);
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mshr->order = order++;
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if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
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// Mark this as a cache line fill
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@ -201,12 +201,16 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
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if (pkt->req->isLocked()) {
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trackLoadLocked(pkt->req);
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}
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DPRINTF(MemoryAccess, "Performing Read of size %i on address 0x%x\n",
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pkt->getSize(), pkt->getAddr());
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memcpy(pkt->getPtr<uint8_t>(),
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pmemAddr + pkt->getAddr() - params()->addrRange.start,
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pkt->getSize());
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}
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else if (pkt->isWrite()) {
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if (writeOK(pkt->req)) {
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DPRINTF(MemoryAccess, "Performing Write of size %i on address 0x%x\n",
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pkt->getSize(), pkt->getAddr());
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memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
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pkt->getPtr<uint8_t>(), pkt->getSize());
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}
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