From ba33db8fd66fe0814a59d520df54f0bb3788ce1d Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: [PATCH] ARM: Decode the CPS instruction.

---
 src/arch/arm/isa/formats/branch.isa | 5 ++++-
 src/arch/arm/isa/formats/data.isa   | 5 ++++-
 src/arch/arm/isa/formats/uncond.isa | 7 ++++++-
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 53a2c95b4..dbb6f9f9d 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -161,7 +161,10 @@ def format Thumb32BranchesAndMiscCtrl() {{
                         const uint32_t op1 = bits(machInst, 10, 8);
                         const uint32_t op2 = bits(machInst, 7, 0);
                         if (op1 != 0) {
-                            return new WarnUnimplemented("cps", machInst);
+                            const bool enable = bits(machInst, 10, 9) == 0x2;
+                            const uint32_t mods = bits(machInst, 8, 0) |
+                                                  ((enable ? 1 : 0) << 9);
+                            return new Cps(machInst, mods);
                         } else if ((op2 & 0xf0) == 0xf0) {
                             return new WarnUnimplemented("dbg", machInst);
                         } else {
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 19a9ee9fe..3e6265d0b 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1026,7 +1026,10 @@ def format Thumb16Misc() {{
                 if (opBits == 2) {
                     return new Setend(machInst, bits(machInst, 3));
                 } else if (opBits == 3) {
-                    return new WarnUnimplemented("cps", machInst);
+                    const bool enable = (bits(machInst, 4) == 0);
+                    const uint32_t mods = (bits(machInst, 2, 0) << 5) |
+                                          ((enable ? 1 : 0) << 9);
+                    return new Cps(machInst, mods);
                 }
             }
           case 0x9:
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index 45cdbd058..0aa57a261 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -46,7 +46,12 @@ def format ArmUnconditional() {{
                 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
                     return new Setend(machInst, bits(machInst, 9));
                 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
-                    return new WarnUnimplemented("cps", machInst);
+                    const bool enable = bits(machInst, 19, 18) == 0x2;
+                    const uint32_t mods = bits(machInst, 4, 0) |
+                                          (bits(machInst, 8, 6) << 5) |
+                                          (bits(machInst, 17) << 8) |
+                                          ((enable ? 1 : 0) << 9);
+                    return new Cps(machInst, mods);
                 }
             } else if (bits(op1, 6, 5) == 0x1) {
                 return new WarnUnimplemented(