Make memtest work with 8 memtesters
src/mem/physical.cc: Update comment to match memtest use src/python/m5/objects/PhysicalMemory.py: Make memtester have a way to connect functionally tests/configs/memtest.py: Properly create 8 memtesters and connect them to the memory system --HG-- extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
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3 changed files with 10 additions and 3 deletions
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@ -231,7 +231,7 @@ PhysicalMemory::getPort(const std::string &if_name, int idx)
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port = new MemoryPort(name() + "-port", this);
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port = new MemoryPort(name() + "-port", this);
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return port;
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return port;
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} else if (if_name == "functional") {
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} else if (if_name == "functional") {
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/* special port for functional writes at startup. */
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/* special port for functional writes at startup. And for memtester */
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return new MemoryPort(name() + "-funcport", this);
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return new MemoryPort(name() + "-funcport", this);
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} else {
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} else {
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panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
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panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
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@ -5,6 +5,7 @@ from MemObject import *
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class PhysicalMemory(MemObject):
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class PhysicalMemory(MemObject):
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type = 'PhysicalMemory'
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type = 'PhysicalMemory'
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port = Port("the access port")
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port = Port("the access port")
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functional = Port("Functional Access Port")
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range = Param.AddrRange(AddrRange('128MB'), "Device Address")
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range = Param.AddrRange(AddrRange('128MB'), "Device Address")
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file = Param.String('', "memory mapped file")
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file = Param.String('', "memory mapped file")
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latency = Param.Latency(Parent.clock, "latency of an access")
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latency = Param.Latency(Parent.clock, "latency of an access")
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@ -51,7 +51,8 @@ class L2(BaseCache):
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tgts_per_mshr = 16
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tgts_per_mshr = 16
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write_buffers = 8
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write_buffers = 8
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nb_cores = 1
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
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cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
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# system simulated
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# system simulated
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@ -66,12 +67,17 @@ system.l2c.cpu_side = system.toL2Bus.port
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# connect l2c to membus
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# connect l2c to membus
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system.l2c.mem_side = system.membus.port
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system.l2c.mem_side = system.membus.port
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which_port = 0
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# add L1 caches
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# add L1 caches
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for cpu in cpus:
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for cpu in cpus:
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cpu.l1c = L1(size = '32kB', assoc = 4)
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cpu.l1c = L1(size = '32kB', assoc = 4)
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cpu.l1c.cpu_side = cpu.test
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cpu.l1c.cpu_side = cpu.test
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cpu.l1c.mem_side = system.toL2Bus.port
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cpu.l1c.mem_side = system.toL2Bus.port
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system.funcmem.port = cpu.functional
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if which_port == 0:
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system.funcmem.port = cpu.functional
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which_port = 1
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else:
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system.funcmem.functional = cpu.functional
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# connect memory to membus
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# connect memory to membus
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