Make memtest work with 8 memtesters

src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
This commit is contained in:
Ron Dreslinski 2006-10-09 17:13:50 -04:00
parent d7c1557e7e
commit b9fb4d4870
3 changed files with 10 additions and 3 deletions

View file

@ -231,7 +231,7 @@ PhysicalMemory::getPort(const std::string &if_name, int idx)
port = new MemoryPort(name() + "-port", this); port = new MemoryPort(name() + "-port", this);
return port; return port;
} else if (if_name == "functional") { } else if (if_name == "functional") {
/* special port for functional writes at startup. */ /* special port for functional writes at startup. And for memtester */
return new MemoryPort(name() + "-funcport", this); return new MemoryPort(name() + "-funcport", this);
} else { } else {
panic("PhysicalMemory::getPort: unknown port %s requested", if_name); panic("PhysicalMemory::getPort: unknown port %s requested", if_name);

View file

@ -5,6 +5,7 @@ from MemObject import *
class PhysicalMemory(MemObject): class PhysicalMemory(MemObject):
type = 'PhysicalMemory' type = 'PhysicalMemory'
port = Port("the access port") port = Port("the access port")
functional = Port("Functional Access Port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address") range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file") file = Param.String('', "memory mapped file")
latency = Param.Latency(Parent.clock, "latency of an access") latency = Param.Latency(Parent.clock, "latency of an access")

View file

@ -51,7 +51,8 @@ class L2(BaseCache):
tgts_per_mshr = 16 tgts_per_mshr = 16
write_buffers = 8 write_buffers = 8
nb_cores = 1 #MAX CORES IS 8 with the fals sharing method
nb_cores = 8
cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ] cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
# system simulated # system simulated
@ -66,12 +67,17 @@ system.l2c.cpu_side = system.toL2Bus.port
# connect l2c to membus # connect l2c to membus
system.l2c.mem_side = system.membus.port system.l2c.mem_side = system.membus.port
which_port = 0
# add L1 caches # add L1 caches
for cpu in cpus: for cpu in cpus:
cpu.l1c = L1(size = '32kB', assoc = 4) cpu.l1c = L1(size = '32kB', assoc = 4)
cpu.l1c.cpu_side = cpu.test cpu.l1c.cpu_side = cpu.test
cpu.l1c.mem_side = system.toL2Bus.port cpu.l1c.mem_side = system.toL2Bus.port
system.funcmem.port = cpu.functional if which_port == 0:
system.funcmem.port = cpu.functional
which_port = 1
else:
system.funcmem.functional = cpu.functional
# connect memory to membus # connect memory to membus