Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge src/base/traceflags.py: src/cpu/SConscript: Hand merge. src/cpu/o3/alpha/params.hh: Hand merge. This needs to get changed. --HG-- rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
This commit is contained in:
commit
b973fae85d
10 changed files with 102 additions and 26 deletions
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@ -48,8 +48,11 @@ ccfilename = sys.argv[1] + '.cc'
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# To define a new flag, simply add it to this list.
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#
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baseFlags = [
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'Activity',
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'AlphaConsole',
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'BADADDR',
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'BaseCPU',
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'BE',
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'BPredRAS',
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'Bus',
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'BusAddrRanges',
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@ -84,6 +87,7 @@ baseFlags = [
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'EthernetPIO',
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'EthernetSM',
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'Event',
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'FE',
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'Fault',
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'Fetch',
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'Flow',
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@ -97,6 +101,7 @@ baseFlags = [
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'GDBSend',
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'GDBWrite',
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'HWPrefetch',
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'IBE',
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'IEW',
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'IIC',
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'IICMore',
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@ -115,13 +120,8 @@ baseFlags = [
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'MSHR',
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'Mbox',
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'MemDepUnit',
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'BaseCPU'
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'O3CPU',
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'OzoneCPU',
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'FE',
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'IBE',
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'BE',
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'O3CPU',
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'OzoneLSQ',
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'PCEvent',
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'PCIA',
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@ -135,6 +135,7 @@ baseFlags = [
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'RenameMap',
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'SQL',
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'Sampler',
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'Scoreboard',
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'ScsiCtrl',
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'ScsiDisk',
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'ScsiNone',
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@ -158,8 +159,6 @@ baseFlags = [
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'Uart',
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'VtoPhys',
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'WriteBarrier',
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'Activity',
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'Scoreboard',
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'Writeback',
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]
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@ -178,7 +177,7 @@ compoundFlagMap = {
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'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
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'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
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'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
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'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity','Scoreboard','Writeback'],
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'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'O3CPU', 'Activity','Scoreboard','Writeback'],
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'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU']
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}
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@ -130,13 +130,13 @@ if need_simple_base:
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if 'FastCPU' in env['CPU_MODELS']:
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sources += Split('fast/cpu.cc')
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need_bp_unit = False
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if 'O3CPU' in env['CPU_MODELS']:
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need_bp_unit = True
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sources += SConscript('o3/SConscript', exports = 'env')
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sources += Split('''
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o3/2bit_local_pred.cc
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o3/base_dyn_inst.cc
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o3/bpred_unit.cc
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o3/btb.cc
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o3/commit.cc
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o3/decode.cc
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o3/fetch.cc
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@ -148,18 +148,17 @@ if 'O3CPU' in env['CPU_MODELS']:
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o3/lsq_unit.cc
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o3/lsq.cc
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o3/mem_dep_unit.cc
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o3/ras.cc
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o3/rename.cc
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o3/rename_map.cc
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o3/rob.cc
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o3/scoreboard.cc
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o3/store_set.cc
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o3/tournament_pred.cc
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''')
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if env['USE_CHECKER']:
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sources += Split('o3/checker_builder.cc')
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if 'OzoneCPU' in env['CPU_MODELS']:
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need_bp_unit = True
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sources += Split('''
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ozone/base_dyn_inst.cc
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ozone/bpred_unit.cc
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@ -174,6 +173,14 @@ if 'OzoneCPU' in env['CPU_MODELS']:
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if env['USE_CHECKER']:
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sources += Split('ozone/checker_builder.cc')
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if need_bp_unit:
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sources += Split('''
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o3/2bit_local_pred.cc
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o3/btb.cc
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o3/ras.cc
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o3/tournament_pred.cc
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''')
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if env['USE_CHECKER']:
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sources += Split('checker/cpu.cc')
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checker_supports = False
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@ -91,7 +91,10 @@ Param<unsigned> renameWidth;
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Param<unsigned> commitToIEWDelay;
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Param<unsigned> renameToIEWDelay;
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Param<unsigned> issueToExecuteDelay;
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Param<unsigned> dispatchWidth;
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Param<unsigned> issueWidth;
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Param<unsigned> wbWidth;
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Param<unsigned> wbDepth;
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SimObjectParam<FUPool *> fuPool;
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Param<unsigned> iewToCommitDelay;
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@ -207,7 +210,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
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"Issue/Execute/Writeback delay"),
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INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
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"to the IEW stage)"),
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INIT_PARAM(dispatchWidth, "Dispatch width"),
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INIT_PARAM(issueWidth, "Issue width"),
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INIT_PARAM(wbWidth, "Writeback width"),
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INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
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INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
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INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
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@ -333,7 +339,10 @@ CREATE_SIM_OBJECT(DerivO3CPU)
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params->commitToIEWDelay = commitToIEWDelay;
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params->renameToIEWDelay = renameToIEWDelay;
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params->issueToExecuteDelay = issueToExecuteDelay;
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params->dispatchWidth = dispatchWidth;
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params->issueWidth = issueWidth;
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params->wbWidth = wbWidth;
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params->wbDepth = wbDepth;
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params->fuPool = fuPool;
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params->iewToCommitDelay = iewToCommitDelay;
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@ -64,6 +64,9 @@ class AlphaSimpleParams : public O3Params
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BaseCPU *checker;
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unsigned decodeToFetchDelay;
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unsigned dispatchWidth;
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unsigned wbWidth;
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unsigned wbDepth;
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};
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#endif // __CPU_O3_ALPHA_PARAMS_HH__
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@ -204,6 +204,45 @@ class DefaultIEW
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/** Returns if the LSQ has any stores to writeback. */
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bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
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void incrWb(InstSeqNum &sn)
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{
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if (++wbOutstanding == wbMax)
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ableToIssue = false;
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DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
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#if DEBUG
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wbList.insert(sn);
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#endif
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}
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void decrWb(InstSeqNum &sn)
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{
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if (wbOutstanding-- == wbMax)
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ableToIssue = true;
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DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
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#if DEBUG
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assert(wbList.find(sn) != wbList.end());
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wbList.erase(sn);
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#endif
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}
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#if DEBUG
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std::set<InstSeqNum> wbList;
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void dumpWb()
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{
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std::set<InstSeqNum>::iterator wb_it = wbList.begin();
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while (wb_it != wbList.end()) {
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cprintf("[sn:%lli]\n",
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(*wb_it));
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wb_it++;
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}
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}
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#endif
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bool canIssue() { return ableToIssue; }
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bool ableToIssue;
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private:
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/** Sends commit proper information for a squash due to a branch
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* mispredict.
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@ -384,11 +423,8 @@ class DefaultIEW
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*/
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unsigned issueToExecuteDelay;
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/** Width of issue's read path, in instructions. The read path is both
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* the skid buffer and the rename instruction queue.
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* Note to self: is this really different than issueWidth?
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*/
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unsigned issueReadWidth;
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/** Width of dispatch, in instructions. */
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unsigned dispatchWidth;
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/** Width of issue, in instructions. */
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unsigned issueWidth;
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@ -403,6 +439,17 @@ class DefaultIEW
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*/
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unsigned wbCycle;
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/** Number of instructions in flight that will writeback. */
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unsigned wbOutstanding;
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/** Writeback width. */
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unsigned wbWidth;
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/** Writeback width * writeback depth, where writeback depth is
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* the number of cycles of writing back instructions that can be
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* buffered. */
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unsigned wbMax;
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/** Number of active threads. */
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unsigned numThreads;
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@ -50,8 +50,10 @@ DefaultIEW<Impl>::DefaultIEW(Params *params)
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commitToIEWDelay(params->commitToIEWDelay),
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renameToIEWDelay(params->renameToIEWDelay),
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issueToExecuteDelay(params->issueToExecuteDelay),
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issueReadWidth(params->issueWidth),
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dispatchWidth(params->dispatchWidth),
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issueWidth(params->issueWidth),
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wbOutstanding(0),
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wbWidth(params->wbWidth),
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numThreads(params->numberOfThreads),
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switchedOut(false)
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{
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fetchRedirect[i] = false;
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}
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wbMax = wbWidth * params->wbDepth;
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updateLSQNextCycle = false;
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ableToIssue = true;
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skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
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}
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@ -559,12 +565,12 @@ DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
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// free slot.
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while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
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++wbNumInst;
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if (wbNumInst == issueWidth) {
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if (wbNumInst == wbWidth) {
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++wbCycle;
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wbNumInst = 0;
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}
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assert(wbCycle < 5);
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assert((wbCycle * wbWidth + wbNumInst) < wbMax);
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}
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// Add finished instruction to queue to commit.
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@ -937,7 +943,7 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
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// Loop through the instructions, putting them in the instruction
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// queue.
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for ( ; dis_num_inst < insts_to_add &&
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dis_num_inst < issueReadWidth;
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dis_num_inst < dispatchWidth;
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++dis_num_inst)
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{
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inst = insts_to_dispatch.front();
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@ -1189,6 +1195,7 @@ DefaultIEW<Impl>::executeInsts()
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++iewExecSquashedInsts;
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decrWb(inst->seqNum);
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continue;
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}
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@ -1351,6 +1358,8 @@ DefaultIEW<Impl>::writebackInsts()
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}
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writebackCount[tid]++;
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}
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decrWb(inst->seqNum);
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}
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}
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@ -687,6 +687,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
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int total_issued = 0;
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while (total_issued < totalWidth &&
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iewStage->canIssue() &&
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order_it != order_end_it) {
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OpClass op_class = (*order_it).queueType;
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@ -784,6 +785,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
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listOrder.erase(order_it++);
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statIssuedInstType[tid][op_class]++;
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iewStage->incrWb(issuing_inst->seqNum);
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} else {
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statFuBusy[op_class]++;
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fuBusy[tid]++;
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@ -77,6 +77,7 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
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//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
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if (isSwitchedOut() || inst->isSquashed()) {
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iewStage->decrWb(inst->seqNum);
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delete state;
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delete pkt;
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return;
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@ -118,6 +118,7 @@ TimingSimpleCPU::quiesce(Event *quiesce_event)
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// an access to complete.
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if (status() == Idle || status() == Running || status() == SwitchedOut) {
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DPRINTF(Config, "Ready to quiesce\n");
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changeState(SimObject::QuiescedTiming);
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return false;
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} else {
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DPRINTF(Config, "Waiting to quiesce\n");
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@ -37,12 +37,10 @@ class DerivO3CPU(BaseCPU):
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
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"to the IEW stage)")
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dispatchWidth = Param.Unsigned("Dispatch width")
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issueWidth = Param.Unsigned("Issue width")
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executeWidth = Param.Unsigned("Execute width")
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executeIntWidth = Param.Unsigned("Integer execute width")
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executeFloatWidth = Param.Unsigned("Floating point execute width")
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executeBranchWidth = Param.Unsigned("Branch execute width")
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executeMemoryWidth = Param.Unsigned("Memory execute width")
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wbWidth = Param.Unsigned("Writeback width")
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wbDepth = Param.Unsigned("Writeback depth")
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fuPool = Param.FUPool(NULL, "Functional Unit pool")
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iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
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